CMSIS Cortex-M4 Peripheral Access Layer Header File for XMC4800 from Infineon.
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| #define | __CM4_REV 0x0200 |
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| #define | __MPU_PRESENT 1 |
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| #define | __NVIC_PRIO_BITS 6 |
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| #define | __Vendor_SysTickConfig 0 |
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| #define | __FPU_PRESENT 1 |
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| #define | WR_REG(reg, mask, pos, val) |
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| #define | WR_REG_SIZE(reg, mask, pos, val, size) |
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| #define | RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos) |
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| #define | RD_REG_SIZE(reg, mask, pos, size) |
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| #define | SET_BIT(reg, pos) (reg |= ((uint32_t)1<<pos)) |
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| #define | CLR_BIT(reg, pos) (reg = reg & (uint32_t)(~((uint32_t)1<<pos)) ) |
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| #define | IRQ_Hdlr_0 SCU_0_IRQHandler |
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| #define | IRQ_Hdlr_1 ERU0_0_IRQHandler |
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| #define | IRQ_Hdlr_2 ERU0_1_IRQHandler |
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| #define | IRQ_Hdlr_3 ERU0_2_IRQHandler |
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| #define | IRQ_Hdlr_4 ERU0_3_IRQHandler |
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| #define | IRQ_Hdlr_5 ERU1_0_IRQHandler |
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| #define | IRQ_Hdlr_6 ERU1_1_IRQHandler |
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| #define | IRQ_Hdlr_7 ERU1_2_IRQHandler |
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| #define | IRQ_Hdlr_8 ERU1_3_IRQHandler |
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| #define | IRQ_Hdlr_12 PMU0_0_IRQHandler |
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| #define | IRQ_Hdlr_14 VADC0_C0_0_IRQHandler |
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| #define | IRQ_Hdlr_15 VADC0_C0_1_IRQHandler |
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| #define | IRQ_Hdlr_16 VADC0_C0_2_IRQHandler |
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| #define | IRQ_Hdlr_17 VADC0_C0_3_IRQHandler |
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| #define | IRQ_Hdlr_18 VADC0_G0_0_IRQHandler |
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| #define | IRQ_Hdlr_19 VADC0_G0_1_IRQHandler |
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| #define | IRQ_Hdlr_20 VADC0_G0_2_IRQHandler |
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| #define | IRQ_Hdlr_21 VADC0_G0_3_IRQHandler |
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| #define | IRQ_Hdlr_22 VADC0_G1_0_IRQHandler |
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| #define | IRQ_Hdlr_23 VADC0_G1_1_IRQHandler |
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| #define | IRQ_Hdlr_24 VADC0_G1_2_IRQHandler |
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| #define | IRQ_Hdlr_25 VADC0_G1_3_IRQHandler |
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| #define | IRQ_Hdlr_26 VADC0_G2_0_IRQHandler |
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| #define | IRQ_Hdlr_27 VADC0_G2_1_IRQHandler |
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| #define | IRQ_Hdlr_28 VADC0_G2_2_IRQHandler |
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| #define | IRQ_Hdlr_29 VADC0_G2_3_IRQHandler |
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| #define | IRQ_Hdlr_30 VADC0_G3_0_IRQHandler |
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| #define | IRQ_Hdlr_31 VADC0_G3_1_IRQHandler |
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| #define | IRQ_Hdlr_32 VADC0_G3_2_IRQHandler |
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| #define | IRQ_Hdlr_33 VADC0_G3_3_IRQHandler |
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| #define | IRQ_Hdlr_34 DSD0_0_IRQHandler |
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| #define | IRQ_Hdlr_35 DSD0_1_IRQHandler |
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| #define | IRQ_Hdlr_36 DSD0_2_IRQHandler |
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| #define | IRQ_Hdlr_37 DSD0_3_IRQHandler |
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| #define | IRQ_Hdlr_38 DSD0_4_IRQHandler |
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| #define | IRQ_Hdlr_39 DSD0_5_IRQHandler |
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| #define | IRQ_Hdlr_40 DSD0_6_IRQHandler |
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| #define | IRQ_Hdlr_41 DSD0_7_IRQHandler |
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| #define | IRQ_Hdlr_42 DAC0_0_IRQHandler |
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| #define | IRQ_Hdlr_43 DAC0_1_IRQHandler |
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| #define | IRQ_Hdlr_44 CCU40_0_IRQHandler |
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| #define | IRQ_Hdlr_45 CCU40_1_IRQHandler |
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| #define | IRQ_Hdlr_46 CCU40_2_IRQHandler |
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| #define | IRQ_Hdlr_47 CCU40_3_IRQHandler |
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| #define | IRQ_Hdlr_48 CCU41_0_IRQHandler |
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| #define | IRQ_Hdlr_49 CCU41_1_IRQHandler |
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| #define | IRQ_Hdlr_50 CCU41_2_IRQHandler |
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| #define | IRQ_Hdlr_51 CCU41_3_IRQHandler |
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| #define | IRQ_Hdlr_52 CCU42_0_IRQHandler |
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| #define | IRQ_Hdlr_53 CCU42_1_IRQHandler |
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| #define | IRQ_Hdlr_54 CCU42_2_IRQHandler |
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| #define | IRQ_Hdlr_55 CCU42_3_IRQHandler |
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| #define | IRQ_Hdlr_56 CCU43_0_IRQHandler |
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| #define | IRQ_Hdlr_57 CCU43_1_IRQHandler |
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| #define | IRQ_Hdlr_58 CCU43_2_IRQHandler |
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| #define | IRQ_Hdlr_59 CCU43_3_IRQHandler |
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| #define | IRQ_Hdlr_60 CCU80_0_IRQHandler |
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| #define | IRQ_Hdlr_61 CCU80_1_IRQHandler |
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| #define | IRQ_Hdlr_62 CCU80_2_IRQHandler |
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| #define | IRQ_Hdlr_63 CCU80_3_IRQHandler |
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| #define | IRQ_Hdlr_64 CCU81_0_IRQHandler |
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| #define | IRQ_Hdlr_65 CCU81_1_IRQHandler |
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| #define | IRQ_Hdlr_66 CCU81_2_IRQHandler |
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| #define | IRQ_Hdlr_67 CCU81_3_IRQHandler |
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| #define | IRQ_Hdlr_68 POSIF0_0_IRQHandler |
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| #define | IRQ_Hdlr_69 POSIF0_1_IRQHandler |
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| #define | IRQ_Hdlr_70 POSIF1_0_IRQHandler |
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| #define | IRQ_Hdlr_71 POSIF1_1_IRQHandler |
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| #define | IRQ_Hdlr_76 CAN0_0_IRQHandler |
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| #define | IRQ_Hdlr_77 CAN0_1_IRQHandler |
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| #define | IRQ_Hdlr_78 CAN0_2_IRQHandler |
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| #define | IRQ_Hdlr_79 CAN0_3_IRQHandler |
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| #define | IRQ_Hdlr_80 CAN0_4_IRQHandler |
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| #define | IRQ_Hdlr_81 CAN0_5_IRQHandler |
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| #define | IRQ_Hdlr_82 CAN0_6_IRQHandler |
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| #define | IRQ_Hdlr_83 CAN0_7_IRQHandler |
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| #define | IRQ_Hdlr_84 USIC0_0_IRQHandler |
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| #define | IRQ_Hdlr_85 USIC0_1_IRQHandler |
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| #define | IRQ_Hdlr_86 USIC0_2_IRQHandler |
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| #define | IRQ_Hdlr_87 USIC0_3_IRQHandler |
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| #define | IRQ_Hdlr_88 USIC0_4_IRQHandler |
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| #define | IRQ_Hdlr_89 USIC0_5_IRQHandler |
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| #define | IRQ_Hdlr_90 USIC1_0_IRQHandler |
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| #define | IRQ_Hdlr_91 USIC1_1_IRQHandler |
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| #define | IRQ_Hdlr_92 USIC1_2_IRQHandler |
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| #define | IRQ_Hdlr_93 USIC1_3_IRQHandler |
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| #define | IRQ_Hdlr_94 USIC1_4_IRQHandler |
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| #define | IRQ_Hdlr_95 USIC1_5_IRQHandler |
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| #define | IRQ_Hdlr_96 USIC2_0_IRQHandler |
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| #define | IRQ_Hdlr_97 USIC2_1_IRQHandler |
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| #define | IRQ_Hdlr_98 USIC2_2_IRQHandler |
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| #define | IRQ_Hdlr_99 USIC2_3_IRQHandler |
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| #define | IRQ_Hdlr_100 USIC2_4_IRQHandler |
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| #define | IRQ_Hdlr_101 USIC2_5_IRQHandler |
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| #define | IRQ_Hdlr_102 LEDTS0_0_IRQHandler |
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| #define | IRQ_Hdlr_104 FCE0_0_IRQHandler |
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| #define | IRQ_Hdlr_105 GPDMA0_0_IRQHandler |
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| #define | IRQ_Hdlr_106 SDMMC0_0_IRQHandler |
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| #define | IRQ_Hdlr_107 USB0_0_IRQHandler |
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| #define | IRQ_Hdlr_108 ETH0_0_IRQHandler |
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| #define | IRQ_Hdlr_109 ECAT0_0_IRQHandler |
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| #define | IRQ_Hdlr_110 GPDMA1_0_IRQHandler |
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| #define | GET_IRQ_HANDLER(N) IRQ_Hdlr_##N |
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| #define | PPB_ACTLR_DISMCYCINT_Pos (0UL) |
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| #define | PPB_ACTLR_DISMCYCINT_Msk (0x1UL) |
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| #define | PPB_ACTLR_DISDEFWBUF_Pos (1UL) |
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| #define | PPB_ACTLR_DISDEFWBUF_Msk (0x2UL) |
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| #define | PPB_ACTLR_DISFOLD_Pos (2UL) |
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| #define | PPB_ACTLR_DISFOLD_Msk (0x4UL) |
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| #define | PPB_ACTLR_DISFPCA_Pos (8UL) |
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| #define | PPB_ACTLR_DISFPCA_Msk (0x100UL) |
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| #define | PPB_ACTLR_DISOOFP_Pos (9UL) |
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| #define | PPB_ACTLR_DISOOFP_Msk (0x200UL) |
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| #define | PPB_SYST_CSR_ENABLE_Pos (0UL) |
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| #define | PPB_SYST_CSR_ENABLE_Msk (0x1UL) |
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| #define | PPB_SYST_CSR_TICKINT_Pos (1UL) |
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| #define | PPB_SYST_CSR_TICKINT_Msk (0x2UL) |
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| #define | PPB_SYST_CSR_CLKSOURCE_Pos (2UL) |
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| #define | PPB_SYST_CSR_CLKSOURCE_Msk (0x4UL) |
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| #define | PPB_SYST_CSR_COUNTFLAG_Pos (16UL) |
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| #define | PPB_SYST_CSR_COUNTFLAG_Msk (0x10000UL) |
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| #define | PPB_SYST_RVR_RELOAD_Pos (0UL) |
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| #define | PPB_SYST_RVR_RELOAD_Msk (0xffffffUL) |
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| #define | PPB_SYST_CVR_CURRENT_Pos (0UL) |
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| #define | PPB_SYST_CVR_CURRENT_Msk (0xffffffUL) |
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| #define | PPB_SYST_CALIB_TENMS_Pos (0UL) |
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| #define | PPB_SYST_CALIB_TENMS_Msk (0xffffffUL) |
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| #define | PPB_SYST_CALIB_SKEW_Pos (30UL) |
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| #define | PPB_SYST_CALIB_SKEW_Msk (0x40000000UL) |
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| #define | PPB_SYST_CALIB_NOREF_Pos (31UL) |
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| #define | PPB_SYST_CALIB_NOREF_Msk (0x80000000UL) |
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| #define | PPB_NVIC_ISER0_SETENA_Pos (0UL) |
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| #define | PPB_NVIC_ISER0_SETENA_Msk (0xffffffffUL) |
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| #define | PPB_NVIC_ISER1_SETENA_Pos (0UL) |
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| #define | PPB_NVIC_ISER1_SETENA_Msk (0xffffffffUL) |
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| #define | PPB_NVIC_ISER2_SETENA_Pos (0UL) |
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| #define | PPB_NVIC_ISER2_SETENA_Msk (0xffffffffUL) |
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| #define | PPB_NVIC_ISER3_SETENA_Pos (0UL) |
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| #define | PPB_NVIC_ISER3_SETENA_Msk (0xffffffffUL) |
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| #define | PPB_NVIC_ICER0_CLRENA_Pos (0UL) |
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| #define | PPB_NVIC_ICER0_CLRENA_Msk (0xffffffffUL) |
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| #define | PPB_NVIC_ICER1_CLRENA_Pos (0UL) |
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| #define | PPB_NVIC_ICER1_CLRENA_Msk (0xffffffffUL) |
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| #define | PPB_NVIC_ICER2_CLRENA_Pos (0UL) |
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| #define | PPB_NVIC_ICER2_CLRENA_Msk (0xffffffffUL) |
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| #define | PPB_NVIC_ICER3_CLRENA_Pos (0UL) |
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| #define | PPB_NVIC_ICER3_CLRENA_Msk (0xffffffffUL) |
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| #define | PPB_NVIC_ISPR0_SETPEND_Pos (0UL) |
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| #define | PPB_NVIC_ISPR0_SETPEND_Msk (0xffffffffUL) |
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| #define | PPB_NVIC_ISPR1_SETPEND_Pos (0UL) |
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| #define | PPB_NVIC_ISPR1_SETPEND_Msk (0xffffffffUL) |
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| #define | PPB_NVIC_ISPR2_SETPEND_Pos (0UL) |
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| #define | PPB_NVIC_ISPR2_SETPEND_Msk (0xffffffffUL) |
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| #define | PPB_NVIC_ISPR3_SETPEND_Pos (0UL) |
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| #define | PPB_NVIC_ISPR3_SETPEND_Msk (0xffffffffUL) |
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| #define | PPB_NVIC_ICPR0_CLRPEND_Pos (0UL) |
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| #define | PPB_NVIC_ICPR0_CLRPEND_Msk (0xffffffffUL) |
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| #define | PPB_NVIC_ICPR1_CLRPEND_Pos (0UL) |
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| #define | PPB_NVIC_ICPR1_CLRPEND_Msk (0xffffffffUL) |
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| #define | PPB_NVIC_ICPR2_CLRPEND_Pos (0UL) |
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| #define | PPB_NVIC_ICPR2_CLRPEND_Msk (0xffffffffUL) |
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| #define | PPB_NVIC_ICPR3_CLRPEND_Pos (0UL) |
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| #define | PPB_NVIC_ICPR3_CLRPEND_Msk (0xffffffffUL) |
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| #define | PPB_NVIC_IABR0_ACTIVE_Pos (0UL) |
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| #define | PPB_NVIC_IABR0_ACTIVE_Msk (0xffffffffUL) |
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| #define | PPB_NVIC_IABR1_ACTIVE_Pos (0UL) |
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| #define | PPB_NVIC_IABR1_ACTIVE_Msk (0xffffffffUL) |
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| #define | PPB_NVIC_IABR2_ACTIVE_Pos (0UL) |
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| #define | PPB_NVIC_IABR2_ACTIVE_Msk (0xffffffffUL) |
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| #define | PPB_NVIC_IABR3_ACTIVE_Pos (0UL) |
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| #define | PPB_NVIC_IABR3_ACTIVE_Msk (0xffffffffUL) |
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| #define | PPB_NVIC_IPR0_PRI_0_Pos (0UL) |
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| #define | PPB_NVIC_IPR0_PRI_0_Msk (0xffUL) |
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| #define | PPB_NVIC_IPR0_PRI_1_Pos (8UL) |
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| #define | PPB_NVIC_IPR0_PRI_1_Msk (0xff00UL) |
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| #define | PPB_NVIC_IPR0_PRI_2_Pos (16UL) |
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| #define | PPB_NVIC_IPR0_PRI_2_Msk (0xff0000UL) |
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| #define | PPB_NVIC_IPR0_PRI_3_Pos (24UL) |
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| #define | PPB_NVIC_IPR0_PRI_3_Msk (0xff000000UL) |
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| #define | PPB_NVIC_IPR1_PRI_0_Pos (0UL) |
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| #define | PPB_NVIC_IPR1_PRI_0_Msk (0xffUL) |
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| #define | PPB_NVIC_IPR1_PRI_1_Pos (8UL) |
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| #define | PPB_NVIC_IPR1_PRI_1_Msk (0xff00UL) |
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| #define | PPB_NVIC_IPR1_PRI_2_Pos (16UL) |
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| #define | PPB_NVIC_IPR1_PRI_2_Msk (0xff0000UL) |
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| #define | PPB_NVIC_IPR1_PRI_3_Pos (24UL) |
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| #define | PPB_NVIC_IPR1_PRI_3_Msk (0xff000000UL) |
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| #define | PPB_NVIC_IPR2_PRI_0_Pos (0UL) |
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| #define | PPB_NVIC_IPR2_PRI_0_Msk (0xffUL) |
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| #define | PPB_NVIC_IPR2_PRI_1_Pos (8UL) |
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| #define | PPB_NVIC_IPR2_PRI_1_Msk (0xff00UL) |
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| #define | PPB_NVIC_IPR2_PRI_2_Pos (16UL) |
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| #define | PPB_NVIC_IPR2_PRI_2_Msk (0xff0000UL) |
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| #define | PPB_NVIC_IPR2_PRI_3_Pos (24UL) |
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| #define | PPB_NVIC_IPR2_PRI_3_Msk (0xff000000UL) |
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| #define | PPB_NVIC_IPR3_PRI_0_Pos (0UL) |
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| #define | PPB_NVIC_IPR3_PRI_0_Msk (0xffUL) |
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| #define | PPB_NVIC_IPR3_PRI_1_Pos (8UL) |
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| #define | PPB_NVIC_IPR3_PRI_1_Msk (0xff00UL) |
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| #define | PPB_NVIC_IPR3_PRI_2_Pos (16UL) |
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| #define | PPB_NVIC_IPR3_PRI_2_Msk (0xff0000UL) |
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| #define | PPB_NVIC_IPR3_PRI_3_Pos (24UL) |
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| #define | PPB_NVIC_IPR3_PRI_3_Msk (0xff000000UL) |
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| #define | PPB_NVIC_IPR4_PRI_0_Pos (0UL) |
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| #define | PPB_NVIC_IPR4_PRI_0_Msk (0xffUL) |
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| #define | PPB_NVIC_IPR4_PRI_1_Pos (8UL) |
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| #define | PPB_NVIC_IPR4_PRI_1_Msk (0xff00UL) |
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| #define | PPB_NVIC_IPR4_PRI_2_Pos (16UL) |
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| #define | PPB_NVIC_IPR4_PRI_2_Msk (0xff0000UL) |
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| #define | PPB_NVIC_IPR4_PRI_3_Pos (24UL) |
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| #define | PPB_NVIC_IPR4_PRI_3_Msk (0xff000000UL) |
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| #define | PPB_NVIC_IPR5_PRI_0_Pos (0UL) |
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| #define | PPB_NVIC_IPR5_PRI_0_Msk (0xffUL) |
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| #define | PPB_NVIC_IPR5_PRI_1_Pos (8UL) |
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| #define | PPB_NVIC_IPR5_PRI_1_Msk (0xff00UL) |
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| #define | PPB_NVIC_IPR5_PRI_2_Pos (16UL) |
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| #define | PPB_NVIC_IPR5_PRI_2_Msk (0xff0000UL) |
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| #define | PPB_NVIC_IPR5_PRI_3_Pos (24UL) |
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| #define | PPB_NVIC_IPR5_PRI_3_Msk (0xff000000UL) |
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| #define | PPB_NVIC_IPR6_PRI_0_Pos (0UL) |
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| #define | PPB_NVIC_IPR6_PRI_0_Msk (0xffUL) |
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| #define | PPB_NVIC_IPR6_PRI_1_Pos (8UL) |
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| #define | PPB_NVIC_IPR6_PRI_1_Msk (0xff00UL) |
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| #define | PPB_NVIC_IPR6_PRI_2_Pos (16UL) |
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| #define | PPB_NVIC_IPR6_PRI_2_Msk (0xff0000UL) |
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| #define | PPB_NVIC_IPR6_PRI_3_Pos (24UL) |
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| #define | PPB_NVIC_IPR6_PRI_3_Msk (0xff000000UL) |
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| #define | PPB_NVIC_IPR7_PRI_0_Pos (0UL) |
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| #define | PPB_NVIC_IPR7_PRI_0_Msk (0xffUL) |
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| #define | PPB_NVIC_IPR7_PRI_1_Pos (8UL) |
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| #define | PPB_NVIC_IPR7_PRI_1_Msk (0xff00UL) |
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| #define | PPB_NVIC_IPR7_PRI_2_Pos (16UL) |
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| #define | PPB_NVIC_IPR7_PRI_2_Msk (0xff0000UL) |
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| #define | PPB_NVIC_IPR7_PRI_3_Pos (24UL) |
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| #define | PPB_NVIC_IPR7_PRI_3_Msk (0xff000000UL) |
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| #define | PPB_NVIC_IPR8_PRI_0_Pos (0UL) |
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| #define | PPB_NVIC_IPR8_PRI_0_Msk (0xffUL) |
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| #define | PPB_NVIC_IPR8_PRI_1_Pos (8UL) |
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| #define | PPB_NVIC_IPR8_PRI_1_Msk (0xff00UL) |
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| #define | PPB_NVIC_IPR8_PRI_2_Pos (16UL) |
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| #define | PPB_NVIC_IPR8_PRI_2_Msk (0xff0000UL) |
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| #define | PPB_NVIC_IPR8_PRI_3_Pos (24UL) |
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| #define | PPB_NVIC_IPR8_PRI_3_Msk (0xff000000UL) |
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| #define | PPB_NVIC_IPR9_PRI_0_Pos (0UL) |
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| #define | PPB_NVIC_IPR9_PRI_0_Msk (0xffUL) |
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| #define | PPB_NVIC_IPR9_PRI_1_Pos (8UL) |
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| #define | PPB_NVIC_IPR9_PRI_1_Msk (0xff00UL) |
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| #define | PPB_NVIC_IPR9_PRI_2_Pos (16UL) |
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| #define | PPB_NVIC_IPR9_PRI_2_Msk (0xff0000UL) |
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| #define | PPB_NVIC_IPR9_PRI_3_Pos (24UL) |
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| #define | PPB_NVIC_IPR9_PRI_3_Msk (0xff000000UL) |
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| #define | PPB_NVIC_IPR10_PRI_0_Pos (0UL) |
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| #define | PPB_NVIC_IPR10_PRI_0_Msk (0xffUL) |
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| #define | PPB_NVIC_IPR10_PRI_1_Pos (8UL) |
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| #define | PPB_NVIC_IPR10_PRI_1_Msk (0xff00UL) |
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| #define | PPB_NVIC_IPR10_PRI_2_Pos (16UL) |
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| #define | PPB_NVIC_IPR10_PRI_2_Msk (0xff0000UL) |
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| #define | PPB_NVIC_IPR10_PRI_3_Pos (24UL) |
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| #define | PPB_NVIC_IPR10_PRI_3_Msk (0xff000000UL) |
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| #define | PPB_NVIC_IPR11_PRI_0_Pos (0UL) |
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| #define | PPB_NVIC_IPR11_PRI_0_Msk (0xffUL) |
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| #define | PPB_NVIC_IPR11_PRI_1_Pos (8UL) |
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| #define | PPB_NVIC_IPR11_PRI_1_Msk (0xff00UL) |
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| #define | PPB_NVIC_IPR11_PRI_2_Pos (16UL) |
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| #define | PPB_NVIC_IPR11_PRI_2_Msk (0xff0000UL) |
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| #define | PPB_NVIC_IPR11_PRI_3_Pos (24UL) |
| |
| #define | PPB_NVIC_IPR11_PRI_3_Msk (0xff000000UL) |
| |
| #define | PPB_NVIC_IPR12_PRI_0_Pos (0UL) |
| |
| #define | PPB_NVIC_IPR12_PRI_0_Msk (0xffUL) |
| |
| #define | PPB_NVIC_IPR12_PRI_1_Pos (8UL) |
| |
| #define | PPB_NVIC_IPR12_PRI_1_Msk (0xff00UL) |
| |
| #define | PPB_NVIC_IPR12_PRI_2_Pos (16UL) |
| |
| #define | PPB_NVIC_IPR12_PRI_2_Msk (0xff0000UL) |
| |
| #define | PPB_NVIC_IPR12_PRI_3_Pos (24UL) |
| |
| #define | PPB_NVIC_IPR12_PRI_3_Msk (0xff000000UL) |
| |
| #define | PPB_NVIC_IPR13_PRI_0_Pos (0UL) |
| |
| #define | PPB_NVIC_IPR13_PRI_0_Msk (0xffUL) |
| |
| #define | PPB_NVIC_IPR13_PRI_1_Pos (8UL) |
| |
| #define | PPB_NVIC_IPR13_PRI_1_Msk (0xff00UL) |
| |
| #define | PPB_NVIC_IPR13_PRI_2_Pos (16UL) |
| |
| #define | PPB_NVIC_IPR13_PRI_2_Msk (0xff0000UL) |
| |
| #define | PPB_NVIC_IPR13_PRI_3_Pos (24UL) |
| |
| #define | PPB_NVIC_IPR13_PRI_3_Msk (0xff000000UL) |
| |
| #define | PPB_NVIC_IPR14_PRI_0_Pos (0UL) |
| |
| #define | PPB_NVIC_IPR14_PRI_0_Msk (0xffUL) |
| |
| #define | PPB_NVIC_IPR14_PRI_1_Pos (8UL) |
| |
| #define | PPB_NVIC_IPR14_PRI_1_Msk (0xff00UL) |
| |
| #define | PPB_NVIC_IPR14_PRI_2_Pos (16UL) |
| |
| #define | PPB_NVIC_IPR14_PRI_2_Msk (0xff0000UL) |
| |
| #define | PPB_NVIC_IPR14_PRI_3_Pos (24UL) |
| |
| #define | PPB_NVIC_IPR14_PRI_3_Msk (0xff000000UL) |
| |
| #define | PPB_NVIC_IPR15_PRI_0_Pos (0UL) |
| |
| #define | PPB_NVIC_IPR15_PRI_0_Msk (0xffUL) |
| |
| #define | PPB_NVIC_IPR15_PRI_1_Pos (8UL) |
| |
| #define | PPB_NVIC_IPR15_PRI_1_Msk (0xff00UL) |
| |
| #define | PPB_NVIC_IPR15_PRI_2_Pos (16UL) |
| |
| #define | PPB_NVIC_IPR15_PRI_2_Msk (0xff0000UL) |
| |
| #define | PPB_NVIC_IPR15_PRI_3_Pos (24UL) |
| |
| #define | PPB_NVIC_IPR15_PRI_3_Msk (0xff000000UL) |
| |
| #define | PPB_NVIC_IPR16_PRI_0_Pos (0UL) |
| |
| #define | PPB_NVIC_IPR16_PRI_0_Msk (0xffUL) |
| |
| #define | PPB_NVIC_IPR16_PRI_1_Pos (8UL) |
| |
| #define | PPB_NVIC_IPR16_PRI_1_Msk (0xff00UL) |
| |
| #define | PPB_NVIC_IPR16_PRI_2_Pos (16UL) |
| |
| #define | PPB_NVIC_IPR16_PRI_2_Msk (0xff0000UL) |
| |
| #define | PPB_NVIC_IPR16_PRI_3_Pos (24UL) |
| |
| #define | PPB_NVIC_IPR16_PRI_3_Msk (0xff000000UL) |
| |
| #define | PPB_NVIC_IPR17_PRI_0_Pos (0UL) |
| |
| #define | PPB_NVIC_IPR17_PRI_0_Msk (0xffUL) |
| |
| #define | PPB_NVIC_IPR17_PRI_1_Pos (8UL) |
| |
| #define | PPB_NVIC_IPR17_PRI_1_Msk (0xff00UL) |
| |
| #define | PPB_NVIC_IPR17_PRI_2_Pos (16UL) |
| |
| #define | PPB_NVIC_IPR17_PRI_2_Msk (0xff0000UL) |
| |
| #define | PPB_NVIC_IPR17_PRI_3_Pos (24UL) |
| |
| #define | PPB_NVIC_IPR17_PRI_3_Msk (0xff000000UL) |
| |
| #define | PPB_NVIC_IPR18_PRI_0_Pos (0UL) |
| |
| #define | PPB_NVIC_IPR18_PRI_0_Msk (0xffUL) |
| |
| #define | PPB_NVIC_IPR18_PRI_1_Pos (8UL) |
| |
| #define | PPB_NVIC_IPR18_PRI_1_Msk (0xff00UL) |
| |
| #define | PPB_NVIC_IPR18_PRI_2_Pos (16UL) |
| |
| #define | PPB_NVIC_IPR18_PRI_2_Msk (0xff0000UL) |
| |
| #define | PPB_NVIC_IPR18_PRI_3_Pos (24UL) |
| |
| #define | PPB_NVIC_IPR18_PRI_3_Msk (0xff000000UL) |
| |
| #define | PPB_NVIC_IPR19_PRI_0_Pos (0UL) |
| |
| #define | PPB_NVIC_IPR19_PRI_0_Msk (0xffUL) |
| |
| #define | PPB_NVIC_IPR19_PRI_1_Pos (8UL) |
| |
| #define | PPB_NVIC_IPR19_PRI_1_Msk (0xff00UL) |
| |
| #define | PPB_NVIC_IPR19_PRI_2_Pos (16UL) |
| |
| #define | PPB_NVIC_IPR19_PRI_2_Msk (0xff0000UL) |
| |
| #define | PPB_NVIC_IPR19_PRI_3_Pos (24UL) |
| |
| #define | PPB_NVIC_IPR19_PRI_3_Msk (0xff000000UL) |
| |
| #define | PPB_NVIC_IPR20_PRI_0_Pos (0UL) |
| |
| #define | PPB_NVIC_IPR20_PRI_0_Msk (0xffUL) |
| |
| #define | PPB_NVIC_IPR20_PRI_1_Pos (8UL) |
| |
| #define | PPB_NVIC_IPR20_PRI_1_Msk (0xff00UL) |
| |
| #define | PPB_NVIC_IPR20_PRI_2_Pos (16UL) |
| |
| #define | PPB_NVIC_IPR20_PRI_2_Msk (0xff0000UL) |
| |
| #define | PPB_NVIC_IPR20_PRI_3_Pos (24UL) |
| |
| #define | PPB_NVIC_IPR20_PRI_3_Msk (0xff000000UL) |
| |
| #define | PPB_NVIC_IPR21_PRI_0_Pos (0UL) |
| |
| #define | PPB_NVIC_IPR21_PRI_0_Msk (0xffUL) |
| |
| #define | PPB_NVIC_IPR21_PRI_1_Pos (8UL) |
| |
| #define | PPB_NVIC_IPR21_PRI_1_Msk (0xff00UL) |
| |
| #define | PPB_NVIC_IPR21_PRI_2_Pos (16UL) |
| |
| #define | PPB_NVIC_IPR21_PRI_2_Msk (0xff0000UL) |
| |
| #define | PPB_NVIC_IPR21_PRI_3_Pos (24UL) |
| |
| #define | PPB_NVIC_IPR21_PRI_3_Msk (0xff000000UL) |
| |
| #define | PPB_NVIC_IPR22_PRI_0_Pos (0UL) |
| |
| #define | PPB_NVIC_IPR22_PRI_0_Msk (0xffUL) |
| |
| #define | PPB_NVIC_IPR22_PRI_1_Pos (8UL) |
| |
| #define | PPB_NVIC_IPR22_PRI_1_Msk (0xff00UL) |
| |
| #define | PPB_NVIC_IPR22_PRI_2_Pos (16UL) |
| |
| #define | PPB_NVIC_IPR22_PRI_2_Msk (0xff0000UL) |
| |
| #define | PPB_NVIC_IPR22_PRI_3_Pos (24UL) |
| |
| #define | PPB_NVIC_IPR22_PRI_3_Msk (0xff000000UL) |
| |
| #define | PPB_NVIC_IPR23_PRI_0_Pos (0UL) |
| |
| #define | PPB_NVIC_IPR23_PRI_0_Msk (0xffUL) |
| |
| #define | PPB_NVIC_IPR23_PRI_1_Pos (8UL) |
| |
| #define | PPB_NVIC_IPR23_PRI_1_Msk (0xff00UL) |
| |
| #define | PPB_NVIC_IPR23_PRI_2_Pos (16UL) |
| |
| #define | PPB_NVIC_IPR23_PRI_2_Msk (0xff0000UL) |
| |
| #define | PPB_NVIC_IPR23_PRI_3_Pos (24UL) |
| |
| #define | PPB_NVIC_IPR23_PRI_3_Msk (0xff000000UL) |
| |
| #define | PPB_NVIC_IPR24_PRI_0_Pos (0UL) |
| |
| #define | PPB_NVIC_IPR24_PRI_0_Msk (0xffUL) |
| |
| #define | PPB_NVIC_IPR24_PRI_1_Pos (8UL) |
| |
| #define | PPB_NVIC_IPR24_PRI_1_Msk (0xff00UL) |
| |
| #define | PPB_NVIC_IPR24_PRI_2_Pos (16UL) |
| |
| #define | PPB_NVIC_IPR24_PRI_2_Msk (0xff0000UL) |
| |
| #define | PPB_NVIC_IPR24_PRI_3_Pos (24UL) |
| |
| #define | PPB_NVIC_IPR24_PRI_3_Msk (0xff000000UL) |
| |
| #define | PPB_NVIC_IPR25_PRI_0_Pos (0UL) |
| |
| #define | PPB_NVIC_IPR25_PRI_0_Msk (0xffUL) |
| |
| #define | PPB_NVIC_IPR25_PRI_1_Pos (8UL) |
| |
| #define | PPB_NVIC_IPR25_PRI_1_Msk (0xff00UL) |
| |
| #define | PPB_NVIC_IPR25_PRI_2_Pos (16UL) |
| |
| #define | PPB_NVIC_IPR25_PRI_2_Msk (0xff0000UL) |
| |
| #define | PPB_NVIC_IPR25_PRI_3_Pos (24UL) |
| |
| #define | PPB_NVIC_IPR25_PRI_3_Msk (0xff000000UL) |
| |
| #define | PPB_NVIC_IPR26_PRI_0_Pos (0UL) |
| |
| #define | PPB_NVIC_IPR26_PRI_0_Msk (0xffUL) |
| |
| #define | PPB_NVIC_IPR26_PRI_1_Pos (8UL) |
| |
| #define | PPB_NVIC_IPR26_PRI_1_Msk (0xff00UL) |
| |
| #define | PPB_NVIC_IPR26_PRI_2_Pos (16UL) |
| |
| #define | PPB_NVIC_IPR26_PRI_2_Msk (0xff0000UL) |
| |
| #define | PPB_NVIC_IPR26_PRI_3_Pos (24UL) |
| |
| #define | PPB_NVIC_IPR26_PRI_3_Msk (0xff000000UL) |
| |
| #define | PPB_NVIC_IPR27_PRI_0_Pos (0UL) |
| |
| #define | PPB_NVIC_IPR27_PRI_0_Msk (0xffUL) |
| |
| #define | PPB_NVIC_IPR27_PRI_1_Pos (8UL) |
| |
| #define | PPB_NVIC_IPR27_PRI_1_Msk (0xff00UL) |
| |
| #define | PPB_NVIC_IPR27_PRI_2_Pos (16UL) |
| |
| #define | PPB_NVIC_IPR27_PRI_2_Msk (0xff0000UL) |
| |
| #define | PPB_NVIC_IPR27_PRI_3_Pos (24UL) |
| |
| #define | PPB_NVIC_IPR27_PRI_3_Msk (0xff000000UL) |
| |
| #define | PPB_CPUID_Revision_Pos (0UL) |
| |
| #define | PPB_CPUID_Revision_Msk (0xfUL) |
| |
| #define | PPB_CPUID_PartNo_Pos (4UL) |
| |
| #define | PPB_CPUID_PartNo_Msk (0xfff0UL) |
| |
| #define | PPB_CPUID_Constant_Pos (16UL) |
| |
| #define | PPB_CPUID_Constant_Msk (0xf0000UL) |
| |
| #define | PPB_CPUID_Variant_Pos (20UL) |
| |
| #define | PPB_CPUID_Variant_Msk (0xf00000UL) |
| |
| #define | PPB_CPUID_Implementer_Pos (24UL) |
| |
| #define | PPB_CPUID_Implementer_Msk (0xff000000UL) |
| |
| #define | PPB_ICSR_VECTACTIVE_Pos (0UL) |
| |
| #define | PPB_ICSR_VECTACTIVE_Msk (0x1ffUL) |
| |
| #define | PPB_ICSR_RETTOBASE_Pos (11UL) |
| |
| #define | PPB_ICSR_RETTOBASE_Msk (0x800UL) |
| |
| #define | PPB_ICSR_VECTPENDING_Pos (12UL) |
| |
| #define | PPB_ICSR_VECTPENDING_Msk (0x3f000UL) |
| |
| #define | PPB_ICSR_ISRPENDING_Pos (22UL) |
| |
| #define | PPB_ICSR_ISRPENDING_Msk (0x400000UL) |
| |
| #define | PPB_ICSR_PENDSTCLR_Pos (25UL) |
| |
| #define | PPB_ICSR_PENDSTCLR_Msk (0x2000000UL) |
| |
| #define | PPB_ICSR_PENDSTSET_Pos (26UL) |
| |
| #define | PPB_ICSR_PENDSTSET_Msk (0x4000000UL) |
| |
| #define | PPB_ICSR_PENDSVCLR_Pos (27UL) |
| |
| #define | PPB_ICSR_PENDSVCLR_Msk (0x8000000UL) |
| |
| #define | PPB_ICSR_PENDSVSET_Pos (28UL) |
| |
| #define | PPB_ICSR_PENDSVSET_Msk (0x10000000UL) |
| |
| #define | PPB_ICSR_NMIPENDSET_Pos (31UL) |
| |
| #define | PPB_ICSR_NMIPENDSET_Msk (0x80000000UL) |
| |
| #define | PPB_VTOR_TBLOFF_Pos (10UL) |
| |
| #define | PPB_VTOR_TBLOFF_Msk (0xfffffc00UL) |
| |
| #define | PPB_AIRCR_VECTRESET_Pos (0UL) |
| |
| #define | PPB_AIRCR_VECTRESET_Msk (0x1UL) |
| |
| #define | PPB_AIRCR_VECTCLRACTIVE_Pos (1UL) |
| |
| #define | PPB_AIRCR_VECTCLRACTIVE_Msk (0x2UL) |
| |
| #define | PPB_AIRCR_SYSRESETREQ_Pos (2UL) |
| |
| #define | PPB_AIRCR_SYSRESETREQ_Msk (0x4UL) |
| |
| #define | PPB_AIRCR_PRIGROUP_Pos (8UL) |
| |
| #define | PPB_AIRCR_PRIGROUP_Msk (0x700UL) |
| |
| #define | PPB_AIRCR_ENDIANNESS_Pos (15UL) |
| |
| #define | PPB_AIRCR_ENDIANNESS_Msk (0x8000UL) |
| |
| #define | PPB_AIRCR_VECTKEY_Pos (16UL) |
| |
| #define | PPB_AIRCR_VECTKEY_Msk (0xffff0000UL) |
| |
| #define | PPB_SCR_SLEEPONEXIT_Pos (1UL) |
| |
| #define | PPB_SCR_SLEEPONEXIT_Msk (0x2UL) |
| |
| #define | PPB_SCR_SLEEPDEEP_Pos (2UL) |
| |
| #define | PPB_SCR_SLEEPDEEP_Msk (0x4UL) |
| |
| #define | PPB_SCR_SEVONPEND_Pos (4UL) |
| |
| #define | PPB_SCR_SEVONPEND_Msk (0x10UL) |
| |
| #define | PPB_CCR_NONBASETHRDENA_Pos (0UL) |
| |
| #define | PPB_CCR_NONBASETHRDENA_Msk (0x1UL) |
| |
| #define | PPB_CCR_USERSETMPEND_Pos (1UL) |
| |
| #define | PPB_CCR_USERSETMPEND_Msk (0x2UL) |
| |
| #define | PPB_CCR_UNALIGN_TRP_Pos (3UL) |
| |
| #define | PPB_CCR_UNALIGN_TRP_Msk (0x8UL) |
| |
| #define | PPB_CCR_DIV_0_TRP_Pos (4UL) |
| |
| #define | PPB_CCR_DIV_0_TRP_Msk (0x10UL) |
| |
| #define | PPB_CCR_BFHFNMIGN_Pos (8UL) |
| |
| #define | PPB_CCR_BFHFNMIGN_Msk (0x100UL) |
| |
| #define | PPB_CCR_STKALIGN_Pos (9UL) |
| |
| #define | PPB_CCR_STKALIGN_Msk (0x200UL) |
| |
| #define | PPB_SHPR1_PRI_4_Pos (0UL) |
| |
| #define | PPB_SHPR1_PRI_4_Msk (0xffUL) |
| |
| #define | PPB_SHPR1_PRI_5_Pos (8UL) |
| |
| #define | PPB_SHPR1_PRI_5_Msk (0xff00UL) |
| |
| #define | PPB_SHPR1_PRI_6_Pos (16UL) |
| |
| #define | PPB_SHPR1_PRI_6_Msk (0xff0000UL) |
| |
| #define | PPB_SHPR2_PRI_11_Pos (24UL) |
| |
| #define | PPB_SHPR2_PRI_11_Msk (0xff000000UL) |
| |
| #define | PPB_SHPR3_PRI_14_Pos (16UL) |
| |
| #define | PPB_SHPR3_PRI_14_Msk (0xff0000UL) |
| |
| #define | PPB_SHPR3_PRI_15_Pos (24UL) |
| |
| #define | PPB_SHPR3_PRI_15_Msk (0xff000000UL) |
| |
| #define | PPB_SHCSR_MEMFAULTACT_Pos (0UL) |
| |
| #define | PPB_SHCSR_MEMFAULTACT_Msk (0x1UL) |
| |
| #define | PPB_SHCSR_BUSFAULTACT_Pos (1UL) |
| |
| #define | PPB_SHCSR_BUSFAULTACT_Msk (0x2UL) |
| |
| #define | PPB_SHCSR_USGFAULTACT_Pos (3UL) |
| |
| #define | PPB_SHCSR_USGFAULTACT_Msk (0x8UL) |
| |
| #define | PPB_SHCSR_SVCALLACT_Pos (7UL) |
| |
| #define | PPB_SHCSR_SVCALLACT_Msk (0x80UL) |
| |
| #define | PPB_SHCSR_MONITORACT_Pos (8UL) |
| |
| #define | PPB_SHCSR_MONITORACT_Msk (0x100UL) |
| |
| #define | PPB_SHCSR_PENDSVACT_Pos (10UL) |
| |
| #define | PPB_SHCSR_PENDSVACT_Msk (0x400UL) |
| |
| #define | PPB_SHCSR_SYSTICKACT_Pos (11UL) |
| |
| #define | PPB_SHCSR_SYSTICKACT_Msk (0x800UL) |
| |
| #define | PPB_SHCSR_USGFAULTPENDED_Pos (12UL) |
| |
| #define | PPB_SHCSR_USGFAULTPENDED_Msk (0x1000UL) |
| |
| #define | PPB_SHCSR_MEMFAULTPENDED_Pos (13UL) |
| |
| #define | PPB_SHCSR_MEMFAULTPENDED_Msk (0x2000UL) |
| |
| #define | PPB_SHCSR_BUSFAULTPENDED_Pos (14UL) |
| |
| #define | PPB_SHCSR_BUSFAULTPENDED_Msk (0x4000UL) |
| |
| #define | PPB_SHCSR_SVCALLPENDED_Pos (15UL) |
| |
| #define | PPB_SHCSR_SVCALLPENDED_Msk (0x8000UL) |
| |
| #define | PPB_SHCSR_MEMFAULTENA_Pos (16UL) |
| |
| #define | PPB_SHCSR_MEMFAULTENA_Msk (0x10000UL) |
| |
| #define | PPB_SHCSR_BUSFAULTENA_Pos (17UL) |
| |
| #define | PPB_SHCSR_BUSFAULTENA_Msk (0x20000UL) |
| |
| #define | PPB_SHCSR_USGFAULTENA_Pos (18UL) |
| |
| #define | PPB_SHCSR_USGFAULTENA_Msk (0x40000UL) |
| |
| #define | PPB_CFSR_IACCVIOL_Pos (0UL) |
| |
| #define | PPB_CFSR_IACCVIOL_Msk (0x1UL) |
| |
| #define | PPB_CFSR_DACCVIOL_Pos (1UL) |
| |
| #define | PPB_CFSR_DACCVIOL_Msk (0x2UL) |
| |
| #define | PPB_CFSR_MUNSTKERR_Pos (3UL) |
| |
| #define | PPB_CFSR_MUNSTKERR_Msk (0x8UL) |
| |
| #define | PPB_CFSR_MSTKERR_Pos (4UL) |
| |
| #define | PPB_CFSR_MSTKERR_Msk (0x10UL) |
| |
| #define | PPB_CFSR_MLSPERR_Pos (5UL) |
| |
| #define | PPB_CFSR_MLSPERR_Msk (0x20UL) |
| |
| #define | PPB_CFSR_MMARVALID_Pos (7UL) |
| |
| #define | PPB_CFSR_MMARVALID_Msk (0x80UL) |
| |
| #define | PPB_CFSR_IBUSERR_Pos (8UL) |
| |
| #define | PPB_CFSR_IBUSERR_Msk (0x100UL) |
| |
| #define | PPB_CFSR_PRECISERR_Pos (9UL) |
| |
| #define | PPB_CFSR_PRECISERR_Msk (0x200UL) |
| |
| #define | PPB_CFSR_IMPRECISERR_Pos (10UL) |
| |
| #define | PPB_CFSR_IMPRECISERR_Msk (0x400UL) |
| |
| #define | PPB_CFSR_UNSTKERR_Pos (11UL) |
| |
| #define | PPB_CFSR_UNSTKERR_Msk (0x800UL) |
| |
| #define | PPB_CFSR_STKERR_Pos (12UL) |
| |
| #define | PPB_CFSR_STKERR_Msk (0x1000UL) |
| |
| #define | PPB_CFSR_LSPERR_Pos (13UL) |
| |
| #define | PPB_CFSR_LSPERR_Msk (0x2000UL) |
| |
| #define | PPB_CFSR_BFARVALID_Pos (15UL) |
| |
| #define | PPB_CFSR_BFARVALID_Msk (0x8000UL) |
| |
| #define | PPB_CFSR_UNDEFINSTR_Pos (16UL) |
| |
| #define | PPB_CFSR_UNDEFINSTR_Msk (0x10000UL) |
| |
| #define | PPB_CFSR_INVSTATE_Pos (17UL) |
| |
| #define | PPB_CFSR_INVSTATE_Msk (0x20000UL) |
| |
| #define | PPB_CFSR_INVPC_Pos (18UL) |
| |
| #define | PPB_CFSR_INVPC_Msk (0x40000UL) |
| |
| #define | PPB_CFSR_NOCP_Pos (19UL) |
| |
| #define | PPB_CFSR_NOCP_Msk (0x80000UL) |
| |
| #define | PPB_CFSR_UNALIGNED_Pos (24UL) |
| |
| #define | PPB_CFSR_UNALIGNED_Msk (0x1000000UL) |
| |
| #define | PPB_CFSR_DIVBYZERO_Pos (25UL) |
| |
| #define | PPB_CFSR_DIVBYZERO_Msk (0x2000000UL) |
| |
| #define | PPB_HFSR_VECTTBL_Pos (1UL) |
| |
| #define | PPB_HFSR_VECTTBL_Msk (0x2UL) |
| |
| #define | PPB_HFSR_FORCED_Pos (30UL) |
| |
| #define | PPB_HFSR_FORCED_Msk (0x40000000UL) |
| |
| #define | PPB_HFSR_DEBUGEVT_Pos (31UL) |
| |
| #define | PPB_HFSR_DEBUGEVT_Msk (0x80000000UL) |
| |
| #define | PPB_MMFAR_ADDRESS_Pos (0UL) |
| |
| #define | PPB_MMFAR_ADDRESS_Msk (0xffffffffUL) |
| |
| #define | PPB_BFAR_ADDRESS_Pos (0UL) |
| |
| #define | PPB_BFAR_ADDRESS_Msk (0xffffffffUL) |
| |
| #define | PPB_AFSR_VALUE_Pos (0UL) |
| |
| #define | PPB_AFSR_VALUE_Msk (0xffffffffUL) |
| |
| #define | PPB_CPACR_CP10_Pos (20UL) |
| |
| #define | PPB_CPACR_CP10_Msk (0x300000UL) |
| |
| #define | PPB_CPACR_CP11_Pos (22UL) |
| |
| #define | PPB_CPACR_CP11_Msk (0xc00000UL) |
| |
| #define | PPB_MPU_TYPE_SEPARATE_Pos (0UL) |
| |
| #define | PPB_MPU_TYPE_SEPARATE_Msk (0x1UL) |
| |
| #define | PPB_MPU_TYPE_DREGION_Pos (8UL) |
| |
| #define | PPB_MPU_TYPE_DREGION_Msk (0xff00UL) |
| |
| #define | PPB_MPU_TYPE_IREGION_Pos (16UL) |
| |
| #define | PPB_MPU_TYPE_IREGION_Msk (0xff0000UL) |
| |
| #define | PPB_MPU_CTRL_ENABLE_Pos (0UL) |
| |
| #define | PPB_MPU_CTRL_ENABLE_Msk (0x1UL) |
| |
| #define | PPB_MPU_CTRL_HFNMIENA_Pos (1UL) |
| |
| #define | PPB_MPU_CTRL_HFNMIENA_Msk (0x2UL) |
| |
| #define | PPB_MPU_CTRL_PRIVDEFENA_Pos (2UL) |
| |
| #define | PPB_MPU_CTRL_PRIVDEFENA_Msk (0x4UL) |
| |
| #define | PPB_MPU_RNR_REGION_Pos (0UL) |
| |
| #define | PPB_MPU_RNR_REGION_Msk (0xffUL) |
| |
| #define | PPB_MPU_RBAR_REGION_Pos (0UL) |
| |
| #define | PPB_MPU_RBAR_REGION_Msk (0xfUL) |
| |
| #define | PPB_MPU_RBAR_VALID_Pos (4UL) |
| |
| #define | PPB_MPU_RBAR_VALID_Msk (0x10UL) |
| |
| #define | PPB_MPU_RBAR_ADDR_Pos (9UL) |
| |
| #define | PPB_MPU_RBAR_ADDR_Msk (0xfffffe00UL) |
| |
| #define | PPB_MPU_RASR_ENABLE_Pos (0UL) |
| |
| #define | PPB_MPU_RASR_ENABLE_Msk (0x1UL) |
| |
| #define | PPB_MPU_RASR_SIZE_Pos (1UL) |
| |
| #define | PPB_MPU_RASR_SIZE_Msk (0x3eUL) |
| |
| #define | PPB_MPU_RASR_SRD_Pos (8UL) |
| |
| #define | PPB_MPU_RASR_SRD_Msk (0xff00UL) |
| |
| #define | PPB_MPU_RASR_B_Pos (16UL) |
| |
| #define | PPB_MPU_RASR_B_Msk (0x10000UL) |
| |
| #define | PPB_MPU_RASR_C_Pos (17UL) |
| |
| #define | PPB_MPU_RASR_C_Msk (0x20000UL) |
| |
| #define | PPB_MPU_RASR_S_Pos (18UL) |
| |
| #define | PPB_MPU_RASR_S_Msk (0x40000UL) |
| |
| #define | PPB_MPU_RASR_TEX_Pos (19UL) |
| |
| #define | PPB_MPU_RASR_TEX_Msk (0x380000UL) |
| |
| #define | PPB_MPU_RASR_AP_Pos (24UL) |
| |
| #define | PPB_MPU_RASR_AP_Msk (0x7000000UL) |
| |
| #define | PPB_MPU_RASR_XN_Pos (28UL) |
| |
| #define | PPB_MPU_RASR_XN_Msk (0x10000000UL) |
| |
| #define | PPB_MPU_RBAR_A1_REGION_Pos (0UL) |
| |
| #define | PPB_MPU_RBAR_A1_REGION_Msk (0xfUL) |
| |
| #define | PPB_MPU_RBAR_A1_VALID_Pos (4UL) |
| |
| #define | PPB_MPU_RBAR_A1_VALID_Msk (0x10UL) |
| |
| #define | PPB_MPU_RBAR_A1_ADDR_Pos (9UL) |
| |
| #define | PPB_MPU_RBAR_A1_ADDR_Msk (0xfffffe00UL) |
| |
| #define | PPB_MPU_RASR_A1_ENABLE_Pos (0UL) |
| |
| #define | PPB_MPU_RASR_A1_ENABLE_Msk (0x1UL) |
| |
| #define | PPB_MPU_RASR_A1_SIZE_Pos (1UL) |
| |
| #define | PPB_MPU_RASR_A1_SIZE_Msk (0x3eUL) |
| |
| #define | PPB_MPU_RASR_A1_SRD_Pos (8UL) |
| |
| #define | PPB_MPU_RASR_A1_SRD_Msk (0xff00UL) |
| |
| #define | PPB_MPU_RASR_A1_B_Pos (16UL) |
| |
| #define | PPB_MPU_RASR_A1_B_Msk (0x10000UL) |
| |
| #define | PPB_MPU_RASR_A1_C_Pos (17UL) |
| |
| #define | PPB_MPU_RASR_A1_C_Msk (0x20000UL) |
| |
| #define | PPB_MPU_RASR_A1_S_Pos (18UL) |
| |
| #define | PPB_MPU_RASR_A1_S_Msk (0x40000UL) |
| |
| #define | PPB_MPU_RASR_A1_TEX_Pos (19UL) |
| |
| #define | PPB_MPU_RASR_A1_TEX_Msk (0x380000UL) |
| |
| #define | PPB_MPU_RASR_A1_AP_Pos (24UL) |
| |
| #define | PPB_MPU_RASR_A1_AP_Msk (0x7000000UL) |
| |
| #define | PPB_MPU_RASR_A1_XN_Pos (28UL) |
| |
| #define | PPB_MPU_RASR_A1_XN_Msk (0x10000000UL) |
| |
| #define | PPB_MPU_RBAR_A2_REGION_Pos (0UL) |
| |
| #define | PPB_MPU_RBAR_A2_REGION_Msk (0xfUL) |
| |
| #define | PPB_MPU_RBAR_A2_VALID_Pos (4UL) |
| |
| #define | PPB_MPU_RBAR_A2_VALID_Msk (0x10UL) |
| |
| #define | PPB_MPU_RBAR_A2_ADDR_Pos (9UL) |
| |
| #define | PPB_MPU_RBAR_A2_ADDR_Msk (0xfffffe00UL) |
| |
| #define | PPB_MPU_RASR_A2_ENABLE_Pos (0UL) |
| |
| #define | PPB_MPU_RASR_A2_ENABLE_Msk (0x1UL) |
| |
| #define | PPB_MPU_RASR_A2_SIZE_Pos (1UL) |
| |
| #define | PPB_MPU_RASR_A2_SIZE_Msk (0x3eUL) |
| |
| #define | PPB_MPU_RASR_A2_SRD_Pos (8UL) |
| |
| #define | PPB_MPU_RASR_A2_SRD_Msk (0xff00UL) |
| |
| #define | PPB_MPU_RASR_A2_B_Pos (16UL) |
| |
| #define | PPB_MPU_RASR_A2_B_Msk (0x10000UL) |
| |
| #define | PPB_MPU_RASR_A2_C_Pos (17UL) |
| |
| #define | PPB_MPU_RASR_A2_C_Msk (0x20000UL) |
| |
| #define | PPB_MPU_RASR_A2_S_Pos (18UL) |
| |
| #define | PPB_MPU_RASR_A2_S_Msk (0x40000UL) |
| |
| #define | PPB_MPU_RASR_A2_TEX_Pos (19UL) |
| |
| #define | PPB_MPU_RASR_A2_TEX_Msk (0x380000UL) |
| |
| #define | PPB_MPU_RASR_A2_AP_Pos (24UL) |
| |
| #define | PPB_MPU_RASR_A2_AP_Msk (0x7000000UL) |
| |
| #define | PPB_MPU_RASR_A2_XN_Pos (28UL) |
| |
| #define | PPB_MPU_RASR_A2_XN_Msk (0x10000000UL) |
| |
| #define | PPB_MPU_RBAR_A3_REGION_Pos (0UL) |
| |
| #define | PPB_MPU_RBAR_A3_REGION_Msk (0xfUL) |
| |
| #define | PPB_MPU_RBAR_A3_VALID_Pos (4UL) |
| |
| #define | PPB_MPU_RBAR_A3_VALID_Msk (0x10UL) |
| |
| #define | PPB_MPU_RBAR_A3_ADDR_Pos (9UL) |
| |
| #define | PPB_MPU_RBAR_A3_ADDR_Msk (0xfffffe00UL) |
| |
| #define | PPB_MPU_RASR_A3_ENABLE_Pos (0UL) |
| |
| #define | PPB_MPU_RASR_A3_ENABLE_Msk (0x1UL) |
| |
| #define | PPB_MPU_RASR_A3_SIZE_Pos (1UL) |
| |
| #define | PPB_MPU_RASR_A3_SIZE_Msk (0x3eUL) |
| |
| #define | PPB_MPU_RASR_A3_SRD_Pos (8UL) |
| |
| #define | PPB_MPU_RASR_A3_SRD_Msk (0xff00UL) |
| |
| #define | PPB_MPU_RASR_A3_B_Pos (16UL) |
| |
| #define | PPB_MPU_RASR_A3_B_Msk (0x10000UL) |
| |
| #define | PPB_MPU_RASR_A3_C_Pos (17UL) |
| |
| #define | PPB_MPU_RASR_A3_C_Msk (0x20000UL) |
| |
| #define | PPB_MPU_RASR_A3_S_Pos (18UL) |
| |
| #define | PPB_MPU_RASR_A3_S_Msk (0x40000UL) |
| |
| #define | PPB_MPU_RASR_A3_TEX_Pos (19UL) |
| |
| #define | PPB_MPU_RASR_A3_TEX_Msk (0x380000UL) |
| |
| #define | PPB_MPU_RASR_A3_AP_Pos (24UL) |
| |
| #define | PPB_MPU_RASR_A3_AP_Msk (0x7000000UL) |
| |
| #define | PPB_MPU_RASR_A3_XN_Pos (28UL) |
| |
| #define | PPB_MPU_RASR_A3_XN_Msk (0x10000000UL) |
| |
| #define | PPB_STIR_INTID_Pos (0UL) |
| |
| #define | PPB_STIR_INTID_Msk (0x1ffUL) |
| |
| #define | PPB_FPCCR_LSPACT_Pos (0UL) |
| |
| #define | PPB_FPCCR_LSPACT_Msk (0x1UL) |
| |
| #define | PPB_FPCCR_USER_Pos (1UL) |
| |
| #define | PPB_FPCCR_USER_Msk (0x2UL) |
| |
| #define | PPB_FPCCR_THREAD_Pos (3UL) |
| |
| #define | PPB_FPCCR_THREAD_Msk (0x8UL) |
| |
| #define | PPB_FPCCR_HFRDY_Pos (4UL) |
| |
| #define | PPB_FPCCR_HFRDY_Msk (0x10UL) |
| |
| #define | PPB_FPCCR_MMRDY_Pos (5UL) |
| |
| #define | PPB_FPCCR_MMRDY_Msk (0x20UL) |
| |
| #define | PPB_FPCCR_BFRDY_Pos (6UL) |
| |
| #define | PPB_FPCCR_BFRDY_Msk (0x40UL) |
| |
| #define | PPB_FPCCR_MONRDY_Pos (8UL) |
| |
| #define | PPB_FPCCR_MONRDY_Msk (0x100UL) |
| |
| #define | PPB_FPCCR_LSPEN_Pos (30UL) |
| |
| #define | PPB_FPCCR_LSPEN_Msk (0x40000000UL) |
| |
| #define | PPB_FPCCR_ASPEN_Pos (31UL) |
| |
| #define | PPB_FPCCR_ASPEN_Msk (0x80000000UL) |
| |
| #define | PPB_FPCAR_ADDRESS_Pos (3UL) |
| |
| #define | PPB_FPCAR_ADDRESS_Msk (0xfffffff8UL) |
| |
| #define | PPB_FPDSCR_RMode_Pos (22UL) |
| |
| #define | PPB_FPDSCR_RMode_Msk (0xc00000UL) |
| |
| #define | PPB_FPDSCR_FZ_Pos (24UL) |
| |
| #define | PPB_FPDSCR_FZ_Msk (0x1000000UL) |
| |
| #define | PPB_FPDSCR_DN_Pos (25UL) |
| |
| #define | PPB_FPDSCR_DN_Msk (0x2000000UL) |
| |
| #define | PPB_FPDSCR_AHP_Pos (26UL) |
| |
| #define | PPB_FPDSCR_AHP_Msk (0x4000000UL) |
| |
| #define | DLR_OVRSTAT_LN0_Pos (0UL) |
| |
| #define | DLR_OVRSTAT_LN0_Msk (0x1UL) |
| |
| #define | DLR_OVRSTAT_LN1_Pos (1UL) |
| |
| #define | DLR_OVRSTAT_LN1_Msk (0x2UL) |
| |
| #define | DLR_OVRSTAT_LN2_Pos (2UL) |
| |
| #define | DLR_OVRSTAT_LN2_Msk (0x4UL) |
| |
| #define | DLR_OVRSTAT_LN3_Pos (3UL) |
| |
| #define | DLR_OVRSTAT_LN3_Msk (0x8UL) |
| |
| #define | DLR_OVRSTAT_LN4_Pos (4UL) |
| |
| #define | DLR_OVRSTAT_LN4_Msk (0x10UL) |
| |
| #define | DLR_OVRSTAT_LN5_Pos (5UL) |
| |
| #define | DLR_OVRSTAT_LN5_Msk (0x20UL) |
| |
| #define | DLR_OVRSTAT_LN6_Pos (6UL) |
| |
| #define | DLR_OVRSTAT_LN6_Msk (0x40UL) |
| |
| #define | DLR_OVRSTAT_LN7_Pos (7UL) |
| |
| #define | DLR_OVRSTAT_LN7_Msk (0x80UL) |
| |
| #define | DLR_OVRSTAT_LN8_Pos (8UL) |
| |
| #define | DLR_OVRSTAT_LN8_Msk (0x100UL) |
| |
| #define | DLR_OVRSTAT_LN9_Pos (9UL) |
| |
| #define | DLR_OVRSTAT_LN9_Msk (0x200UL) |
| |
| #define | DLR_OVRSTAT_LN10_Pos (10UL) |
| |
| #define | DLR_OVRSTAT_LN10_Msk (0x400UL) |
| |
| #define | DLR_OVRSTAT_LN11_Pos (11UL) |
| |
| #define | DLR_OVRSTAT_LN11_Msk (0x800UL) |
| |
| #define | DLR_OVRCLR_LN0_Pos (0UL) |
| |
| #define | DLR_OVRCLR_LN0_Msk (0x1UL) |
| |
| #define | DLR_OVRCLR_LN1_Pos (1UL) |
| |
| #define | DLR_OVRCLR_LN1_Msk (0x2UL) |
| |
| #define | DLR_OVRCLR_LN2_Pos (2UL) |
| |
| #define | DLR_OVRCLR_LN2_Msk (0x4UL) |
| |
| #define | DLR_OVRCLR_LN3_Pos (3UL) |
| |
| #define | DLR_OVRCLR_LN3_Msk (0x8UL) |
| |
| #define | DLR_OVRCLR_LN4_Pos (4UL) |
| |
| #define | DLR_OVRCLR_LN4_Msk (0x10UL) |
| |
| #define | DLR_OVRCLR_LN5_Pos (5UL) |
| |
| #define | DLR_OVRCLR_LN5_Msk (0x20UL) |
| |
| #define | DLR_OVRCLR_LN6_Pos (6UL) |
| |
| #define | DLR_OVRCLR_LN6_Msk (0x40UL) |
| |
| #define | DLR_OVRCLR_LN7_Pos (7UL) |
| |
| #define | DLR_OVRCLR_LN7_Msk (0x80UL) |
| |
| #define | DLR_OVRCLR_LN8_Pos (8UL) |
| |
| #define | DLR_OVRCLR_LN8_Msk (0x100UL) |
| |
| #define | DLR_OVRCLR_LN9_Pos (9UL) |
| |
| #define | DLR_OVRCLR_LN9_Msk (0x200UL) |
| |
| #define | DLR_OVRCLR_LN10_Pos (10UL) |
| |
| #define | DLR_OVRCLR_LN10_Msk (0x400UL) |
| |
| #define | DLR_OVRCLR_LN11_Pos (11UL) |
| |
| #define | DLR_OVRCLR_LN11_Msk (0x800UL) |
| |
| #define | DLR_SRSEL0_RS0_Pos (0UL) |
| |
| #define | DLR_SRSEL0_RS0_Msk (0xfUL) |
| |
| #define | DLR_SRSEL0_RS1_Pos (4UL) |
| |
| #define | DLR_SRSEL0_RS1_Msk (0xf0UL) |
| |
| #define | DLR_SRSEL0_RS2_Pos (8UL) |
| |
| #define | DLR_SRSEL0_RS2_Msk (0xf00UL) |
| |
| #define | DLR_SRSEL0_RS3_Pos (12UL) |
| |
| #define | DLR_SRSEL0_RS3_Msk (0xf000UL) |
| |
| #define | DLR_SRSEL0_RS4_Pos (16UL) |
| |
| #define | DLR_SRSEL0_RS4_Msk (0xf0000UL) |
| |
| #define | DLR_SRSEL0_RS5_Pos (20UL) |
| |
| #define | DLR_SRSEL0_RS5_Msk (0xf00000UL) |
| |
| #define | DLR_SRSEL0_RS6_Pos (24UL) |
| |
| #define | DLR_SRSEL0_RS6_Msk (0xf000000UL) |
| |
| #define | DLR_SRSEL0_RS7_Pos (28UL) |
| |
| #define | DLR_SRSEL0_RS7_Msk (0xf0000000UL) |
| |
| #define | DLR_SRSEL1_RS8_Pos (0UL) |
| |
| #define | DLR_SRSEL1_RS8_Msk (0xfUL) |
| |
| #define | DLR_SRSEL1_RS9_Pos (4UL) |
| |
| #define | DLR_SRSEL1_RS9_Msk (0xf0UL) |
| |
| #define | DLR_SRSEL1_RS10_Pos (8UL) |
| |
| #define | DLR_SRSEL1_RS10_Msk (0xf00UL) |
| |
| #define | DLR_SRSEL1_RS11_Pos (12UL) |
| |
| #define | DLR_SRSEL1_RS11_Msk (0xf000UL) |
| |
| #define | DLR_LNEN_LN0_Pos (0UL) |
| |
| #define | DLR_LNEN_LN0_Msk (0x1UL) |
| |
| #define | DLR_LNEN_LN1_Pos (1UL) |
| |
| #define | DLR_LNEN_LN1_Msk (0x2UL) |
| |
| #define | DLR_LNEN_LN2_Pos (2UL) |
| |
| #define | DLR_LNEN_LN2_Msk (0x4UL) |
| |
| #define | DLR_LNEN_LN3_Pos (3UL) |
| |
| #define | DLR_LNEN_LN3_Msk (0x8UL) |
| |
| #define | DLR_LNEN_LN4_Pos (4UL) |
| |
| #define | DLR_LNEN_LN4_Msk (0x10UL) |
| |
| #define | DLR_LNEN_LN5_Pos (5UL) |
| |
| #define | DLR_LNEN_LN5_Msk (0x20UL) |
| |
| #define | DLR_LNEN_LN6_Pos (6UL) |
| |
| #define | DLR_LNEN_LN6_Msk (0x40UL) |
| |
| #define | DLR_LNEN_LN7_Pos (7UL) |
| |
| #define | DLR_LNEN_LN7_Msk (0x80UL) |
| |
| #define | DLR_LNEN_LN8_Pos (8UL) |
| |
| #define | DLR_LNEN_LN8_Msk (0x100UL) |
| |
| #define | DLR_LNEN_LN9_Pos (9UL) |
| |
| #define | DLR_LNEN_LN9_Msk (0x200UL) |
| |
| #define | DLR_LNEN_LN10_Pos (10UL) |
| |
| #define | DLR_LNEN_LN10_Msk (0x400UL) |
| |
| #define | DLR_LNEN_LN11_Pos (11UL) |
| |
| #define | DLR_LNEN_LN11_Msk (0x800UL) |
| |
| #define | ERU_EXISEL_EXS0A_Pos (0UL) |
| |
| #define | ERU_EXISEL_EXS0A_Msk (0x3UL) |
| |
| #define | ERU_EXISEL_EXS0B_Pos (2UL) |
| |
| #define | ERU_EXISEL_EXS0B_Msk (0xcUL) |
| |
| #define | ERU_EXISEL_EXS1A_Pos (4UL) |
| |
| #define | ERU_EXISEL_EXS1A_Msk (0x30UL) |
| |
| #define | ERU_EXISEL_EXS1B_Pos (6UL) |
| |
| #define | ERU_EXISEL_EXS1B_Msk (0xc0UL) |
| |
| #define | ERU_EXISEL_EXS2A_Pos (8UL) |
| |
| #define | ERU_EXISEL_EXS2A_Msk (0x300UL) |
| |
| #define | ERU_EXISEL_EXS2B_Pos (10UL) |
| |
| #define | ERU_EXISEL_EXS2B_Msk (0xc00UL) |
| |
| #define | ERU_EXISEL_EXS3A_Pos (12UL) |
| |
| #define | ERU_EXISEL_EXS3A_Msk (0x3000UL) |
| |
| #define | ERU_EXISEL_EXS3B_Pos (14UL) |
| |
| #define | ERU_EXISEL_EXS3B_Msk (0xc000UL) |
| |
| #define | ERU_EXICON_PE_Pos (0UL) |
| |
| #define | ERU_EXICON_PE_Msk (0x1UL) |
| |
| #define | ERU_EXICON_LD_Pos (1UL) |
| |
| #define | ERU_EXICON_LD_Msk (0x2UL) |
| |
| #define | ERU_EXICON_RE_Pos (2UL) |
| |
| #define | ERU_EXICON_RE_Msk (0x4UL) |
| |
| #define | ERU_EXICON_FE_Pos (3UL) |
| |
| #define | ERU_EXICON_FE_Msk (0x8UL) |
| |
| #define | ERU_EXICON_OCS_Pos (4UL) |
| |
| #define | ERU_EXICON_OCS_Msk (0x70UL) |
| |
| #define | ERU_EXICON_FL_Pos (7UL) |
| |
| #define | ERU_EXICON_FL_Msk (0x80UL) |
| |
| #define | ERU_EXICON_SS_Pos (8UL) |
| |
| #define | ERU_EXICON_SS_Msk (0x300UL) |
| |
| #define | ERU_EXICON_NA_Pos (10UL) |
| |
| #define | ERU_EXICON_NA_Msk (0x400UL) |
| |
| #define | ERU_EXICON_NB_Pos (11UL) |
| |
| #define | ERU_EXICON_NB_Msk (0x800UL) |
| |
| #define | ERU_EXOCON_ISS_Pos (0UL) |
| |
| #define | ERU_EXOCON_ISS_Msk (0x3UL) |
| |
| #define | ERU_EXOCON_GEEN_Pos (2UL) |
| |
| #define | ERU_EXOCON_GEEN_Msk (0x4UL) |
| |
| #define | ERU_EXOCON_PDR_Pos (3UL) |
| |
| #define | ERU_EXOCON_PDR_Msk (0x8UL) |
| |
| #define | ERU_EXOCON_GP_Pos (4UL) |
| |
| #define | ERU_EXOCON_GP_Msk (0x30UL) |
| |
| #define | ERU_EXOCON_IPEN0_Pos (12UL) |
| |
| #define | ERU_EXOCON_IPEN0_Msk (0x1000UL) |
| |
| #define | ERU_EXOCON_IPEN1_Pos (13UL) |
| |
| #define | ERU_EXOCON_IPEN1_Msk (0x2000UL) |
| |
| #define | ERU_EXOCON_IPEN2_Pos (14UL) |
| |
| #define | ERU_EXOCON_IPEN2_Msk (0x4000UL) |
| |
| #define | ERU_EXOCON_IPEN3_Pos (15UL) |
| |
| #define | ERU_EXOCON_IPEN3_Msk (0x8000UL) |
| |
| #define | GPDMA0_RAWTFR_CH0_Pos (0UL) |
| |
| #define | GPDMA0_RAWTFR_CH0_Msk (0x1UL) |
| |
| #define | GPDMA0_RAWTFR_CH1_Pos (1UL) |
| |
| #define | GPDMA0_RAWTFR_CH1_Msk (0x2UL) |
| |
| #define | GPDMA0_RAWTFR_CH2_Pos (2UL) |
| |
| #define | GPDMA0_RAWTFR_CH2_Msk (0x4UL) |
| |
| #define | GPDMA0_RAWTFR_CH3_Pos (3UL) |
| |
| #define | GPDMA0_RAWTFR_CH3_Msk (0x8UL) |
| |
| #define | GPDMA0_RAWTFR_CH4_Pos (4UL) |
| |
| #define | GPDMA0_RAWTFR_CH4_Msk (0x10UL) |
| |
| #define | GPDMA0_RAWTFR_CH5_Pos (5UL) |
| |
| #define | GPDMA0_RAWTFR_CH5_Msk (0x20UL) |
| |
| #define | GPDMA0_RAWTFR_CH6_Pos (6UL) |
| |
| #define | GPDMA0_RAWTFR_CH6_Msk (0x40UL) |
| |
| #define | GPDMA0_RAWTFR_CH7_Pos (7UL) |
| |
| #define | GPDMA0_RAWTFR_CH7_Msk (0x80UL) |
| |
| #define | GPDMA0_RAWBLOCK_CH0_Pos (0UL) |
| |
| #define | GPDMA0_RAWBLOCK_CH0_Msk (0x1UL) |
| |
| #define | GPDMA0_RAWBLOCK_CH1_Pos (1UL) |
| |
| #define | GPDMA0_RAWBLOCK_CH1_Msk (0x2UL) |
| |
| #define | GPDMA0_RAWBLOCK_CH2_Pos (2UL) |
| |
| #define | GPDMA0_RAWBLOCK_CH2_Msk (0x4UL) |
| |
| #define | GPDMA0_RAWBLOCK_CH3_Pos (3UL) |
| |
| #define | GPDMA0_RAWBLOCK_CH3_Msk (0x8UL) |
| |
| #define | GPDMA0_RAWBLOCK_CH4_Pos (4UL) |
| |
| #define | GPDMA0_RAWBLOCK_CH4_Msk (0x10UL) |
| |
| #define | GPDMA0_RAWBLOCK_CH5_Pos (5UL) |
| |
| #define | GPDMA0_RAWBLOCK_CH5_Msk (0x20UL) |
| |
| #define | GPDMA0_RAWBLOCK_CH6_Pos (6UL) |
| |
| #define | GPDMA0_RAWBLOCK_CH6_Msk (0x40UL) |
| |
| #define | GPDMA0_RAWBLOCK_CH7_Pos (7UL) |
| |
| #define | GPDMA0_RAWBLOCK_CH7_Msk (0x80UL) |
| |
| #define | GPDMA0_RAWSRCTRAN_CH0_Pos (0UL) |
| |
| #define | GPDMA0_RAWSRCTRAN_CH0_Msk (0x1UL) |
| |
| #define | GPDMA0_RAWSRCTRAN_CH1_Pos (1UL) |
| |
| #define | GPDMA0_RAWSRCTRAN_CH1_Msk (0x2UL) |
| |
| #define | GPDMA0_RAWSRCTRAN_CH2_Pos (2UL) |
| |
| #define | GPDMA0_RAWSRCTRAN_CH2_Msk (0x4UL) |
| |
| #define | GPDMA0_RAWSRCTRAN_CH3_Pos (3UL) |
| |
| #define | GPDMA0_RAWSRCTRAN_CH3_Msk (0x8UL) |
| |
| #define | GPDMA0_RAWSRCTRAN_CH4_Pos (4UL) |
| |
| #define | GPDMA0_RAWSRCTRAN_CH4_Msk (0x10UL) |
| |
| #define | GPDMA0_RAWSRCTRAN_CH5_Pos (5UL) |
| |
| #define | GPDMA0_RAWSRCTRAN_CH5_Msk (0x20UL) |
| |
| #define | GPDMA0_RAWSRCTRAN_CH6_Pos (6UL) |
| |
| #define | GPDMA0_RAWSRCTRAN_CH6_Msk (0x40UL) |
| |
| #define | GPDMA0_RAWSRCTRAN_CH7_Pos (7UL) |
| |
| #define | GPDMA0_RAWSRCTRAN_CH7_Msk (0x80UL) |
| |
| #define | GPDMA0_RAWDSTTRAN_CH0_Pos (0UL) |
| |
| #define | GPDMA0_RAWDSTTRAN_CH0_Msk (0x1UL) |
| |
| #define | GPDMA0_RAWDSTTRAN_CH1_Pos (1UL) |
| |
| #define | GPDMA0_RAWDSTTRAN_CH1_Msk (0x2UL) |
| |
| #define | GPDMA0_RAWDSTTRAN_CH2_Pos (2UL) |
| |
| #define | GPDMA0_RAWDSTTRAN_CH2_Msk (0x4UL) |
| |
| #define | GPDMA0_RAWDSTTRAN_CH3_Pos (3UL) |
| |
| #define | GPDMA0_RAWDSTTRAN_CH3_Msk (0x8UL) |
| |
| #define | GPDMA0_RAWDSTTRAN_CH4_Pos (4UL) |
| |
| #define | GPDMA0_RAWDSTTRAN_CH4_Msk (0x10UL) |
| |
| #define | GPDMA0_RAWDSTTRAN_CH5_Pos (5UL) |
| |
| #define | GPDMA0_RAWDSTTRAN_CH5_Msk (0x20UL) |
| |
| #define | GPDMA0_RAWDSTTRAN_CH6_Pos (6UL) |
| |
| #define | GPDMA0_RAWDSTTRAN_CH6_Msk (0x40UL) |
| |
| #define | GPDMA0_RAWDSTTRAN_CH7_Pos (7UL) |
| |
| #define | GPDMA0_RAWDSTTRAN_CH7_Msk (0x80UL) |
| |
| #define | GPDMA0_RAWERR_CH0_Pos (0UL) |
| |
| #define | GPDMA0_RAWERR_CH0_Msk (0x1UL) |
| |
| #define | GPDMA0_RAWERR_CH1_Pos (1UL) |
| |
| #define | GPDMA0_RAWERR_CH1_Msk (0x2UL) |
| |
| #define | GPDMA0_RAWERR_CH2_Pos (2UL) |
| |
| #define | GPDMA0_RAWERR_CH2_Msk (0x4UL) |
| |
| #define | GPDMA0_RAWERR_CH3_Pos (3UL) |
| |
| #define | GPDMA0_RAWERR_CH3_Msk (0x8UL) |
| |
| #define | GPDMA0_RAWERR_CH4_Pos (4UL) |
| |
| #define | GPDMA0_RAWERR_CH4_Msk (0x10UL) |
| |
| #define | GPDMA0_RAWERR_CH5_Pos (5UL) |
| |
| #define | GPDMA0_RAWERR_CH5_Msk (0x20UL) |
| |
| #define | GPDMA0_RAWERR_CH6_Pos (6UL) |
| |
| #define | GPDMA0_RAWERR_CH6_Msk (0x40UL) |
| |
| #define | GPDMA0_RAWERR_CH7_Pos (7UL) |
| |
| #define | GPDMA0_RAWERR_CH7_Msk (0x80UL) |
| |
| #define | GPDMA0_STATUSTFR_CH0_Pos (0UL) |
| |
| #define | GPDMA0_STATUSTFR_CH0_Msk (0x1UL) |
| |
| #define | GPDMA0_STATUSTFR_CH1_Pos (1UL) |
| |
| #define | GPDMA0_STATUSTFR_CH1_Msk (0x2UL) |
| |
| #define | GPDMA0_STATUSTFR_CH2_Pos (2UL) |
| |
| #define | GPDMA0_STATUSTFR_CH2_Msk (0x4UL) |
| |
| #define | GPDMA0_STATUSTFR_CH3_Pos (3UL) |
| |
| #define | GPDMA0_STATUSTFR_CH3_Msk (0x8UL) |
| |
| #define | GPDMA0_STATUSTFR_CH4_Pos (4UL) |
| |
| #define | GPDMA0_STATUSTFR_CH4_Msk (0x10UL) |
| |
| #define | GPDMA0_STATUSTFR_CH5_Pos (5UL) |
| |
| #define | GPDMA0_STATUSTFR_CH5_Msk (0x20UL) |
| |
| #define | GPDMA0_STATUSTFR_CH6_Pos (6UL) |
| |
| #define | GPDMA0_STATUSTFR_CH6_Msk (0x40UL) |
| |
| #define | GPDMA0_STATUSTFR_CH7_Pos (7UL) |
| |
| #define | GPDMA0_STATUSTFR_CH7_Msk (0x80UL) |
| |
| #define | GPDMA0_STATUSBLOCK_CH0_Pos (0UL) |
| |
| #define | GPDMA0_STATUSBLOCK_CH0_Msk (0x1UL) |
| |
| #define | GPDMA0_STATUSBLOCK_CH1_Pos (1UL) |
| |
| #define | GPDMA0_STATUSBLOCK_CH1_Msk (0x2UL) |
| |
| #define | GPDMA0_STATUSBLOCK_CH2_Pos (2UL) |
| |
| #define | GPDMA0_STATUSBLOCK_CH2_Msk (0x4UL) |
| |
| #define | GPDMA0_STATUSBLOCK_CH3_Pos (3UL) |
| |
| #define | GPDMA0_STATUSBLOCK_CH3_Msk (0x8UL) |
| |
| #define | GPDMA0_STATUSBLOCK_CH4_Pos (4UL) |
| |
| #define | GPDMA0_STATUSBLOCK_CH4_Msk (0x10UL) |
| |
| #define | GPDMA0_STATUSBLOCK_CH5_Pos (5UL) |
| |
| #define | GPDMA0_STATUSBLOCK_CH5_Msk (0x20UL) |
| |
| #define | GPDMA0_STATUSBLOCK_CH6_Pos (6UL) |
| |
| #define | GPDMA0_STATUSBLOCK_CH6_Msk (0x40UL) |
| |
| #define | GPDMA0_STATUSBLOCK_CH7_Pos (7UL) |
| |
| #define | GPDMA0_STATUSBLOCK_CH7_Msk (0x80UL) |
| |
| #define | GPDMA0_STATUSSRCTRAN_CH0_Pos (0UL) |
| |
| #define | GPDMA0_STATUSSRCTRAN_CH0_Msk (0x1UL) |
| |
| #define | GPDMA0_STATUSSRCTRAN_CH1_Pos (1UL) |
| |
| #define | GPDMA0_STATUSSRCTRAN_CH1_Msk (0x2UL) |
| |
| #define | GPDMA0_STATUSSRCTRAN_CH2_Pos (2UL) |
| |
| #define | GPDMA0_STATUSSRCTRAN_CH2_Msk (0x4UL) |
| |
| #define | GPDMA0_STATUSSRCTRAN_CH3_Pos (3UL) |
| |
| #define | GPDMA0_STATUSSRCTRAN_CH3_Msk (0x8UL) |
| |
| #define | GPDMA0_STATUSSRCTRAN_CH4_Pos (4UL) |
| |
| #define | GPDMA0_STATUSSRCTRAN_CH4_Msk (0x10UL) |
| |
| #define | GPDMA0_STATUSSRCTRAN_CH5_Pos (5UL) |
| |
| #define | GPDMA0_STATUSSRCTRAN_CH5_Msk (0x20UL) |
| |
| #define | GPDMA0_STATUSSRCTRAN_CH6_Pos (6UL) |
| |
| #define | GPDMA0_STATUSSRCTRAN_CH6_Msk (0x40UL) |
| |
| #define | GPDMA0_STATUSSRCTRAN_CH7_Pos (7UL) |
| |
| #define | GPDMA0_STATUSSRCTRAN_CH7_Msk (0x80UL) |
| |
| #define | GPDMA0_STATUSDSTTRAN_CH0_Pos (0UL) |
| |
| #define | GPDMA0_STATUSDSTTRAN_CH0_Msk (0x1UL) |
| |
| #define | GPDMA0_STATUSDSTTRAN_CH1_Pos (1UL) |
| |
| #define | GPDMA0_STATUSDSTTRAN_CH1_Msk (0x2UL) |
| |
| #define | GPDMA0_STATUSDSTTRAN_CH2_Pos (2UL) |
| |
| #define | GPDMA0_STATUSDSTTRAN_CH2_Msk (0x4UL) |
| |
| #define | GPDMA0_STATUSDSTTRAN_CH3_Pos (3UL) |
| |
| #define | GPDMA0_STATUSDSTTRAN_CH3_Msk (0x8UL) |
| |
| #define | GPDMA0_STATUSDSTTRAN_CH4_Pos (4UL) |
| |
| #define | GPDMA0_STATUSDSTTRAN_CH4_Msk (0x10UL) |
| |
| #define | GPDMA0_STATUSDSTTRAN_CH5_Pos (5UL) |
| |
| #define | GPDMA0_STATUSDSTTRAN_CH5_Msk (0x20UL) |
| |
| #define | GPDMA0_STATUSDSTTRAN_CH6_Pos (6UL) |
| |
| #define | GPDMA0_STATUSDSTTRAN_CH6_Msk (0x40UL) |
| |
| #define | GPDMA0_STATUSDSTTRAN_CH7_Pos (7UL) |
| |
| #define | GPDMA0_STATUSDSTTRAN_CH7_Msk (0x80UL) |
| |
| #define | GPDMA0_STATUSERR_CH0_Pos (0UL) |
| |
| #define | GPDMA0_STATUSERR_CH0_Msk (0x1UL) |
| |
| #define | GPDMA0_STATUSERR_CH1_Pos (1UL) |
| |
| #define | GPDMA0_STATUSERR_CH1_Msk (0x2UL) |
| |
| #define | GPDMA0_STATUSERR_CH2_Pos (2UL) |
| |
| #define | GPDMA0_STATUSERR_CH2_Msk (0x4UL) |
| |
| #define | GPDMA0_STATUSERR_CH3_Pos (3UL) |
| |
| #define | GPDMA0_STATUSERR_CH3_Msk (0x8UL) |
| |
| #define | GPDMA0_STATUSERR_CH4_Pos (4UL) |
| |
| #define | GPDMA0_STATUSERR_CH4_Msk (0x10UL) |
| |
| #define | GPDMA0_STATUSERR_CH5_Pos (5UL) |
| |
| #define | GPDMA0_STATUSERR_CH5_Msk (0x20UL) |
| |
| #define | GPDMA0_STATUSERR_CH6_Pos (6UL) |
| |
| #define | GPDMA0_STATUSERR_CH6_Msk (0x40UL) |
| |
| #define | GPDMA0_STATUSERR_CH7_Pos (7UL) |
| |
| #define | GPDMA0_STATUSERR_CH7_Msk (0x80UL) |
| |
| #define | GPDMA0_MASKTFR_CH0_Pos (0UL) |
| |
| #define | GPDMA0_MASKTFR_CH0_Msk (0x1UL) |
| |
| #define | GPDMA0_MASKTFR_CH1_Pos (1UL) |
| |
| #define | GPDMA0_MASKTFR_CH1_Msk (0x2UL) |
| |
| #define | GPDMA0_MASKTFR_CH2_Pos (2UL) |
| |
| #define | GPDMA0_MASKTFR_CH2_Msk (0x4UL) |
| |
| #define | GPDMA0_MASKTFR_CH3_Pos (3UL) |
| |
| #define | GPDMA0_MASKTFR_CH3_Msk (0x8UL) |
| |
| #define | GPDMA0_MASKTFR_CH4_Pos (4UL) |
| |
| #define | GPDMA0_MASKTFR_CH4_Msk (0x10UL) |
| |
| #define | GPDMA0_MASKTFR_CH5_Pos (5UL) |
| |
| #define | GPDMA0_MASKTFR_CH5_Msk (0x20UL) |
| |
| #define | GPDMA0_MASKTFR_CH6_Pos (6UL) |
| |
| #define | GPDMA0_MASKTFR_CH6_Msk (0x40UL) |
| |
| #define | GPDMA0_MASKTFR_CH7_Pos (7UL) |
| |
| #define | GPDMA0_MASKTFR_CH7_Msk (0x80UL) |
| |
| #define | GPDMA0_MASKTFR_WE_CH0_Pos (8UL) |
| |
| #define | GPDMA0_MASKTFR_WE_CH0_Msk (0x100UL) |
| |
| #define | GPDMA0_MASKTFR_WE_CH1_Pos (9UL) |
| |
| #define | GPDMA0_MASKTFR_WE_CH1_Msk (0x200UL) |
| |
| #define | GPDMA0_MASKTFR_WE_CH2_Pos (10UL) |
| |
| #define | GPDMA0_MASKTFR_WE_CH2_Msk (0x400UL) |
| |
| #define | GPDMA0_MASKTFR_WE_CH3_Pos (11UL) |
| |
| #define | GPDMA0_MASKTFR_WE_CH3_Msk (0x800UL) |
| |
| #define | GPDMA0_MASKTFR_WE_CH4_Pos (12UL) |
| |
| #define | GPDMA0_MASKTFR_WE_CH4_Msk (0x1000UL) |
| |
| #define | GPDMA0_MASKTFR_WE_CH5_Pos (13UL) |
| |
| #define | GPDMA0_MASKTFR_WE_CH5_Msk (0x2000UL) |
| |
| #define | GPDMA0_MASKTFR_WE_CH6_Pos (14UL) |
| |
| #define | GPDMA0_MASKTFR_WE_CH6_Msk (0x4000UL) |
| |
| #define | GPDMA0_MASKTFR_WE_CH7_Pos (15UL) |
| |
| #define | GPDMA0_MASKTFR_WE_CH7_Msk (0x8000UL) |
| |
| #define | GPDMA0_MASKBLOCK_CH0_Pos (0UL) |
| |
| #define | GPDMA0_MASKBLOCK_CH0_Msk (0x1UL) |
| |
| #define | GPDMA0_MASKBLOCK_CH1_Pos (1UL) |
| |
| #define | GPDMA0_MASKBLOCK_CH1_Msk (0x2UL) |
| |
| #define | GPDMA0_MASKBLOCK_CH2_Pos (2UL) |
| |
| #define | GPDMA0_MASKBLOCK_CH2_Msk (0x4UL) |
| |
| #define | GPDMA0_MASKBLOCK_CH3_Pos (3UL) |
| |
| #define | GPDMA0_MASKBLOCK_CH3_Msk (0x8UL) |
| |
| #define | GPDMA0_MASKBLOCK_CH4_Pos (4UL) |
| |
| #define | GPDMA0_MASKBLOCK_CH4_Msk (0x10UL) |
| |
| #define | GPDMA0_MASKBLOCK_CH5_Pos (5UL) |
| |
| #define | GPDMA0_MASKBLOCK_CH5_Msk (0x20UL) |
| |
| #define | GPDMA0_MASKBLOCK_CH6_Pos (6UL) |
| |
| #define | GPDMA0_MASKBLOCK_CH6_Msk (0x40UL) |
| |
| #define | GPDMA0_MASKBLOCK_CH7_Pos (7UL) |
| |
| #define | GPDMA0_MASKBLOCK_CH7_Msk (0x80UL) |
| |
| #define | GPDMA0_MASKBLOCK_WE_CH0_Pos (8UL) |
| |
| #define | GPDMA0_MASKBLOCK_WE_CH0_Msk (0x100UL) |
| |
| #define | GPDMA0_MASKBLOCK_WE_CH1_Pos (9UL) |
| |
| #define | GPDMA0_MASKBLOCK_WE_CH1_Msk (0x200UL) |
| |
| #define | GPDMA0_MASKBLOCK_WE_CH2_Pos (10UL) |
| |
| #define | GPDMA0_MASKBLOCK_WE_CH2_Msk (0x400UL) |
| |
| #define | GPDMA0_MASKBLOCK_WE_CH3_Pos (11UL) |
| |
| #define | GPDMA0_MASKBLOCK_WE_CH3_Msk (0x800UL) |
| |
| #define | GPDMA0_MASKBLOCK_WE_CH4_Pos (12UL) |
| |
| #define | GPDMA0_MASKBLOCK_WE_CH4_Msk (0x1000UL) |
| |
| #define | GPDMA0_MASKBLOCK_WE_CH5_Pos (13UL) |
| |
| #define | GPDMA0_MASKBLOCK_WE_CH5_Msk (0x2000UL) |
| |
| #define | GPDMA0_MASKBLOCK_WE_CH6_Pos (14UL) |
| |
| #define | GPDMA0_MASKBLOCK_WE_CH6_Msk (0x4000UL) |
| |
| #define | GPDMA0_MASKBLOCK_WE_CH7_Pos (15UL) |
| |
| #define | GPDMA0_MASKBLOCK_WE_CH7_Msk (0x8000UL) |
| |
| #define | GPDMA0_MASKSRCTRAN_CH0_Pos (0UL) |
| |
| #define | GPDMA0_MASKSRCTRAN_CH0_Msk (0x1UL) |
| |
| #define | GPDMA0_MASKSRCTRAN_CH1_Pos (1UL) |
| |
| #define | GPDMA0_MASKSRCTRAN_CH1_Msk (0x2UL) |
| |
| #define | GPDMA0_MASKSRCTRAN_CH2_Pos (2UL) |
| |
| #define | GPDMA0_MASKSRCTRAN_CH2_Msk (0x4UL) |
| |
| #define | GPDMA0_MASKSRCTRAN_CH3_Pos (3UL) |
| |
| #define | GPDMA0_MASKSRCTRAN_CH3_Msk (0x8UL) |
| |
| #define | GPDMA0_MASKSRCTRAN_CH4_Pos (4UL) |
| |
| #define | GPDMA0_MASKSRCTRAN_CH4_Msk (0x10UL) |
| |
| #define | GPDMA0_MASKSRCTRAN_CH5_Pos (5UL) |
| |
| #define | GPDMA0_MASKSRCTRAN_CH5_Msk (0x20UL) |
| |
| #define | GPDMA0_MASKSRCTRAN_CH6_Pos (6UL) |
| |
| #define | GPDMA0_MASKSRCTRAN_CH6_Msk (0x40UL) |
| |
| #define | GPDMA0_MASKSRCTRAN_CH7_Pos (7UL) |
| |
| #define | GPDMA0_MASKSRCTRAN_CH7_Msk (0x80UL) |
| |
| #define | GPDMA0_MASKSRCTRAN_WE_CH0_Pos (8UL) |
| |
| #define | GPDMA0_MASKSRCTRAN_WE_CH0_Msk (0x100UL) |
| |
| #define | GPDMA0_MASKSRCTRAN_WE_CH1_Pos (9UL) |
| |
| #define | GPDMA0_MASKSRCTRAN_WE_CH1_Msk (0x200UL) |
| |
| #define | GPDMA0_MASKSRCTRAN_WE_CH2_Pos (10UL) |
| |
| #define | GPDMA0_MASKSRCTRAN_WE_CH2_Msk (0x400UL) |
| |
| #define | GPDMA0_MASKSRCTRAN_WE_CH3_Pos (11UL) |
| |
| #define | GPDMA0_MASKSRCTRAN_WE_CH3_Msk (0x800UL) |
| |
| #define | GPDMA0_MASKSRCTRAN_WE_CH4_Pos (12UL) |
| |
| #define | GPDMA0_MASKSRCTRAN_WE_CH4_Msk (0x1000UL) |
| |
| #define | GPDMA0_MASKSRCTRAN_WE_CH5_Pos (13UL) |
| |
| #define | GPDMA0_MASKSRCTRAN_WE_CH5_Msk (0x2000UL) |
| |
| #define | GPDMA0_MASKSRCTRAN_WE_CH6_Pos (14UL) |
| |
| #define | GPDMA0_MASKSRCTRAN_WE_CH6_Msk (0x4000UL) |
| |
| #define | GPDMA0_MASKSRCTRAN_WE_CH7_Pos (15UL) |
| |
| #define | GPDMA0_MASKSRCTRAN_WE_CH7_Msk (0x8000UL) |
| |
| #define | GPDMA0_MASKDSTTRAN_CH0_Pos (0UL) |
| |
| #define | GPDMA0_MASKDSTTRAN_CH0_Msk (0x1UL) |
| |
| #define | GPDMA0_MASKDSTTRAN_CH1_Pos (1UL) |
| |
| #define | GPDMA0_MASKDSTTRAN_CH1_Msk (0x2UL) |
| |
| #define | GPDMA0_MASKDSTTRAN_CH2_Pos (2UL) |
| |
| #define | GPDMA0_MASKDSTTRAN_CH2_Msk (0x4UL) |
| |
| #define | GPDMA0_MASKDSTTRAN_CH3_Pos (3UL) |
| |
| #define | GPDMA0_MASKDSTTRAN_CH3_Msk (0x8UL) |
| |
| #define | GPDMA0_MASKDSTTRAN_CH4_Pos (4UL) |
| |
| #define | GPDMA0_MASKDSTTRAN_CH4_Msk (0x10UL) |
| |
| #define | GPDMA0_MASKDSTTRAN_CH5_Pos (5UL) |
| |
| #define | GPDMA0_MASKDSTTRAN_CH5_Msk (0x20UL) |
| |
| #define | GPDMA0_MASKDSTTRAN_CH6_Pos (6UL) |
| |
| #define | GPDMA0_MASKDSTTRAN_CH6_Msk (0x40UL) |
| |
| #define | GPDMA0_MASKDSTTRAN_CH7_Pos (7UL) |
| |
| #define | GPDMA0_MASKDSTTRAN_CH7_Msk (0x80UL) |
| |
| #define | GPDMA0_MASKDSTTRAN_WE_CH0_Pos (8UL) |
| |
| #define | GPDMA0_MASKDSTTRAN_WE_CH0_Msk (0x100UL) |
| |
| #define | GPDMA0_MASKDSTTRAN_WE_CH1_Pos (9UL) |
| |
| #define | GPDMA0_MASKDSTTRAN_WE_CH1_Msk (0x200UL) |
| |
| #define | GPDMA0_MASKDSTTRAN_WE_CH2_Pos (10UL) |
| |
| #define | GPDMA0_MASKDSTTRAN_WE_CH2_Msk (0x400UL) |
| |
| #define | GPDMA0_MASKDSTTRAN_WE_CH3_Pos (11UL) |
| |
| #define | GPDMA0_MASKDSTTRAN_WE_CH3_Msk (0x800UL) |
| |
| #define | GPDMA0_MASKDSTTRAN_WE_CH4_Pos (12UL) |
| |
| #define | GPDMA0_MASKDSTTRAN_WE_CH4_Msk (0x1000UL) |
| |
| #define | GPDMA0_MASKDSTTRAN_WE_CH5_Pos (13UL) |
| |
| #define | GPDMA0_MASKDSTTRAN_WE_CH5_Msk (0x2000UL) |
| |
| #define | GPDMA0_MASKDSTTRAN_WE_CH6_Pos (14UL) |
| |
| #define | GPDMA0_MASKDSTTRAN_WE_CH6_Msk (0x4000UL) |
| |
| #define | GPDMA0_MASKDSTTRAN_WE_CH7_Pos (15UL) |
| |
| #define | GPDMA0_MASKDSTTRAN_WE_CH7_Msk (0x8000UL) |
| |
| #define | GPDMA0_MASKERR_CH0_Pos (0UL) |
| |
| #define | GPDMA0_MASKERR_CH0_Msk (0x1UL) |
| |
| #define | GPDMA0_MASKERR_CH1_Pos (1UL) |
| |
| #define | GPDMA0_MASKERR_CH1_Msk (0x2UL) |
| |
| #define | GPDMA0_MASKERR_CH2_Pos (2UL) |
| |
| #define | GPDMA0_MASKERR_CH2_Msk (0x4UL) |
| |
| #define | GPDMA0_MASKERR_CH3_Pos (3UL) |
| |
| #define | GPDMA0_MASKERR_CH3_Msk (0x8UL) |
| |
| #define | GPDMA0_MASKERR_CH4_Pos (4UL) |
| |
| #define | GPDMA0_MASKERR_CH4_Msk (0x10UL) |
| |
| #define | GPDMA0_MASKERR_CH5_Pos (5UL) |
| |
| #define | GPDMA0_MASKERR_CH5_Msk (0x20UL) |
| |
| #define | GPDMA0_MASKERR_CH6_Pos (6UL) |
| |
| #define | GPDMA0_MASKERR_CH6_Msk (0x40UL) |
| |
| #define | GPDMA0_MASKERR_CH7_Pos (7UL) |
| |
| #define | GPDMA0_MASKERR_CH7_Msk (0x80UL) |
| |
| #define | GPDMA0_MASKERR_WE_CH0_Pos (8UL) |
| |
| #define | GPDMA0_MASKERR_WE_CH0_Msk (0x100UL) |
| |
| #define | GPDMA0_MASKERR_WE_CH1_Pos (9UL) |
| |
| #define | GPDMA0_MASKERR_WE_CH1_Msk (0x200UL) |
| |
| #define | GPDMA0_MASKERR_WE_CH2_Pos (10UL) |
| |
| #define | GPDMA0_MASKERR_WE_CH2_Msk (0x400UL) |
| |
| #define | GPDMA0_MASKERR_WE_CH3_Pos (11UL) |
| |
| #define | GPDMA0_MASKERR_WE_CH3_Msk (0x800UL) |
| |
| #define | GPDMA0_MASKERR_WE_CH4_Pos (12UL) |
| |
| #define | GPDMA0_MASKERR_WE_CH4_Msk (0x1000UL) |
| |
| #define | GPDMA0_MASKERR_WE_CH5_Pos (13UL) |
| |
| #define | GPDMA0_MASKERR_WE_CH5_Msk (0x2000UL) |
| |
| #define | GPDMA0_MASKERR_WE_CH6_Pos (14UL) |
| |
| #define | GPDMA0_MASKERR_WE_CH6_Msk (0x4000UL) |
| |
| #define | GPDMA0_MASKERR_WE_CH7_Pos (15UL) |
| |
| #define | GPDMA0_MASKERR_WE_CH7_Msk (0x8000UL) |
| |
| #define | GPDMA0_CLEARTFR_CH0_Pos (0UL) |
| |
| #define | GPDMA0_CLEARTFR_CH0_Msk (0x1UL) |
| |
| #define | GPDMA0_CLEARTFR_CH1_Pos (1UL) |
| |
| #define | GPDMA0_CLEARTFR_CH1_Msk (0x2UL) |
| |
| #define | GPDMA0_CLEARTFR_CH2_Pos (2UL) |
| |
| #define | GPDMA0_CLEARTFR_CH2_Msk (0x4UL) |
| |
| #define | GPDMA0_CLEARTFR_CH3_Pos (3UL) |
| |
| #define | GPDMA0_CLEARTFR_CH3_Msk (0x8UL) |
| |
| #define | GPDMA0_CLEARTFR_CH4_Pos (4UL) |
| |
| #define | GPDMA0_CLEARTFR_CH4_Msk (0x10UL) |
| |
| #define | GPDMA0_CLEARTFR_CH5_Pos (5UL) |
| |
| #define | GPDMA0_CLEARTFR_CH5_Msk (0x20UL) |
| |
| #define | GPDMA0_CLEARTFR_CH6_Pos (6UL) |
| |
| #define | GPDMA0_CLEARTFR_CH6_Msk (0x40UL) |
| |
| #define | GPDMA0_CLEARTFR_CH7_Pos (7UL) |
| |
| #define | GPDMA0_CLEARTFR_CH7_Msk (0x80UL) |
| |
| #define | GPDMA0_CLEARBLOCK_CH0_Pos (0UL) |
| |
| #define | GPDMA0_CLEARBLOCK_CH0_Msk (0x1UL) |
| |
| #define | GPDMA0_CLEARBLOCK_CH1_Pos (1UL) |
| |
| #define | GPDMA0_CLEARBLOCK_CH1_Msk (0x2UL) |
| |
| #define | GPDMA0_CLEARBLOCK_CH2_Pos (2UL) |
| |
| #define | GPDMA0_CLEARBLOCK_CH2_Msk (0x4UL) |
| |
| #define | GPDMA0_CLEARBLOCK_CH3_Pos (3UL) |
| |
| #define | GPDMA0_CLEARBLOCK_CH3_Msk (0x8UL) |
| |
| #define | GPDMA0_CLEARBLOCK_CH4_Pos (4UL) |
| |
| #define | GPDMA0_CLEARBLOCK_CH4_Msk (0x10UL) |
| |
| #define | GPDMA0_CLEARBLOCK_CH5_Pos (5UL) |
| |
| #define | GPDMA0_CLEARBLOCK_CH5_Msk (0x20UL) |
| |
| #define | GPDMA0_CLEARBLOCK_CH6_Pos (6UL) |
| |
| #define | GPDMA0_CLEARBLOCK_CH6_Msk (0x40UL) |
| |
| #define | GPDMA0_CLEARBLOCK_CH7_Pos (7UL) |
| |
| #define | GPDMA0_CLEARBLOCK_CH7_Msk (0x80UL) |
| |
| #define | GPDMA0_CLEARSRCTRAN_CH0_Pos (0UL) |
| |
| #define | GPDMA0_CLEARSRCTRAN_CH0_Msk (0x1UL) |
| |
| #define | GPDMA0_CLEARSRCTRAN_CH1_Pos (1UL) |
| |
| #define | GPDMA0_CLEARSRCTRAN_CH1_Msk (0x2UL) |
| |
| #define | GPDMA0_CLEARSRCTRAN_CH2_Pos (2UL) |
| |
| #define | GPDMA0_CLEARSRCTRAN_CH2_Msk (0x4UL) |
| |
| #define | GPDMA0_CLEARSRCTRAN_CH3_Pos (3UL) |
| |
| #define | GPDMA0_CLEARSRCTRAN_CH3_Msk (0x8UL) |
| |
| #define | GPDMA0_CLEARSRCTRAN_CH4_Pos (4UL) |
| |
| #define | GPDMA0_CLEARSRCTRAN_CH4_Msk (0x10UL) |
| |
| #define | GPDMA0_CLEARSRCTRAN_CH5_Pos (5UL) |
| |
| #define | GPDMA0_CLEARSRCTRAN_CH5_Msk (0x20UL) |
| |
| #define | GPDMA0_CLEARSRCTRAN_CH6_Pos (6UL) |
| |
| #define | GPDMA0_CLEARSRCTRAN_CH6_Msk (0x40UL) |
| |
| #define | GPDMA0_CLEARSRCTRAN_CH7_Pos (7UL) |
| |
| #define | GPDMA0_CLEARSRCTRAN_CH7_Msk (0x80UL) |
| |
| #define | GPDMA0_CLEARDSTTRAN_CH0_Pos (0UL) |
| |
| #define | GPDMA0_CLEARDSTTRAN_CH0_Msk (0x1UL) |
| |
| #define | GPDMA0_CLEARDSTTRAN_CH1_Pos (1UL) |
| |
| #define | GPDMA0_CLEARDSTTRAN_CH1_Msk (0x2UL) |
| |
| #define | GPDMA0_CLEARDSTTRAN_CH2_Pos (2UL) |
| |
| #define | GPDMA0_CLEARDSTTRAN_CH2_Msk (0x4UL) |
| |
| #define | GPDMA0_CLEARDSTTRAN_CH3_Pos (3UL) |
| |
| #define | GPDMA0_CLEARDSTTRAN_CH3_Msk (0x8UL) |
| |
| #define | GPDMA0_CLEARDSTTRAN_CH4_Pos (4UL) |
| |
| #define | GPDMA0_CLEARDSTTRAN_CH4_Msk (0x10UL) |
| |
| #define | GPDMA0_CLEARDSTTRAN_CH5_Pos (5UL) |
| |
| #define | GPDMA0_CLEARDSTTRAN_CH5_Msk (0x20UL) |
| |
| #define | GPDMA0_CLEARDSTTRAN_CH6_Pos (6UL) |
| |
| #define | GPDMA0_CLEARDSTTRAN_CH6_Msk (0x40UL) |
| |
| #define | GPDMA0_CLEARDSTTRAN_CH7_Pos (7UL) |
| |
| #define | GPDMA0_CLEARDSTTRAN_CH7_Msk (0x80UL) |
| |
| #define | GPDMA0_CLEARERR_CH0_Pos (0UL) |
| |
| #define | GPDMA0_CLEARERR_CH0_Msk (0x1UL) |
| |
| #define | GPDMA0_CLEARERR_CH1_Pos (1UL) |
| |
| #define | GPDMA0_CLEARERR_CH1_Msk (0x2UL) |
| |
| #define | GPDMA0_CLEARERR_CH2_Pos (2UL) |
| |
| #define | GPDMA0_CLEARERR_CH2_Msk (0x4UL) |
| |
| #define | GPDMA0_CLEARERR_CH3_Pos (3UL) |
| |
| #define | GPDMA0_CLEARERR_CH3_Msk (0x8UL) |
| |
| #define | GPDMA0_CLEARERR_CH4_Pos (4UL) |
| |
| #define | GPDMA0_CLEARERR_CH4_Msk (0x10UL) |
| |
| #define | GPDMA0_CLEARERR_CH5_Pos (5UL) |
| |
| #define | GPDMA0_CLEARERR_CH5_Msk (0x20UL) |
| |
| #define | GPDMA0_CLEARERR_CH6_Pos (6UL) |
| |
| #define | GPDMA0_CLEARERR_CH6_Msk (0x40UL) |
| |
| #define | GPDMA0_CLEARERR_CH7_Pos (7UL) |
| |
| #define | GPDMA0_CLEARERR_CH7_Msk (0x80UL) |
| |
| #define | GPDMA0_STATUSINT_TFR_Pos (0UL) |
| |
| #define | GPDMA0_STATUSINT_TFR_Msk (0x1UL) |
| |
| #define | GPDMA0_STATUSINT_BLOCK_Pos (1UL) |
| |
| #define | GPDMA0_STATUSINT_BLOCK_Msk (0x2UL) |
| |
| #define | GPDMA0_STATUSINT_SRCT_Pos (2UL) |
| |
| #define | GPDMA0_STATUSINT_SRCT_Msk (0x4UL) |
| |
| #define | GPDMA0_STATUSINT_DSTT_Pos (3UL) |
| |
| #define | GPDMA0_STATUSINT_DSTT_Msk (0x8UL) |
| |
| #define | GPDMA0_STATUSINT_ERR_Pos (4UL) |
| |
| #define | GPDMA0_STATUSINT_ERR_Msk (0x10UL) |
| |
| #define | GPDMA0_REQSRCREG_CH0_Pos (0UL) |
| |
| #define | GPDMA0_REQSRCREG_CH0_Msk (0x1UL) |
| |
| #define | GPDMA0_REQSRCREG_CH1_Pos (1UL) |
| |
| #define | GPDMA0_REQSRCREG_CH1_Msk (0x2UL) |
| |
| #define | GPDMA0_REQSRCREG_CH2_Pos (2UL) |
| |
| #define | GPDMA0_REQSRCREG_CH2_Msk (0x4UL) |
| |
| #define | GPDMA0_REQSRCREG_CH3_Pos (3UL) |
| |
| #define | GPDMA0_REQSRCREG_CH3_Msk (0x8UL) |
| |
| #define | GPDMA0_REQSRCREG_CH4_Pos (4UL) |
| |
| #define | GPDMA0_REQSRCREG_CH4_Msk (0x10UL) |
| |
| #define | GPDMA0_REQSRCREG_CH5_Pos (5UL) |
| |
| #define | GPDMA0_REQSRCREG_CH5_Msk (0x20UL) |
| |
| #define | GPDMA0_REQSRCREG_CH6_Pos (6UL) |
| |
| #define | GPDMA0_REQSRCREG_CH6_Msk (0x40UL) |
| |
| #define | GPDMA0_REQSRCREG_CH7_Pos (7UL) |
| |
| #define | GPDMA0_REQSRCREG_CH7_Msk (0x80UL) |
| |
| #define | GPDMA0_REQSRCREG_WE_CH0_Pos (8UL) |
| |
| #define | GPDMA0_REQSRCREG_WE_CH0_Msk (0x100UL) |
| |
| #define | GPDMA0_REQSRCREG_WE_CH1_Pos (9UL) |
| |
| #define | GPDMA0_REQSRCREG_WE_CH1_Msk (0x200UL) |
| |
| #define | GPDMA0_REQSRCREG_WE_CH2_Pos (10UL) |
| |
| #define | GPDMA0_REQSRCREG_WE_CH2_Msk (0x400UL) |
| |
| #define | GPDMA0_REQSRCREG_WE_CH3_Pos (11UL) |
| |
| #define | GPDMA0_REQSRCREG_WE_CH3_Msk (0x800UL) |
| |
| #define | GPDMA0_REQSRCREG_WE_CH4_Pos (12UL) |
| |
| #define | GPDMA0_REQSRCREG_WE_CH4_Msk (0x1000UL) |
| |
| #define | GPDMA0_REQSRCREG_WE_CH5_Pos (13UL) |
| |
| #define | GPDMA0_REQSRCREG_WE_CH5_Msk (0x2000UL) |
| |
| #define | GPDMA0_REQSRCREG_WE_CH6_Pos (14UL) |
| |
| #define | GPDMA0_REQSRCREG_WE_CH6_Msk (0x4000UL) |
| |
| #define | GPDMA0_REQSRCREG_WE_CH7_Pos (15UL) |
| |
| #define | GPDMA0_REQSRCREG_WE_CH7_Msk (0x8000UL) |
| |
| #define | GPDMA0_REQDSTREG_CH0_Pos (0UL) |
| |
| #define | GPDMA0_REQDSTREG_CH0_Msk (0x1UL) |
| |
| #define | GPDMA0_REQDSTREG_CH1_Pos (1UL) |
| |
| #define | GPDMA0_REQDSTREG_CH1_Msk (0x2UL) |
| |
| #define | GPDMA0_REQDSTREG_CH2_Pos (2UL) |
| |
| #define | GPDMA0_REQDSTREG_CH2_Msk (0x4UL) |
| |
| #define | GPDMA0_REQDSTREG_CH3_Pos (3UL) |
| |
| #define | GPDMA0_REQDSTREG_CH3_Msk (0x8UL) |
| |
| #define | GPDMA0_REQDSTREG_CH4_Pos (4UL) |
| |
| #define | GPDMA0_REQDSTREG_CH4_Msk (0x10UL) |
| |
| #define | GPDMA0_REQDSTREG_CH5_Pos (5UL) |
| |
| #define | GPDMA0_REQDSTREG_CH5_Msk (0x20UL) |
| |
| #define | GPDMA0_REQDSTREG_CH6_Pos (6UL) |
| |
| #define | GPDMA0_REQDSTREG_CH6_Msk (0x40UL) |
| |
| #define | GPDMA0_REQDSTREG_CH7_Pos (7UL) |
| |
| #define | GPDMA0_REQDSTREG_CH7_Msk (0x80UL) |
| |
| #define | GPDMA0_REQDSTREG_WE_CH0_Pos (8UL) |
| |
| #define | GPDMA0_REQDSTREG_WE_CH0_Msk (0x100UL) |
| |
| #define | GPDMA0_REQDSTREG_WE_CH1_Pos (9UL) |
| |
| #define | GPDMA0_REQDSTREG_WE_CH1_Msk (0x200UL) |
| |
| #define | GPDMA0_REQDSTREG_WE_CH2_Pos (10UL) |
| |
| #define | GPDMA0_REQDSTREG_WE_CH2_Msk (0x400UL) |
| |
| #define | GPDMA0_REQDSTREG_WE_CH3_Pos (11UL) |
| |
| #define | GPDMA0_REQDSTREG_WE_CH3_Msk (0x800UL) |
| |
| #define | GPDMA0_REQDSTREG_WE_CH4_Pos (12UL) |
| |
| #define | GPDMA0_REQDSTREG_WE_CH4_Msk (0x1000UL) |
| |
| #define | GPDMA0_REQDSTREG_WE_CH5_Pos (13UL) |
| |
| #define | GPDMA0_REQDSTREG_WE_CH5_Msk (0x2000UL) |
| |
| #define | GPDMA0_REQDSTREG_WE_CH6_Pos (14UL) |
| |
| #define | GPDMA0_REQDSTREG_WE_CH6_Msk (0x4000UL) |
| |
| #define | GPDMA0_REQDSTREG_WE_CH7_Pos (15UL) |
| |
| #define | GPDMA0_REQDSTREG_WE_CH7_Msk (0x8000UL) |
| |
| #define | GPDMA0_SGLREQSRCREG_CH0_Pos (0UL) |
| |
| #define | GPDMA0_SGLREQSRCREG_CH0_Msk (0x1UL) |
| |
| #define | GPDMA0_SGLREQSRCREG_CH1_Pos (1UL) |
| |
| #define | GPDMA0_SGLREQSRCREG_CH1_Msk (0x2UL) |
| |
| #define | GPDMA0_SGLREQSRCREG_CH2_Pos (2UL) |
| |
| #define | GPDMA0_SGLREQSRCREG_CH2_Msk (0x4UL) |
| |
| #define | GPDMA0_SGLREQSRCREG_CH3_Pos (3UL) |
| |
| #define | GPDMA0_SGLREQSRCREG_CH3_Msk (0x8UL) |
| |
| #define | GPDMA0_SGLREQSRCREG_CH4_Pos (4UL) |
| |
| #define | GPDMA0_SGLREQSRCREG_CH4_Msk (0x10UL) |
| |
| #define | GPDMA0_SGLREQSRCREG_CH5_Pos (5UL) |
| |
| #define | GPDMA0_SGLREQSRCREG_CH5_Msk (0x20UL) |
| |
| #define | GPDMA0_SGLREQSRCREG_CH6_Pos (6UL) |
| |
| #define | GPDMA0_SGLREQSRCREG_CH6_Msk (0x40UL) |
| |
| #define | GPDMA0_SGLREQSRCREG_CH7_Pos (7UL) |
| |
| #define | GPDMA0_SGLREQSRCREG_CH7_Msk (0x80UL) |
| |
| #define | GPDMA0_SGLREQSRCREG_WE_CH0_Pos (8UL) |
| |
| #define | GPDMA0_SGLREQSRCREG_WE_CH0_Msk (0x100UL) |
| |
| #define | GPDMA0_SGLREQSRCREG_WE_CH1_Pos (9UL) |
| |
| #define | GPDMA0_SGLREQSRCREG_WE_CH1_Msk (0x200UL) |
| |
| #define | GPDMA0_SGLREQSRCREG_WE_CH2_Pos (10UL) |
| |
| #define | GPDMA0_SGLREQSRCREG_WE_CH2_Msk (0x400UL) |
| |
| #define | GPDMA0_SGLREQSRCREG_WE_CH3_Pos (11UL) |
| |
| #define | GPDMA0_SGLREQSRCREG_WE_CH3_Msk (0x800UL) |
| |
| #define | GPDMA0_SGLREQSRCREG_WE_CH4_Pos (12UL) |
| |
| #define | GPDMA0_SGLREQSRCREG_WE_CH4_Msk (0x1000UL) |
| |
| #define | GPDMA0_SGLREQSRCREG_WE_CH5_Pos (13UL) |
| |
| #define | GPDMA0_SGLREQSRCREG_WE_CH5_Msk (0x2000UL) |
| |
| #define | GPDMA0_SGLREQSRCREG_WE_CH6_Pos (14UL) |
| |
| #define | GPDMA0_SGLREQSRCREG_WE_CH6_Msk (0x4000UL) |
| |
| #define | GPDMA0_SGLREQSRCREG_WE_CH7_Pos (15UL) |
| |
| #define | GPDMA0_SGLREQSRCREG_WE_CH7_Msk (0x8000UL) |
| |
| #define | GPDMA0_SGLREQDSTREG_CH0_Pos (0UL) |
| |
| #define | GPDMA0_SGLREQDSTREG_CH0_Msk (0x1UL) |
| |
| #define | GPDMA0_SGLREQDSTREG_CH1_Pos (1UL) |
| |
| #define | GPDMA0_SGLREQDSTREG_CH1_Msk (0x2UL) |
| |
| #define | GPDMA0_SGLREQDSTREG_CH2_Pos (2UL) |
| |
| #define | GPDMA0_SGLREQDSTREG_CH2_Msk (0x4UL) |
| |
| #define | GPDMA0_SGLREQDSTREG_CH3_Pos (3UL) |
| |
| #define | GPDMA0_SGLREQDSTREG_CH3_Msk (0x8UL) |
| |
| #define | GPDMA0_SGLREQDSTREG_CH4_Pos (4UL) |
| |
| #define | GPDMA0_SGLREQDSTREG_CH4_Msk (0x10UL) |
| |
| #define | GPDMA0_SGLREQDSTREG_CH5_Pos (5UL) |
| |
| #define | GPDMA0_SGLREQDSTREG_CH5_Msk (0x20UL) |
| |
| #define | GPDMA0_SGLREQDSTREG_CH6_Pos (6UL) |
| |
| #define | GPDMA0_SGLREQDSTREG_CH6_Msk (0x40UL) |
| |
| #define | GPDMA0_SGLREQDSTREG_CH7_Pos (7UL) |
| |
| #define | GPDMA0_SGLREQDSTREG_CH7_Msk (0x80UL) |
| |
| #define | GPDMA0_SGLREQDSTREG_WE_CH0_Pos (8UL) |
| |
| #define | GPDMA0_SGLREQDSTREG_WE_CH0_Msk (0x100UL) |
| |
| #define | GPDMA0_SGLREQDSTREG_WE_CH1_Pos (9UL) |
| |
| #define | GPDMA0_SGLREQDSTREG_WE_CH1_Msk (0x200UL) |
| |
| #define | GPDMA0_SGLREQDSTREG_WE_CH2_Pos (10UL) |
| |
| #define | GPDMA0_SGLREQDSTREG_WE_CH2_Msk (0x400UL) |
| |
| #define | GPDMA0_SGLREQDSTREG_WE_CH3_Pos (11UL) |
| |
| #define | GPDMA0_SGLREQDSTREG_WE_CH3_Msk (0x800UL) |
| |
| #define | GPDMA0_SGLREQDSTREG_WE_CH4_Pos (12UL) |
| |
| #define | GPDMA0_SGLREQDSTREG_WE_CH4_Msk (0x1000UL) |
| |
| #define | GPDMA0_SGLREQDSTREG_WE_CH5_Pos (13UL) |
| |
| #define | GPDMA0_SGLREQDSTREG_WE_CH5_Msk (0x2000UL) |
| |
| #define | GPDMA0_SGLREQDSTREG_WE_CH6_Pos (14UL) |
| |
| #define | GPDMA0_SGLREQDSTREG_WE_CH6_Msk (0x4000UL) |
| |
| #define | GPDMA0_SGLREQDSTREG_WE_CH7_Pos (15UL) |
| |
| #define | GPDMA0_SGLREQDSTREG_WE_CH7_Msk (0x8000UL) |
| |
| #define | GPDMA0_LSTSRCREG_CH0_Pos (0UL) |
| |
| #define | GPDMA0_LSTSRCREG_CH0_Msk (0x1UL) |
| |
| #define | GPDMA0_LSTSRCREG_CH1_Pos (1UL) |
| |
| #define | GPDMA0_LSTSRCREG_CH1_Msk (0x2UL) |
| |
| #define | GPDMA0_LSTSRCREG_CH2_Pos (2UL) |
| |
| #define | GPDMA0_LSTSRCREG_CH2_Msk (0x4UL) |
| |
| #define | GPDMA0_LSTSRCREG_CH3_Pos (3UL) |
| |
| #define | GPDMA0_LSTSRCREG_CH3_Msk (0x8UL) |
| |
| #define | GPDMA0_LSTSRCREG_CH4_Pos (4UL) |
| |
| #define | GPDMA0_LSTSRCREG_CH4_Msk (0x10UL) |
| |
| #define | GPDMA0_LSTSRCREG_CH5_Pos (5UL) |
| |
| #define | GPDMA0_LSTSRCREG_CH5_Msk (0x20UL) |
| |
| #define | GPDMA0_LSTSRCREG_CH6_Pos (6UL) |
| |
| #define | GPDMA0_LSTSRCREG_CH6_Msk (0x40UL) |
| |
| #define | GPDMA0_LSTSRCREG_CH7_Pos (7UL) |
| |
| #define | GPDMA0_LSTSRCREG_CH7_Msk (0x80UL) |
| |
| #define | GPDMA0_LSTSRCREG_WE_CH0_Pos (8UL) |
| |
| #define | GPDMA0_LSTSRCREG_WE_CH0_Msk (0x100UL) |
| |
| #define | GPDMA0_LSTSRCREG_WE_CH1_Pos (9UL) |
| |
| #define | GPDMA0_LSTSRCREG_WE_CH1_Msk (0x200UL) |
| |
| #define | GPDMA0_LSTSRCREG_WE_CH2_Pos (10UL) |
| |
| #define | GPDMA0_LSTSRCREG_WE_CH2_Msk (0x400UL) |
| |
| #define | GPDMA0_LSTSRCREG_WE_CH3_Pos (11UL) |
| |
| #define | GPDMA0_LSTSRCREG_WE_CH3_Msk (0x800UL) |
| |
| #define | GPDMA0_LSTSRCREG_WE_CH4_Pos (12UL) |
| |
| #define | GPDMA0_LSTSRCREG_WE_CH4_Msk (0x1000UL) |
| |
| #define | GPDMA0_LSTSRCREG_WE_CH5_Pos (13UL) |
| |
| #define | GPDMA0_LSTSRCREG_WE_CH5_Msk (0x2000UL) |
| |
| #define | GPDMA0_LSTSRCREG_WE_CH6_Pos (14UL) |
| |
| #define | GPDMA0_LSTSRCREG_WE_CH6_Msk (0x4000UL) |
| |
| #define | GPDMA0_LSTSRCREG_WE_CH7_Pos (15UL) |
| |
| #define | GPDMA0_LSTSRCREG_WE_CH7_Msk (0x8000UL) |
| |
| #define | GPDMA0_LSTDSTREG_CH0_Pos (0UL) |
| |
| #define | GPDMA0_LSTDSTREG_CH0_Msk (0x1UL) |
| |
| #define | GPDMA0_LSTDSTREG_CH1_Pos (1UL) |
| |
| #define | GPDMA0_LSTDSTREG_CH1_Msk (0x2UL) |
| |
| #define | GPDMA0_LSTDSTREG_CH2_Pos (2UL) |
| |
| #define | GPDMA0_LSTDSTREG_CH2_Msk (0x4UL) |
| |
| #define | GPDMA0_LSTDSTREG_CH3_Pos (3UL) |
| |
| #define | GPDMA0_LSTDSTREG_CH3_Msk (0x8UL) |
| |
| #define | GPDMA0_LSTDSTREG_CH4_Pos (4UL) |
| |
| #define | GPDMA0_LSTDSTREG_CH4_Msk (0x10UL) |
| |
| #define | GPDMA0_LSTDSTREG_CH5_Pos (5UL) |
| |
| #define | GPDMA0_LSTDSTREG_CH5_Msk (0x20UL) |
| |
| #define | GPDMA0_LSTDSTREG_CH6_Pos (6UL) |
| |
| #define | GPDMA0_LSTDSTREG_CH6_Msk (0x40UL) |
| |
| #define | GPDMA0_LSTDSTREG_CH7_Pos (7UL) |
| |
| #define | GPDMA0_LSTDSTREG_CH7_Msk (0x80UL) |
| |
| #define | GPDMA0_LSTDSTREG_WE_CH0_Pos (8UL) |
| |
| #define | GPDMA0_LSTDSTREG_WE_CH0_Msk (0x100UL) |
| |
| #define | GPDMA0_LSTDSTREG_WE_CH1_Pos (9UL) |
| |
| #define | GPDMA0_LSTDSTREG_WE_CH1_Msk (0x200UL) |
| |
| #define | GPDMA0_LSTDSTREG_WE_CH2_Pos (10UL) |
| |
| #define | GPDMA0_LSTDSTREG_WE_CH2_Msk (0x400UL) |
| |
| #define | GPDMA0_LSTDSTREG_WE_CH3_Pos (11UL) |
| |
| #define | GPDMA0_LSTDSTREG_WE_CH3_Msk (0x800UL) |
| |
| #define | GPDMA0_LSTDSTREG_WE_CH4_Pos (12UL) |
| |
| #define | GPDMA0_LSTDSTREG_WE_CH4_Msk (0x1000UL) |
| |
| #define | GPDMA0_LSTDSTREG_WE_CH5_Pos (13UL) |
| |
| #define | GPDMA0_LSTDSTREG_WE_CH5_Msk (0x2000UL) |
| |
| #define | GPDMA0_LSTDSTREG_WE_CH6_Pos (14UL) |
| |
| #define | GPDMA0_LSTDSTREG_WE_CH6_Msk (0x4000UL) |
| |
| #define | GPDMA0_LSTDSTREG_WE_CH7_Pos (15UL) |
| |
| #define | GPDMA0_LSTDSTREG_WE_CH7_Msk (0x8000UL) |
| |
| #define | GPDMA0_DMACFGREG_DMA_EN_Pos (0UL) |
| |
| #define | GPDMA0_DMACFGREG_DMA_EN_Msk (0x1UL) |
| |
| #define | GPDMA0_CHENREG_CH_Pos (0UL) |
| |
| #define | GPDMA0_CHENREG_CH_Msk (0xffUL) |
| |
| #define | GPDMA0_CHENREG_WE_CH_Pos (8UL) |
| |
| #define | GPDMA0_CHENREG_WE_CH_Msk (0xff00UL) |
| |
| #define | GPDMA0_ID_VALUE_Pos (0UL) |
| |
| #define | GPDMA0_ID_VALUE_Msk (0xffffffffUL) |
| |
| #define | GPDMA0_TYPE_VALUE_Pos (0UL) |
| |
| #define | GPDMA0_TYPE_VALUE_Msk (0xffffffffUL) |
| |
| #define | GPDMA0_VERSION_VALUE_Pos (0UL) |
| |
| #define | GPDMA0_VERSION_VALUE_Msk (0xffffffffUL) |
| |
| #define | GPDMA0_CH_SAR_SAR_Pos (0UL) |
| |
| #define | GPDMA0_CH_SAR_SAR_Msk (0xffffffffUL) |
| |
| #define | GPDMA0_CH_DAR_DAR_Pos (0UL) |
| |
| #define | GPDMA0_CH_DAR_DAR_Msk (0xffffffffUL) |
| |
| #define | GPDMA0_CH_LLP_LOC_Pos (2UL) |
| |
| #define | GPDMA0_CH_LLP_LOC_Msk (0xfffffffcUL) |
| |
| #define | GPDMA0_CH_CTLL_INT_EN_Pos (0UL) |
| |
| #define | GPDMA0_CH_CTLL_INT_EN_Msk (0x1UL) |
| |
| #define | GPDMA0_CH_CTLL_DST_TR_WIDTH_Pos (1UL) |
| |
| #define | GPDMA0_CH_CTLL_DST_TR_WIDTH_Msk (0xeUL) |
| |
| #define | GPDMA0_CH_CTLL_SRC_TR_WIDTH_Pos (4UL) |
| |
| #define | GPDMA0_CH_CTLL_SRC_TR_WIDTH_Msk (0x70UL) |
| |
| #define | GPDMA0_CH_CTLL_DINC_Pos (7UL) |
| |
| #define | GPDMA0_CH_CTLL_DINC_Msk (0x180UL) |
| |
| #define | GPDMA0_CH_CTLL_SINC_Pos (9UL) |
| |
| #define | GPDMA0_CH_CTLL_SINC_Msk (0x600UL) |
| |
| #define | GPDMA0_CH_CTLL_DEST_MSIZE_Pos (11UL) |
| |
| #define | GPDMA0_CH_CTLL_DEST_MSIZE_Msk (0x3800UL) |
| |
| #define | GPDMA0_CH_CTLL_SRC_MSIZE_Pos (14UL) |
| |
| #define | GPDMA0_CH_CTLL_SRC_MSIZE_Msk (0x1c000UL) |
| |
| #define | GPDMA0_CH_CTLL_SRC_GATHER_EN_Pos (17UL) |
| |
| #define | GPDMA0_CH_CTLL_SRC_GATHER_EN_Msk (0x20000UL) |
| |
| #define | GPDMA0_CH_CTLL_DST_SCATTER_EN_Pos (18UL) |
| |
| #define | GPDMA0_CH_CTLL_DST_SCATTER_EN_Msk (0x40000UL) |
| |
| #define | GPDMA0_CH_CTLL_TT_FC_Pos (20UL) |
| |
| #define | GPDMA0_CH_CTLL_TT_FC_Msk (0x700000UL) |
| |
| #define | GPDMA0_CH_CTLL_LLP_DST_EN_Pos (27UL) |
| |
| #define | GPDMA0_CH_CTLL_LLP_DST_EN_Msk (0x8000000UL) |
| |
| #define | GPDMA0_CH_CTLL_LLP_SRC_EN_Pos (28UL) |
| |
| #define | GPDMA0_CH_CTLL_LLP_SRC_EN_Msk (0x10000000UL) |
| |
| #define | GPDMA0_CH_CTLH_BLOCK_TS_Pos (0UL) |
| |
| #define | GPDMA0_CH_CTLH_BLOCK_TS_Msk (0xfffUL) |
| |
| #define | GPDMA0_CH_CTLH_DONE_Pos (12UL) |
| |
| #define | GPDMA0_CH_CTLH_DONE_Msk (0x1000UL) |
| |
| #define | GPDMA0_CH_SSTAT_SSTAT_Pos (0UL) |
| |
| #define | GPDMA0_CH_SSTAT_SSTAT_Msk (0xffffffffUL) |
| |
| #define | GPDMA0_CH_DSTAT_DSTAT_Pos (0UL) |
| |
| #define | GPDMA0_CH_DSTAT_DSTAT_Msk (0xffffffffUL) |
| |
| #define | GPDMA0_CH_SSTATAR_SSTATAR_Pos (0UL) |
| |
| #define | GPDMA0_CH_SSTATAR_SSTATAR_Msk (0xffffffffUL) |
| |
| #define | GPDMA0_CH_DSTATAR_DSTATAR_Pos (0UL) |
| |
| #define | GPDMA0_CH_DSTATAR_DSTATAR_Msk (0xffffffffUL) |
| |
| #define | GPDMA0_CH_CFGL_CH_PRIOR_Pos (5UL) |
| |
| #define | GPDMA0_CH_CFGL_CH_PRIOR_Msk (0xe0UL) |
| |
| #define | GPDMA0_CH_CFGL_CH_SUSP_Pos (8UL) |
| |
| #define | GPDMA0_CH_CFGL_CH_SUSP_Msk (0x100UL) |
| |
| #define | GPDMA0_CH_CFGL_FIFO_EMPTY_Pos (9UL) |
| |
| #define | GPDMA0_CH_CFGL_FIFO_EMPTY_Msk (0x200UL) |
| |
| #define | GPDMA0_CH_CFGL_HS_SEL_DST_Pos (10UL) |
| |
| #define | GPDMA0_CH_CFGL_HS_SEL_DST_Msk (0x400UL) |
| |
| #define | GPDMA0_CH_CFGL_HS_SEL_SRC_Pos (11UL) |
| |
| #define | GPDMA0_CH_CFGL_HS_SEL_SRC_Msk (0x800UL) |
| |
| #define | GPDMA0_CH_CFGL_LOCK_CH_L_Pos (12UL) |
| |
| #define | GPDMA0_CH_CFGL_LOCK_CH_L_Msk (0x3000UL) |
| |
| #define | GPDMA0_CH_CFGL_LOCK_B_L_Pos (14UL) |
| |
| #define | GPDMA0_CH_CFGL_LOCK_B_L_Msk (0xc000UL) |
| |
| #define | GPDMA0_CH_CFGL_LOCK_CH_Pos (16UL) |
| |
| #define | GPDMA0_CH_CFGL_LOCK_CH_Msk (0x10000UL) |
| |
| #define | GPDMA0_CH_CFGL_LOCK_B_Pos (17UL) |
| |
| #define | GPDMA0_CH_CFGL_LOCK_B_Msk (0x20000UL) |
| |
| #define | GPDMA0_CH_CFGL_DST_HS_POL_Pos (18UL) |
| |
| #define | GPDMA0_CH_CFGL_DST_HS_POL_Msk (0x40000UL) |
| |
| #define | GPDMA0_CH_CFGL_SRC_HS_POL_Pos (19UL) |
| |
| #define | GPDMA0_CH_CFGL_SRC_HS_POL_Msk (0x80000UL) |
| |
| #define | GPDMA0_CH_CFGL_MAX_ABRST_Pos (20UL) |
| |
| #define | GPDMA0_CH_CFGL_MAX_ABRST_Msk (0x3ff00000UL) |
| |
| #define | GPDMA0_CH_CFGL_RELOAD_SRC_Pos (30UL) |
| |
| #define | GPDMA0_CH_CFGL_RELOAD_SRC_Msk (0x40000000UL) |
| |
| #define | GPDMA0_CH_CFGL_RELOAD_DST_Pos (31UL) |
| |
| #define | GPDMA0_CH_CFGL_RELOAD_DST_Msk (0x80000000UL) |
| |
| #define | GPDMA0_CH_CFGH_FCMODE_Pos (0UL) |
| |
| #define | GPDMA0_CH_CFGH_FCMODE_Msk (0x1UL) |
| |
| #define | GPDMA0_CH_CFGH_FIFO_MODE_Pos (1UL) |
| |
| #define | GPDMA0_CH_CFGH_FIFO_MODE_Msk (0x2UL) |
| |
| #define | GPDMA0_CH_CFGH_PROTCTL_Pos (2UL) |
| |
| #define | GPDMA0_CH_CFGH_PROTCTL_Msk (0x1cUL) |
| |
| #define | GPDMA0_CH_CFGH_DS_UPD_EN_Pos (5UL) |
| |
| #define | GPDMA0_CH_CFGH_DS_UPD_EN_Msk (0x20UL) |
| |
| #define | GPDMA0_CH_CFGH_SS_UPD_EN_Pos (6UL) |
| |
| #define | GPDMA0_CH_CFGH_SS_UPD_EN_Msk (0x40UL) |
| |
| #define | GPDMA0_CH_CFGH_SRC_PER_Pos (7UL) |
| |
| #define | GPDMA0_CH_CFGH_SRC_PER_Msk (0x780UL) |
| |
| #define | GPDMA0_CH_CFGH_DEST_PER_Pos (11UL) |
| |
| #define | GPDMA0_CH_CFGH_DEST_PER_Msk (0x7800UL) |
| |
| #define | GPDMA0_CH_SGR_SGI_Pos (0UL) |
| |
| #define | GPDMA0_CH_SGR_SGI_Msk (0xfffffUL) |
| |
| #define | GPDMA0_CH_SGR_SGC_Pos (20UL) |
| |
| #define | GPDMA0_CH_SGR_SGC_Msk (0xfff00000UL) |
| |
| #define | GPDMA0_CH_DSR_DSI_Pos (0UL) |
| |
| #define | GPDMA0_CH_DSR_DSI_Msk (0xfffffUL) |
| |
| #define | GPDMA0_CH_DSR_DSC_Pos (20UL) |
| |
| #define | GPDMA0_CH_DSR_DSC_Msk (0xfff00000UL) |
| |
| #define | GPDMA1_RAWTFR_CH0_Pos (0UL) |
| |
| #define | GPDMA1_RAWTFR_CH0_Msk (0x1UL) |
| |
| #define | GPDMA1_RAWTFR_CH1_Pos (1UL) |
| |
| #define | GPDMA1_RAWTFR_CH1_Msk (0x2UL) |
| |
| #define | GPDMA1_RAWTFR_CH2_Pos (2UL) |
| |
| #define | GPDMA1_RAWTFR_CH2_Msk (0x4UL) |
| |
| #define | GPDMA1_RAWTFR_CH3_Pos (3UL) |
| |
| #define | GPDMA1_RAWTFR_CH3_Msk (0x8UL) |
| |
| #define | GPDMA1_RAWBLOCK_CH0_Pos (0UL) |
| |
| #define | GPDMA1_RAWBLOCK_CH0_Msk (0x1UL) |
| |
| #define | GPDMA1_RAWBLOCK_CH1_Pos (1UL) |
| |
| #define | GPDMA1_RAWBLOCK_CH1_Msk (0x2UL) |
| |
| #define | GPDMA1_RAWBLOCK_CH2_Pos (2UL) |
| |
| #define | GPDMA1_RAWBLOCK_CH2_Msk (0x4UL) |
| |
| #define | GPDMA1_RAWBLOCK_CH3_Pos (3UL) |
| |
| #define | GPDMA1_RAWBLOCK_CH3_Msk (0x8UL) |
| |
| #define | GPDMA1_RAWSRCTRAN_CH0_Pos (0UL) |
| |
| #define | GPDMA1_RAWSRCTRAN_CH0_Msk (0x1UL) |
| |
| #define | GPDMA1_RAWSRCTRAN_CH1_Pos (1UL) |
| |
| #define | GPDMA1_RAWSRCTRAN_CH1_Msk (0x2UL) |
| |
| #define | GPDMA1_RAWSRCTRAN_CH2_Pos (2UL) |
| |
| #define | GPDMA1_RAWSRCTRAN_CH2_Msk (0x4UL) |
| |
| #define | GPDMA1_RAWSRCTRAN_CH3_Pos (3UL) |
| |
| #define | GPDMA1_RAWSRCTRAN_CH3_Msk (0x8UL) |
| |
| #define | GPDMA1_RAWDSTTRAN_CH0_Pos (0UL) |
| |
| #define | GPDMA1_RAWDSTTRAN_CH0_Msk (0x1UL) |
| |
| #define | GPDMA1_RAWDSTTRAN_CH1_Pos (1UL) |
| |
| #define | GPDMA1_RAWDSTTRAN_CH1_Msk (0x2UL) |
| |
| #define | GPDMA1_RAWDSTTRAN_CH2_Pos (2UL) |
| |
| #define | GPDMA1_RAWDSTTRAN_CH2_Msk (0x4UL) |
| |
| #define | GPDMA1_RAWDSTTRAN_CH3_Pos (3UL) |
| |
| #define | GPDMA1_RAWDSTTRAN_CH3_Msk (0x8UL) |
| |
| #define | GPDMA1_RAWERR_CH0_Pos (0UL) |
| |
| #define | GPDMA1_RAWERR_CH0_Msk (0x1UL) |
| |
| #define | GPDMA1_RAWERR_CH1_Pos (1UL) |
| |
| #define | GPDMA1_RAWERR_CH1_Msk (0x2UL) |
| |
| #define | GPDMA1_RAWERR_CH2_Pos (2UL) |
| |
| #define | GPDMA1_RAWERR_CH2_Msk (0x4UL) |
| |
| #define | GPDMA1_RAWERR_CH3_Pos (3UL) |
| |
| #define | GPDMA1_RAWERR_CH3_Msk (0x8UL) |
| |
| #define | GPDMA1_STATUSTFR_CH0_Pos (0UL) |
| |
| #define | GPDMA1_STATUSTFR_CH0_Msk (0x1UL) |
| |
| #define | GPDMA1_STATUSTFR_CH1_Pos (1UL) |
| |
| #define | GPDMA1_STATUSTFR_CH1_Msk (0x2UL) |
| |
| #define | GPDMA1_STATUSTFR_CH2_Pos (2UL) |
| |
| #define | GPDMA1_STATUSTFR_CH2_Msk (0x4UL) |
| |
| #define | GPDMA1_STATUSTFR_CH3_Pos (3UL) |
| |
| #define | GPDMA1_STATUSTFR_CH3_Msk (0x8UL) |
| |
| #define | GPDMA1_STATUSBLOCK_CH0_Pos (0UL) |
| |
| #define | GPDMA1_STATUSBLOCK_CH0_Msk (0x1UL) |
| |
| #define | GPDMA1_STATUSBLOCK_CH1_Pos (1UL) |
| |
| #define | GPDMA1_STATUSBLOCK_CH1_Msk (0x2UL) |
| |
| #define | GPDMA1_STATUSBLOCK_CH2_Pos (2UL) |
| |
| #define | GPDMA1_STATUSBLOCK_CH2_Msk (0x4UL) |
| |
| #define | GPDMA1_STATUSBLOCK_CH3_Pos (3UL) |
| |
| #define | GPDMA1_STATUSBLOCK_CH3_Msk (0x8UL) |
| |
| #define | GPDMA1_STATUSSRCTRAN_CH0_Pos (0UL) |
| |
| #define | GPDMA1_STATUSSRCTRAN_CH0_Msk (0x1UL) |
| |
| #define | GPDMA1_STATUSSRCTRAN_CH1_Pos (1UL) |
| |
| #define | GPDMA1_STATUSSRCTRAN_CH1_Msk (0x2UL) |
| |
| #define | GPDMA1_STATUSSRCTRAN_CH2_Pos (2UL) |
| |
| #define | GPDMA1_STATUSSRCTRAN_CH2_Msk (0x4UL) |
| |
| #define | GPDMA1_STATUSSRCTRAN_CH3_Pos (3UL) |
| |
| #define | GPDMA1_STATUSSRCTRAN_CH3_Msk (0x8UL) |
| |
| #define | GPDMA1_STATUSDSTTRAN_CH0_Pos (0UL) |
| |
| #define | GPDMA1_STATUSDSTTRAN_CH0_Msk (0x1UL) |
| |
| #define | GPDMA1_STATUSDSTTRAN_CH1_Pos (1UL) |
| |
| #define | GPDMA1_STATUSDSTTRAN_CH1_Msk (0x2UL) |
| |
| #define | GPDMA1_STATUSDSTTRAN_CH2_Pos (2UL) |
| |
| #define | GPDMA1_STATUSDSTTRAN_CH2_Msk (0x4UL) |
| |
| #define | GPDMA1_STATUSDSTTRAN_CH3_Pos (3UL) |
| |
| #define | GPDMA1_STATUSDSTTRAN_CH3_Msk (0x8UL) |
| |
| #define | GPDMA1_STATUSERR_CH0_Pos (0UL) |
| |
| #define | GPDMA1_STATUSERR_CH0_Msk (0x1UL) |
| |
| #define | GPDMA1_STATUSERR_CH1_Pos (1UL) |
| |
| #define | GPDMA1_STATUSERR_CH1_Msk (0x2UL) |
| |
| #define | GPDMA1_STATUSERR_CH2_Pos (2UL) |
| |
| #define | GPDMA1_STATUSERR_CH2_Msk (0x4UL) |
| |
| #define | GPDMA1_STATUSERR_CH3_Pos (3UL) |
| |
| #define | GPDMA1_STATUSERR_CH3_Msk (0x8UL) |
| |
| #define | GPDMA1_MASKTFR_CH0_Pos (0UL) |
| |
| #define | GPDMA1_MASKTFR_CH0_Msk (0x1UL) |
| |
| #define | GPDMA1_MASKTFR_CH1_Pos (1UL) |
| |
| #define | GPDMA1_MASKTFR_CH1_Msk (0x2UL) |
| |
| #define | GPDMA1_MASKTFR_CH2_Pos (2UL) |
| |
| #define | GPDMA1_MASKTFR_CH2_Msk (0x4UL) |
| |
| #define | GPDMA1_MASKTFR_CH3_Pos (3UL) |
| |
| #define | GPDMA1_MASKTFR_CH3_Msk (0x8UL) |
| |
| #define | GPDMA1_MASKTFR_WE_CH0_Pos (8UL) |
| |
| #define | GPDMA1_MASKTFR_WE_CH0_Msk (0x100UL) |
| |
| #define | GPDMA1_MASKTFR_WE_CH1_Pos (9UL) |
| |
| #define | GPDMA1_MASKTFR_WE_CH1_Msk (0x200UL) |
| |
| #define | GPDMA1_MASKTFR_WE_CH2_Pos (10UL) |
| |
| #define | GPDMA1_MASKTFR_WE_CH2_Msk (0x400UL) |
| |
| #define | GPDMA1_MASKTFR_WE_CH3_Pos (11UL) |
| |
| #define | GPDMA1_MASKTFR_WE_CH3_Msk (0x800UL) |
| |
| #define | GPDMA1_MASKBLOCK_CH0_Pos (0UL) |
| |
| #define | GPDMA1_MASKBLOCK_CH0_Msk (0x1UL) |
| |
| #define | GPDMA1_MASKBLOCK_CH1_Pos (1UL) |
| |
| #define | GPDMA1_MASKBLOCK_CH1_Msk (0x2UL) |
| |
| #define | GPDMA1_MASKBLOCK_CH2_Pos (2UL) |
| |
| #define | GPDMA1_MASKBLOCK_CH2_Msk (0x4UL) |
| |
| #define | GPDMA1_MASKBLOCK_CH3_Pos (3UL) |
| |
| #define | GPDMA1_MASKBLOCK_CH3_Msk (0x8UL) |
| |
| #define | GPDMA1_MASKBLOCK_WE_CH0_Pos (8UL) |
| |
| #define | GPDMA1_MASKBLOCK_WE_CH0_Msk (0x100UL) |
| |
| #define | GPDMA1_MASKBLOCK_WE_CH1_Pos (9UL) |
| |
| #define | GPDMA1_MASKBLOCK_WE_CH1_Msk (0x200UL) |
| |
| #define | GPDMA1_MASKBLOCK_WE_CH2_Pos (10UL) |
| |
| #define | GPDMA1_MASKBLOCK_WE_CH2_Msk (0x400UL) |
| |
| #define | GPDMA1_MASKBLOCK_WE_CH3_Pos (11UL) |
| |
| #define | GPDMA1_MASKBLOCK_WE_CH3_Msk (0x800UL) |
| |
| #define | GPDMA1_MASKSRCTRAN_CH0_Pos (0UL) |
| |
| #define | GPDMA1_MASKSRCTRAN_CH0_Msk (0x1UL) |
| |
| #define | GPDMA1_MASKSRCTRAN_CH1_Pos (1UL) |
| |
| #define | GPDMA1_MASKSRCTRAN_CH1_Msk (0x2UL) |
| |
| #define | GPDMA1_MASKSRCTRAN_CH2_Pos (2UL) |
| |
| #define | GPDMA1_MASKSRCTRAN_CH2_Msk (0x4UL) |
| |
| #define | GPDMA1_MASKSRCTRAN_CH3_Pos (3UL) |
| |
| #define | GPDMA1_MASKSRCTRAN_CH3_Msk (0x8UL) |
| |
| #define | GPDMA1_MASKSRCTRAN_WE_CH0_Pos (8UL) |
| |
| #define | GPDMA1_MASKSRCTRAN_WE_CH0_Msk (0x100UL) |
| |
| #define | GPDMA1_MASKSRCTRAN_WE_CH1_Pos (9UL) |
| |
| #define | GPDMA1_MASKSRCTRAN_WE_CH1_Msk (0x200UL) |
| |
| #define | GPDMA1_MASKSRCTRAN_WE_CH2_Pos (10UL) |
| |
| #define | GPDMA1_MASKSRCTRAN_WE_CH2_Msk (0x400UL) |
| |
| #define | GPDMA1_MASKSRCTRAN_WE_CH3_Pos (11UL) |
| |
| #define | GPDMA1_MASKSRCTRAN_WE_CH3_Msk (0x800UL) |
| |
| #define | GPDMA1_MASKDSTTRAN_CH0_Pos (0UL) |
| |
| #define | GPDMA1_MASKDSTTRAN_CH0_Msk (0x1UL) |
| |
| #define | GPDMA1_MASKDSTTRAN_CH1_Pos (1UL) |
| |
| #define | GPDMA1_MASKDSTTRAN_CH1_Msk (0x2UL) |
| |
| #define | GPDMA1_MASKDSTTRAN_CH2_Pos (2UL) |
| |
| #define | GPDMA1_MASKDSTTRAN_CH2_Msk (0x4UL) |
| |
| #define | GPDMA1_MASKDSTTRAN_CH3_Pos (3UL) |
| |
| #define | GPDMA1_MASKDSTTRAN_CH3_Msk (0x8UL) |
| |
| #define | GPDMA1_MASKDSTTRAN_WE_CH0_Pos (8UL) |
| |
| #define | GPDMA1_MASKDSTTRAN_WE_CH0_Msk (0x100UL) |
| |
| #define | GPDMA1_MASKDSTTRAN_WE_CH1_Pos (9UL) |
| |
| #define | GPDMA1_MASKDSTTRAN_WE_CH1_Msk (0x200UL) |
| |
| #define | GPDMA1_MASKDSTTRAN_WE_CH2_Pos (10UL) |
| |
| #define | GPDMA1_MASKDSTTRAN_WE_CH2_Msk (0x400UL) |
| |
| #define | GPDMA1_MASKDSTTRAN_WE_CH3_Pos (11UL) |
| |
| #define | GPDMA1_MASKDSTTRAN_WE_CH3_Msk (0x800UL) |
| |
| #define | GPDMA1_MASKERR_CH0_Pos (0UL) |
| |
| #define | GPDMA1_MASKERR_CH0_Msk (0x1UL) |
| |
| #define | GPDMA1_MASKERR_CH1_Pos (1UL) |
| |
| #define | GPDMA1_MASKERR_CH1_Msk (0x2UL) |
| |
| #define | GPDMA1_MASKERR_CH2_Pos (2UL) |
| |
| #define | GPDMA1_MASKERR_CH2_Msk (0x4UL) |
| |
| #define | GPDMA1_MASKERR_CH3_Pos (3UL) |
| |
| #define | GPDMA1_MASKERR_CH3_Msk (0x8UL) |
| |
| #define | GPDMA1_MASKERR_WE_CH0_Pos (8UL) |
| |
| #define | GPDMA1_MASKERR_WE_CH0_Msk (0x100UL) |
| |
| #define | GPDMA1_MASKERR_WE_CH1_Pos (9UL) |
| |
| #define | GPDMA1_MASKERR_WE_CH1_Msk (0x200UL) |
| |
| #define | GPDMA1_MASKERR_WE_CH2_Pos (10UL) |
| |
| #define | GPDMA1_MASKERR_WE_CH2_Msk (0x400UL) |
| |
| #define | GPDMA1_MASKERR_WE_CH3_Pos (11UL) |
| |
| #define | GPDMA1_MASKERR_WE_CH3_Msk (0x800UL) |
| |
| #define | GPDMA1_CLEARTFR_CH0_Pos (0UL) |
| |
| #define | GPDMA1_CLEARTFR_CH0_Msk (0x1UL) |
| |
| #define | GPDMA1_CLEARTFR_CH1_Pos (1UL) |
| |
| #define | GPDMA1_CLEARTFR_CH1_Msk (0x2UL) |
| |
| #define | GPDMA1_CLEARTFR_CH2_Pos (2UL) |
| |
| #define | GPDMA1_CLEARTFR_CH2_Msk (0x4UL) |
| |
| #define | GPDMA1_CLEARTFR_CH3_Pos (3UL) |
| |
| #define | GPDMA1_CLEARTFR_CH3_Msk (0x8UL) |
| |
| #define | GPDMA1_CLEARBLOCK_CH0_Pos (0UL) |
| |
| #define | GPDMA1_CLEARBLOCK_CH0_Msk (0x1UL) |
| |
| #define | GPDMA1_CLEARBLOCK_CH1_Pos (1UL) |
| |
| #define | GPDMA1_CLEARBLOCK_CH1_Msk (0x2UL) |
| |
| #define | GPDMA1_CLEARBLOCK_CH2_Pos (2UL) |
| |
| #define | GPDMA1_CLEARBLOCK_CH2_Msk (0x4UL) |
| |
| #define | GPDMA1_CLEARBLOCK_CH3_Pos (3UL) |
| |
| #define | GPDMA1_CLEARBLOCK_CH3_Msk (0x8UL) |
| |
| #define | GPDMA1_CLEARSRCTRAN_CH0_Pos (0UL) |
| |
| #define | GPDMA1_CLEARSRCTRAN_CH0_Msk (0x1UL) |
| |
| #define | GPDMA1_CLEARSRCTRAN_CH1_Pos (1UL) |
| |
| #define | GPDMA1_CLEARSRCTRAN_CH1_Msk (0x2UL) |
| |
| #define | GPDMA1_CLEARSRCTRAN_CH2_Pos (2UL) |
| |
| #define | GPDMA1_CLEARSRCTRAN_CH2_Msk (0x4UL) |
| |
| #define | GPDMA1_CLEARSRCTRAN_CH3_Pos (3UL) |
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| #define | GPDMA1_CLEARSRCTRAN_CH3_Msk (0x8UL) |
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| #define | GPDMA1_CLEARDSTTRAN_CH0_Pos (0UL) |
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| #define | GPDMA1_CLEARDSTTRAN_CH0_Msk (0x1UL) |
| |
| #define | GPDMA1_CLEARDSTTRAN_CH1_Pos (1UL) |
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| #define | GPDMA1_CLEARDSTTRAN_CH1_Msk (0x2UL) |
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| #define | GPDMA1_CLEARDSTTRAN_CH2_Pos (2UL) |
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| #define | GPDMA1_CLEARDSTTRAN_CH2_Msk (0x4UL) |
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| #define | GPDMA1_CLEARDSTTRAN_CH3_Pos (3UL) |
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| #define | GPDMA1_CLEARDSTTRAN_CH3_Msk (0x8UL) |
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| #define | GPDMA1_CLEARERR_CH0_Pos (0UL) |
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| #define | GPDMA1_CLEARERR_CH0_Msk (0x1UL) |
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| #define | GPDMA1_CLEARERR_CH1_Pos (1UL) |
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| #define | GPDMA1_CLEARERR_CH1_Msk (0x2UL) |
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| #define | GPDMA1_CLEARERR_CH2_Pos (2UL) |
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| #define | GPDMA1_CLEARERR_CH2_Msk (0x4UL) |
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| #define | GPDMA1_CLEARERR_CH3_Pos (3UL) |
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| #define | GPDMA1_CLEARERR_CH3_Msk (0x8UL) |
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| #define | GPDMA1_STATUSINT_TFR_Pos (0UL) |
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| #define | GPDMA1_STATUSINT_TFR_Msk (0x1UL) |
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| #define | GPDMA1_STATUSINT_BLOCK_Pos (1UL) |
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| #define | GPDMA1_STATUSINT_BLOCK_Msk (0x2UL) |
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| #define | GPDMA1_STATUSINT_SRCT_Pos (2UL) |
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| #define | GPDMA1_STATUSINT_SRCT_Msk (0x4UL) |
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| #define | GPDMA1_STATUSINT_DSTT_Pos (3UL) |
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| #define | GPDMA1_STATUSINT_DSTT_Msk (0x8UL) |
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| #define | GPDMA1_STATUSINT_ERR_Pos (4UL) |
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| #define | GPDMA1_STATUSINT_ERR_Msk (0x10UL) |
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| #define | GPDMA1_REQSRCREG_CH0_Pos (0UL) |
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| #define | GPDMA1_REQSRCREG_CH0_Msk (0x1UL) |
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| #define | GPDMA1_REQSRCREG_CH1_Pos (1UL) |
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| #define | GPDMA1_REQSRCREG_CH1_Msk (0x2UL) |
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| #define | GPDMA1_REQSRCREG_CH2_Pos (2UL) |
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| #define | GPDMA1_REQSRCREG_CH2_Msk (0x4UL) |
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| #define | GPDMA1_REQSRCREG_CH3_Pos (3UL) |
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| #define | GPDMA1_REQSRCREG_CH3_Msk (0x8UL) |
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| #define | GPDMA1_REQSRCREG_WE_CH0_Pos (8UL) |
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| #define | GPDMA1_REQSRCREG_WE_CH0_Msk (0x100UL) |
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| #define | GPDMA1_REQSRCREG_WE_CH1_Pos (9UL) |
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| #define | GPDMA1_REQSRCREG_WE_CH1_Msk (0x200UL) |
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| #define | GPDMA1_REQSRCREG_WE_CH2_Pos (10UL) |
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| #define | GPDMA1_REQSRCREG_WE_CH2_Msk (0x400UL) |
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| #define | GPDMA1_REQSRCREG_WE_CH3_Pos (11UL) |
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| #define | GPDMA1_REQSRCREG_WE_CH3_Msk (0x800UL) |
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| #define | GPDMA1_REQDSTREG_CH0_Pos (0UL) |
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| #define | GPDMA1_REQDSTREG_CH0_Msk (0x1UL) |
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| #define | GPDMA1_REQDSTREG_CH1_Pos (1UL) |
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| #define | GPDMA1_REQDSTREG_CH1_Msk (0x2UL) |
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| #define | GPDMA1_REQDSTREG_CH2_Pos (2UL) |
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| #define | GPDMA1_REQDSTREG_CH2_Msk (0x4UL) |
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| #define | GPDMA1_REQDSTREG_CH3_Pos (3UL) |
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| #define | GPDMA1_REQDSTREG_CH3_Msk (0x8UL) |
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| #define | GPDMA1_REQDSTREG_WE_CH0_Pos (8UL) |
| |
| #define | GPDMA1_REQDSTREG_WE_CH0_Msk (0x100UL) |
| |
| #define | GPDMA1_REQDSTREG_WE_CH1_Pos (9UL) |
| |
| #define | GPDMA1_REQDSTREG_WE_CH1_Msk (0x200UL) |
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| #define | GPDMA1_REQDSTREG_WE_CH2_Pos (10UL) |
| |
| #define | GPDMA1_REQDSTREG_WE_CH2_Msk (0x400UL) |
| |
| #define | GPDMA1_REQDSTREG_WE_CH3_Pos (11UL) |
| |
| #define | GPDMA1_REQDSTREG_WE_CH3_Msk (0x800UL) |
| |
| #define | GPDMA1_SGLREQSRCREG_CH0_Pos (0UL) |
| |
| #define | GPDMA1_SGLREQSRCREG_CH0_Msk (0x1UL) |
| |
| #define | GPDMA1_SGLREQSRCREG_CH1_Pos (1UL) |
| |
| #define | GPDMA1_SGLREQSRCREG_CH1_Msk (0x2UL) |
| |
| #define | GPDMA1_SGLREQSRCREG_CH2_Pos (2UL) |
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| #define | GPDMA1_SGLREQSRCREG_CH2_Msk (0x4UL) |
| |
| #define | GPDMA1_SGLREQSRCREG_CH3_Pos (3UL) |
| |
| #define | GPDMA1_SGLREQSRCREG_CH3_Msk (0x8UL) |
| |
| #define | GPDMA1_SGLREQSRCREG_WE_CH0_Pos (8UL) |
| |
| #define | GPDMA1_SGLREQSRCREG_WE_CH0_Msk (0x100UL) |
| |
| #define | GPDMA1_SGLREQSRCREG_WE_CH1_Pos (9UL) |
| |
| #define | GPDMA1_SGLREQSRCREG_WE_CH1_Msk (0x200UL) |
| |
| #define | GPDMA1_SGLREQSRCREG_WE_CH2_Pos (10UL) |
| |
| #define | GPDMA1_SGLREQSRCREG_WE_CH2_Msk (0x400UL) |
| |
| #define | GPDMA1_SGLREQSRCREG_WE_CH3_Pos (11UL) |
| |
| #define | GPDMA1_SGLREQSRCREG_WE_CH3_Msk (0x800UL) |
| |
| #define | GPDMA1_SGLREQDSTREG_CH0_Pos (0UL) |
| |
| #define | GPDMA1_SGLREQDSTREG_CH0_Msk (0x1UL) |
| |
| #define | GPDMA1_SGLREQDSTREG_CH1_Pos (1UL) |
| |
| #define | GPDMA1_SGLREQDSTREG_CH1_Msk (0x2UL) |
| |
| #define | GPDMA1_SGLREQDSTREG_CH2_Pos (2UL) |
| |
| #define | GPDMA1_SGLREQDSTREG_CH2_Msk (0x4UL) |
| |
| #define | GPDMA1_SGLREQDSTREG_CH3_Pos (3UL) |
| |
| #define | GPDMA1_SGLREQDSTREG_CH3_Msk (0x8UL) |
| |
| #define | GPDMA1_SGLREQDSTREG_WE_CH0_Pos (8UL) |
| |
| #define | GPDMA1_SGLREQDSTREG_WE_CH0_Msk (0x100UL) |
| |
| #define | GPDMA1_SGLREQDSTREG_WE_CH1_Pos (9UL) |
| |
| #define | GPDMA1_SGLREQDSTREG_WE_CH1_Msk (0x200UL) |
| |
| #define | GPDMA1_SGLREQDSTREG_WE_CH2_Pos (10UL) |
| |
| #define | GPDMA1_SGLREQDSTREG_WE_CH2_Msk (0x400UL) |
| |
| #define | GPDMA1_SGLREQDSTREG_WE_CH3_Pos (11UL) |
| |
| #define | GPDMA1_SGLREQDSTREG_WE_CH3_Msk (0x800UL) |
| |
| #define | GPDMA1_LSTSRCREG_CH0_Pos (0UL) |
| |
| #define | GPDMA1_LSTSRCREG_CH0_Msk (0x1UL) |
| |
| #define | GPDMA1_LSTSRCREG_CH1_Pos (1UL) |
| |
| #define | GPDMA1_LSTSRCREG_CH1_Msk (0x2UL) |
| |
| #define | GPDMA1_LSTSRCREG_CH2_Pos (2UL) |
| |
| #define | GPDMA1_LSTSRCREG_CH2_Msk (0x4UL) |
| |
| #define | GPDMA1_LSTSRCREG_CH3_Pos (3UL) |
| |
| #define | GPDMA1_LSTSRCREG_CH3_Msk (0x8UL) |
| |
| #define | GPDMA1_LSTSRCREG_WE_CH0_Pos (8UL) |
| |
| #define | GPDMA1_LSTSRCREG_WE_CH0_Msk (0x100UL) |
| |
| #define | GPDMA1_LSTSRCREG_WE_CH1_Pos (9UL) |
| |
| #define | GPDMA1_LSTSRCREG_WE_CH1_Msk (0x200UL) |
| |
| #define | GPDMA1_LSTSRCREG_WE_CH2_Pos (10UL) |
| |
| #define | GPDMA1_LSTSRCREG_WE_CH2_Msk (0x400UL) |
| |
| #define | GPDMA1_LSTSRCREG_WE_CH3_Pos (11UL) |
| |
| #define | GPDMA1_LSTSRCREG_WE_CH3_Msk (0x800UL) |
| |
| #define | GPDMA1_LSTDSTREG_CH0_Pos (0UL) |
| |
| #define | GPDMA1_LSTDSTREG_CH0_Msk (0x1UL) |
| |
| #define | GPDMA1_LSTDSTREG_CH1_Pos (1UL) |
| |
| #define | GPDMA1_LSTDSTREG_CH1_Msk (0x2UL) |
| |
| #define | GPDMA1_LSTDSTREG_CH2_Pos (2UL) |
| |
| #define | GPDMA1_LSTDSTREG_CH2_Msk (0x4UL) |
| |
| #define | GPDMA1_LSTDSTREG_CH3_Pos (3UL) |
| |
| #define | GPDMA1_LSTDSTREG_CH3_Msk (0x8UL) |
| |
| #define | GPDMA1_LSTDSTREG_WE_CH0_Pos (8UL) |
| |
| #define | GPDMA1_LSTDSTREG_WE_CH0_Msk (0x100UL) |
| |
| #define | GPDMA1_LSTDSTREG_WE_CH1_Pos (9UL) |
| |
| #define | GPDMA1_LSTDSTREG_WE_CH1_Msk (0x200UL) |
| |
| #define | GPDMA1_LSTDSTREG_WE_CH2_Pos (10UL) |
| |
| #define | GPDMA1_LSTDSTREG_WE_CH2_Msk (0x400UL) |
| |
| #define | GPDMA1_LSTDSTREG_WE_CH3_Pos (11UL) |
| |
| #define | GPDMA1_LSTDSTREG_WE_CH3_Msk (0x800UL) |
| |
| #define | GPDMA1_DMACFGREG_DMA_EN_Pos (0UL) |
| |
| #define | GPDMA1_DMACFGREG_DMA_EN_Msk (0x1UL) |
| |
| #define | GPDMA1_CHENREG_CH_Pos (0UL) |
| |
| #define | GPDMA1_CHENREG_CH_Msk (0xfUL) |
| |
| #define | GPDMA1_CHENREG_WE_CH_Pos (8UL) |
| |
| #define | GPDMA1_CHENREG_WE_CH_Msk (0xf00UL) |
| |
| #define | GPDMA1_ID_VALUE_Pos (0UL) |
| |
| #define | GPDMA1_ID_VALUE_Msk (0xffffffffUL) |
| |
| #define | GPDMA1_TYPE_VALUE_Pos (0UL) |
| |
| #define | GPDMA1_TYPE_VALUE_Msk (0xffffffffUL) |
| |
| #define | GPDMA1_VERSION_VALUE_Pos (0UL) |
| |
| #define | GPDMA1_VERSION_VALUE_Msk (0xffffffffUL) |
| |
| #define | GPDMA1_CH_SAR_SAR_Pos (0UL) |
| |
| #define | GPDMA1_CH_SAR_SAR_Msk (0xffffffffUL) |
| |
| #define | GPDMA1_CH_DAR_DAR_Pos (0UL) |
| |
| #define | GPDMA1_CH_DAR_DAR_Msk (0xffffffffUL) |
| |
| #define | GPDMA1_CH_CTLL_INT_EN_Pos (0UL) |
| |
| #define | GPDMA1_CH_CTLL_INT_EN_Msk (0x1UL) |
| |
| #define | GPDMA1_CH_CTLL_DST_TR_WIDTH_Pos (1UL) |
| |
| #define | GPDMA1_CH_CTLL_DST_TR_WIDTH_Msk (0xeUL) |
| |
| #define | GPDMA1_CH_CTLL_SRC_TR_WIDTH_Pos (4UL) |
| |
| #define | GPDMA1_CH_CTLL_SRC_TR_WIDTH_Msk (0x70UL) |
| |
| #define | GPDMA1_CH_CTLL_DINC_Pos (7UL) |
| |
| #define | GPDMA1_CH_CTLL_DINC_Msk (0x180UL) |
| |
| #define | GPDMA1_CH_CTLL_SINC_Pos (9UL) |
| |
| #define | GPDMA1_CH_CTLL_SINC_Msk (0x600UL) |
| |
| #define | GPDMA1_CH_CTLL_DEST_MSIZE_Pos (11UL) |
| |
| #define | GPDMA1_CH_CTLL_DEST_MSIZE_Msk (0x3800UL) |
| |
| #define | GPDMA1_CH_CTLL_SRC_MSIZE_Pos (14UL) |
| |
| #define | GPDMA1_CH_CTLL_SRC_MSIZE_Msk (0x1c000UL) |
| |
| #define | GPDMA1_CH_CTLL_TT_FC_Pos (20UL) |
| |
| #define | GPDMA1_CH_CTLL_TT_FC_Msk (0x700000UL) |
| |
| #define | GPDMA1_CH_CTLH_BLOCK_TS_Pos (0UL) |
| |
| #define | GPDMA1_CH_CTLH_BLOCK_TS_Msk (0xfffUL) |
| |
| #define | GPDMA1_CH_CTLH_DONE_Pos (12UL) |
| |
| #define | GPDMA1_CH_CTLH_DONE_Msk (0x1000UL) |
| |
| #define | GPDMA1_CH_CFGL_CH_PRIOR_Pos (5UL) |
| |
| #define | GPDMA1_CH_CFGL_CH_PRIOR_Msk (0xe0UL) |
| |
| #define | GPDMA1_CH_CFGL_CH_SUSP_Pos (8UL) |
| |
| #define | GPDMA1_CH_CFGL_CH_SUSP_Msk (0x100UL) |
| |
| #define | GPDMA1_CH_CFGL_FIFO_EMPTY_Pos (9UL) |
| |
| #define | GPDMA1_CH_CFGL_FIFO_EMPTY_Msk (0x200UL) |
| |
| #define | GPDMA1_CH_CFGL_HS_SEL_DST_Pos (10UL) |
| |
| #define | GPDMA1_CH_CFGL_HS_SEL_DST_Msk (0x400UL) |
| |
| #define | GPDMA1_CH_CFGL_HS_SEL_SRC_Pos (11UL) |
| |
| #define | GPDMA1_CH_CFGL_HS_SEL_SRC_Msk (0x800UL) |
| |
| #define | GPDMA1_CH_CFGL_LOCK_CH_L_Pos (12UL) |
| |
| #define | GPDMA1_CH_CFGL_LOCK_CH_L_Msk (0x3000UL) |
| |
| #define | GPDMA1_CH_CFGL_LOCK_B_L_Pos (14UL) |
| |
| #define | GPDMA1_CH_CFGL_LOCK_B_L_Msk (0xc000UL) |
| |
| #define | GPDMA1_CH_CFGL_LOCK_CH_Pos (16UL) |
| |
| #define | GPDMA1_CH_CFGL_LOCK_CH_Msk (0x10000UL) |
| |
| #define | GPDMA1_CH_CFGL_LOCK_B_Pos (17UL) |
| |
| #define | GPDMA1_CH_CFGL_LOCK_B_Msk (0x20000UL) |
| |
| #define | GPDMA1_CH_CFGL_DST_HS_POL_Pos (18UL) |
| |
| #define | GPDMA1_CH_CFGL_DST_HS_POL_Msk (0x40000UL) |
| |
| #define | GPDMA1_CH_CFGL_SRC_HS_POL_Pos (19UL) |
| |
| #define | GPDMA1_CH_CFGL_SRC_HS_POL_Msk (0x80000UL) |
| |
| #define | GPDMA1_CH_CFGL_MAX_ABRST_Pos (20UL) |
| |
| #define | GPDMA1_CH_CFGL_MAX_ABRST_Msk (0x3ff00000UL) |
| |
| #define | GPDMA1_CH_CFGH_FCMODE_Pos (0UL) |
| |
| #define | GPDMA1_CH_CFGH_FCMODE_Msk (0x1UL) |
| |
| #define | GPDMA1_CH_CFGH_FIFO_MODE_Pos (1UL) |
| |
| #define | GPDMA1_CH_CFGH_FIFO_MODE_Msk (0x2UL) |
| |
| #define | GPDMA1_CH_CFGH_PROTCTL_Pos (2UL) |
| |
| #define | GPDMA1_CH_CFGH_PROTCTL_Msk (0x1cUL) |
| |
| #define | GPDMA1_CH_CFGH_SRC_PER_Pos (7UL) |
| |
| #define | GPDMA1_CH_CFGH_SRC_PER_Msk (0x780UL) |
| |
| #define | GPDMA1_CH_CFGH_DEST_PER_Pos (11UL) |
| |
| #define | GPDMA1_CH_CFGH_DEST_PER_Msk (0x7800UL) |
| |
| #define | FCE_CLC_DISR_Pos (0UL) |
| |
| #define | FCE_CLC_DISR_Msk (0x1UL) |
| |
| #define | FCE_CLC_DISS_Pos (1UL) |
| |
| #define | FCE_CLC_DISS_Msk (0x2UL) |
| |
| #define | FCE_ID_MOD_REV_Pos (0UL) |
| |
| #define | FCE_ID_MOD_REV_Msk (0xffUL) |
| |
| #define | FCE_ID_MOD_TYPE_Pos (8UL) |
| |
| #define | FCE_ID_MOD_TYPE_Msk (0xff00UL) |
| |
| #define | FCE_ID_MOD_NUMBER_Pos (16UL) |
| |
| #define | FCE_ID_MOD_NUMBER_Msk (0xffff0000UL) |
| |
| #define | FCE_KE_IR_IR_Pos (0UL) |
| |
| #define | FCE_KE_IR_IR_Msk (0xffffffffUL) |
| |
| #define | FCE_KE_RES_RES_Pos (0UL) |
| |
| #define | FCE_KE_RES_RES_Msk (0xffffffffUL) |
| |
| #define | FCE_KE_CFG_CMI_Pos (0UL) |
| |
| #define | FCE_KE_CFG_CMI_Msk (0x1UL) |
| |
| #define | FCE_KE_CFG_CEI_Pos (1UL) |
| |
| #define | FCE_KE_CFG_CEI_Msk (0x2UL) |
| |
| #define | FCE_KE_CFG_LEI_Pos (2UL) |
| |
| #define | FCE_KE_CFG_LEI_Msk (0x4UL) |
| |
| #define | FCE_KE_CFG_BEI_Pos (3UL) |
| |
| #define | FCE_KE_CFG_BEI_Msk (0x8UL) |
| |
| #define | FCE_KE_CFG_CCE_Pos (4UL) |
| |
| #define | FCE_KE_CFG_CCE_Msk (0x10UL) |
| |
| #define | FCE_KE_CFG_ALR_Pos (5UL) |
| |
| #define | FCE_KE_CFG_ALR_Msk (0x20UL) |
| |
| #define | FCE_KE_CFG_REFIN_Pos (8UL) |
| |
| #define | FCE_KE_CFG_REFIN_Msk (0x100UL) |
| |
| #define | FCE_KE_CFG_REFOUT_Pos (9UL) |
| |
| #define | FCE_KE_CFG_REFOUT_Msk (0x200UL) |
| |
| #define | FCE_KE_CFG_XSEL_Pos (10UL) |
| |
| #define | FCE_KE_CFG_XSEL_Msk (0x400UL) |
| |
| #define | FCE_KE_STS_CMF_Pos (0UL) |
| |
| #define | FCE_KE_STS_CMF_Msk (0x1UL) |
| |
| #define | FCE_KE_STS_CEF_Pos (1UL) |
| |
| #define | FCE_KE_STS_CEF_Msk (0x2UL) |
| |
| #define | FCE_KE_STS_LEF_Pos (2UL) |
| |
| #define | FCE_KE_STS_LEF_Msk (0x4UL) |
| |
| #define | FCE_KE_STS_BEF_Pos (3UL) |
| |
| #define | FCE_KE_STS_BEF_Msk (0x8UL) |
| |
| #define | FCE_KE_LENGTH_LENGTH_Pos (0UL) |
| |
| #define | FCE_KE_LENGTH_LENGTH_Msk (0xffffUL) |
| |
| #define | FCE_KE_CHECK_CHECK_Pos (0UL) |
| |
| #define | FCE_KE_CHECK_CHECK_Msk (0xffffffffUL) |
| |
| #define | FCE_KE_CRC_CRC_Pos (0UL) |
| |
| #define | FCE_KE_CRC_CRC_Msk (0xffffffffUL) |
| |
| #define | FCE_KE_CTR_FCM_Pos (0UL) |
| |
| #define | FCE_KE_CTR_FCM_Msk (0x1UL) |
| |
| #define | FCE_KE_CTR_FRM_CFG_Pos (1UL) |
| |
| #define | FCE_KE_CTR_FRM_CFG_Msk (0x2UL) |
| |
| #define | FCE_KE_CTR_FRM_CHECK_Pos (2UL) |
| |
| #define | FCE_KE_CTR_FRM_CHECK_Msk (0x4UL) |
| |
| #define | PBA_STS_WERR_Pos (0UL) |
| |
| #define | PBA_STS_WERR_Msk (0x1UL) |
| |
| #define | PBA_WADDR_WADDR_Pos (0UL) |
| |
| #define | PBA_WADDR_WADDR_Msk (0xffffffffUL) |
| |
| #define | FLASH_ID_MOD_REV_Pos (0UL) |
| |
| #define | FLASH_ID_MOD_REV_Msk (0xffUL) |
| |
| #define | FLASH_ID_MOD_TYPE_Pos (8UL) |
| |
| #define | FLASH_ID_MOD_TYPE_Msk (0xff00UL) |
| |
| #define | FLASH_ID_MOD_NUMBER_Pos (16UL) |
| |
| #define | FLASH_ID_MOD_NUMBER_Msk (0xffff0000UL) |
| |
| #define | FLASH_FSR_PBUSY_Pos (0UL) |
| |
| #define | FLASH_FSR_PBUSY_Msk (0x1UL) |
| |
| #define | FLASH_FSR_FABUSY_Pos (1UL) |
| |
| #define | FLASH_FSR_FABUSY_Msk (0x2UL) |
| |
| #define | FLASH_FSR_PROG_Pos (4UL) |
| |
| #define | FLASH_FSR_PROG_Msk (0x10UL) |
| |
| #define | FLASH_FSR_ERASE_Pos (5UL) |
| |
| #define | FLASH_FSR_ERASE_Msk (0x20UL) |
| |
| #define | FLASH_FSR_PFPAGE_Pos (6UL) |
| |
| #define | FLASH_FSR_PFPAGE_Msk (0x40UL) |
| |
| #define | FLASH_FSR_PFOPER_Pos (8UL) |
| |
| #define | FLASH_FSR_PFOPER_Msk (0x100UL) |
| |
| #define | FLASH_FSR_SQER_Pos (10UL) |
| |
| #define | FLASH_FSR_SQER_Msk (0x400UL) |
| |
| #define | FLASH_FSR_PROER_Pos (11UL) |
| |
| #define | FLASH_FSR_PROER_Msk (0x800UL) |
| |
| #define | FLASH_FSR_PFSBER_Pos (12UL) |
| |
| #define | FLASH_FSR_PFSBER_Msk (0x1000UL) |
| |
| #define | FLASH_FSR_PFDBER_Pos (14UL) |
| |
| #define | FLASH_FSR_PFDBER_Msk (0x4000UL) |
| |
| #define | FLASH_FSR_PROIN_Pos (16UL) |
| |
| #define | FLASH_FSR_PROIN_Msk (0x10000UL) |
| |
| #define | FLASH_FSR_RPROIN_Pos (18UL) |
| |
| #define | FLASH_FSR_RPROIN_Msk (0x40000UL) |
| |
| #define | FLASH_FSR_RPRODIS_Pos (19UL) |
| |
| #define | FLASH_FSR_RPRODIS_Msk (0x80000UL) |
| |
| #define | FLASH_FSR_WPROIN0_Pos (21UL) |
| |
| #define | FLASH_FSR_WPROIN0_Msk (0x200000UL) |
| |
| #define | FLASH_FSR_WPROIN1_Pos (22UL) |
| |
| #define | FLASH_FSR_WPROIN1_Msk (0x400000UL) |
| |
| #define | FLASH_FSR_WPROIN2_Pos (23UL) |
| |
| #define | FLASH_FSR_WPROIN2_Msk (0x800000UL) |
| |
| #define | FLASH_FSR_WPRODIS0_Pos (25UL) |
| |
| #define | FLASH_FSR_WPRODIS0_Msk (0x2000000UL) |
| |
| #define | FLASH_FSR_WPRODIS1_Pos (26UL) |
| |
| #define | FLASH_FSR_WPRODIS1_Msk (0x4000000UL) |
| |
| #define | FLASH_FSR_SLM_Pos (28UL) |
| |
| #define | FLASH_FSR_SLM_Msk (0x10000000UL) |
| |
| #define | FLASH_FSR_VER_Pos (31UL) |
| |
| #define | FLASH_FSR_VER_Msk (0x80000000UL) |
| |
| #define | FLASH_FCON_WSPFLASH_Pos (0UL) |
| |
| #define | FLASH_FCON_WSPFLASH_Msk (0xfUL) |
| |
| #define | FLASH_FCON_WSECPF_Pos (4UL) |
| |
| #define | FLASH_FCON_WSECPF_Msk (0x10UL) |
| |
| #define | FLASH_FCON_IDLE_Pos (13UL) |
| |
| #define | FLASH_FCON_IDLE_Msk (0x2000UL) |
| |
| #define | FLASH_FCON_ESLDIS_Pos (14UL) |
| |
| #define | FLASH_FCON_ESLDIS_Msk (0x4000UL) |
| |
| #define | FLASH_FCON_SLEEP_Pos (15UL) |
| |
| #define | FLASH_FCON_SLEEP_Msk (0x8000UL) |
| |
| #define | FLASH_FCON_RPA_Pos (16UL) |
| |
| #define | FLASH_FCON_RPA_Msk (0x10000UL) |
| |
| #define | FLASH_FCON_DCF_Pos (17UL) |
| |
| #define | FLASH_FCON_DCF_Msk (0x20000UL) |
| |
| #define | FLASH_FCON_DDF_Pos (18UL) |
| |
| #define | FLASH_FCON_DDF_Msk (0x40000UL) |
| |
| #define | FLASH_FCON_VOPERM_Pos (24UL) |
| |
| #define | FLASH_FCON_VOPERM_Msk (0x1000000UL) |
| |
| #define | FLASH_FCON_SQERM_Pos (25UL) |
| |
| #define | FLASH_FCON_SQERM_Msk (0x2000000UL) |
| |
| #define | FLASH_FCON_PROERM_Pos (26UL) |
| |
| #define | FLASH_FCON_PROERM_Msk (0x4000000UL) |
| |
| #define | FLASH_FCON_PFSBERM_Pos (27UL) |
| |
| #define | FLASH_FCON_PFSBERM_Msk (0x8000000UL) |
| |
| #define | FLASH_FCON_PFDBERM_Pos (29UL) |
| |
| #define | FLASH_FCON_PFDBERM_Msk (0x20000000UL) |
| |
| #define | FLASH_FCON_EOBM_Pos (31UL) |
| |
| #define | FLASH_FCON_EOBM_Msk (0x80000000UL) |
| |
| #define | FLASH_MARP_MARGIN_Pos (0UL) |
| |
| #define | FLASH_MARP_MARGIN_Msk (0xfUL) |
| |
| #define | FLASH_MARP_TRAPDIS_Pos (15UL) |
| |
| #define | FLASH_MARP_TRAPDIS_Msk (0x8000UL) |
| |
| #define | FLASH_PROCON0_S0L_Pos (0UL) |
| |
| #define | FLASH_PROCON0_S0L_Msk (0x1UL) |
| |
| #define | FLASH_PROCON0_S1L_Pos (1UL) |
| |
| #define | FLASH_PROCON0_S1L_Msk (0x2UL) |
| |
| #define | FLASH_PROCON0_S2L_Pos (2UL) |
| |
| #define | FLASH_PROCON0_S2L_Msk (0x4UL) |
| |
| #define | FLASH_PROCON0_S3L_Pos (3UL) |
| |
| #define | FLASH_PROCON0_S3L_Msk (0x8UL) |
| |
| #define | FLASH_PROCON0_S4L_Pos (4UL) |
| |
| #define | FLASH_PROCON0_S4L_Msk (0x10UL) |
| |
| #define | FLASH_PROCON0_S5L_Pos (5UL) |
| |
| #define | FLASH_PROCON0_S5L_Msk (0x20UL) |
| |
| #define | FLASH_PROCON0_S6L_Pos (6UL) |
| |
| #define | FLASH_PROCON0_S6L_Msk (0x40UL) |
| |
| #define | FLASH_PROCON0_S7L_Pos (7UL) |
| |
| #define | FLASH_PROCON0_S7L_Msk (0x80UL) |
| |
| #define | FLASH_PROCON0_S8L_Pos (8UL) |
| |
| #define | FLASH_PROCON0_S8L_Msk (0x100UL) |
| |
| #define | FLASH_PROCON0_S9L_Pos (9UL) |
| |
| #define | FLASH_PROCON0_S9L_Msk (0x200UL) |
| |
| #define | FLASH_PROCON0_S10_S11L_Pos (10UL) |
| |
| #define | FLASH_PROCON0_S10_S11L_Msk (0x400UL) |
| |
| #define | FLASH_PROCON0_S12_S13L_Pos (11UL) |
| |
| #define | FLASH_PROCON0_S12_S13L_Msk (0x800UL) |
| |
| #define | FLASH_PROCON0_S14_S15L_Pos (12UL) |
| |
| #define | FLASH_PROCON0_S14_S15L_Msk (0x1000UL) |
| |
| #define | FLASH_PROCON0_RPRO_Pos (15UL) |
| |
| #define | FLASH_PROCON0_RPRO_Msk (0x8000UL) |
| |
| #define | FLASH_PROCON1_S0L_Pos (0UL) |
| |
| #define | FLASH_PROCON1_S0L_Msk (0x1UL) |
| |
| #define | FLASH_PROCON1_S1L_Pos (1UL) |
| |
| #define | FLASH_PROCON1_S1L_Msk (0x2UL) |
| |
| #define | FLASH_PROCON1_S2L_Pos (2UL) |
| |
| #define | FLASH_PROCON1_S2L_Msk (0x4UL) |
| |
| #define | FLASH_PROCON1_S3L_Pos (3UL) |
| |
| #define | FLASH_PROCON1_S3L_Msk (0x8UL) |
| |
| #define | FLASH_PROCON1_S4L_Pos (4UL) |
| |
| #define | FLASH_PROCON1_S4L_Msk (0x10UL) |
| |
| #define | FLASH_PROCON1_S5L_Pos (5UL) |
| |
| #define | FLASH_PROCON1_S5L_Msk (0x20UL) |
| |
| #define | FLASH_PROCON1_S6L_Pos (6UL) |
| |
| #define | FLASH_PROCON1_S6L_Msk (0x40UL) |
| |
| #define | FLASH_PROCON1_S7L_Pos (7UL) |
| |
| #define | FLASH_PROCON1_S7L_Msk (0x80UL) |
| |
| #define | FLASH_PROCON1_S8L_Pos (8UL) |
| |
| #define | FLASH_PROCON1_S8L_Msk (0x100UL) |
| |
| #define | FLASH_PROCON1_S9L_Pos (9UL) |
| |
| #define | FLASH_PROCON1_S9L_Msk (0x200UL) |
| |
| #define | FLASH_PROCON1_S10_S11L_Pos (10UL) |
| |
| #define | FLASH_PROCON1_S10_S11L_Msk (0x400UL) |
| |
| #define | FLASH_PROCON1_S12_S13L_Pos (11UL) |
| |
| #define | FLASH_PROCON1_S12_S13L_Msk (0x800UL) |
| |
| #define | FLASH_PROCON1_S14_S15L_Pos (12UL) |
| |
| #define | FLASH_PROCON1_S14_S15L_Msk (0x1000UL) |
| |
| #define | FLASH_PROCON1_PSR_Pos (16UL) |
| |
| #define | FLASH_PROCON1_PSR_Msk (0x10000UL) |
| |
| #define | FLASH_PROCON2_S0ROM_Pos (0UL) |
| |
| #define | FLASH_PROCON2_S0ROM_Msk (0x1UL) |
| |
| #define | FLASH_PROCON2_S1ROM_Pos (1UL) |
| |
| #define | FLASH_PROCON2_S1ROM_Msk (0x2UL) |
| |
| #define | FLASH_PROCON2_S2ROM_Pos (2UL) |
| |
| #define | FLASH_PROCON2_S2ROM_Msk (0x4UL) |
| |
| #define | FLASH_PROCON2_S3ROM_Pos (3UL) |
| |
| #define | FLASH_PROCON2_S3ROM_Msk (0x8UL) |
| |
| #define | FLASH_PROCON2_S4ROM_Pos (4UL) |
| |
| #define | FLASH_PROCON2_S4ROM_Msk (0x10UL) |
| |
| #define | FLASH_PROCON2_S5ROM_Pos (5UL) |
| |
| #define | FLASH_PROCON2_S5ROM_Msk (0x20UL) |
| |
| #define | FLASH_PROCON2_S6ROM_Pos (6UL) |
| |
| #define | FLASH_PROCON2_S6ROM_Msk (0x40UL) |
| |
| #define | FLASH_PROCON2_S7ROM_Pos (7UL) |
| |
| #define | FLASH_PROCON2_S7ROM_Msk (0x80UL) |
| |
| #define | FLASH_PROCON2_S8ROM_Pos (8UL) |
| |
| #define | FLASH_PROCON2_S8ROM_Msk (0x100UL) |
| |
| #define | FLASH_PROCON2_S9ROM_Pos (9UL) |
| |
| #define | FLASH_PROCON2_S9ROM_Msk (0x200UL) |
| |
| #define | FLASH_PROCON2_S10_S11ROM_Pos (10UL) |
| |
| #define | FLASH_PROCON2_S10_S11ROM_Msk (0x400UL) |
| |
| #define | FLASH_PROCON2_S12_S13ROM_Pos (11UL) |
| |
| #define | FLASH_PROCON2_S12_S13ROM_Msk (0x800UL) |
| |
| #define | FLASH_PROCON2_S14_S15ROM_Pos (12UL) |
| |
| #define | FLASH_PROCON2_S14_S15ROM_Msk (0x1000UL) |
| |
| #define | PREF_PCON_IBYP_Pos (0UL) |
| |
| #define | PREF_PCON_IBYP_Msk (0x1UL) |
| |
| #define | PREF_PCON_IINV_Pos (1UL) |
| |
| #define | PREF_PCON_IINV_Msk (0x2UL) |
| |
| #define | PREF_PCON_DBYP_Pos (4UL) |
| |
| #define | PREF_PCON_DBYP_Msk (0x10UL) |
| |
| #define | PMU_ID_MOD_REV_Pos (0UL) |
| |
| #define | PMU_ID_MOD_REV_Msk (0xffUL) |
| |
| #define | PMU_ID_MOD_TYPE_Pos (8UL) |
| |
| #define | PMU_ID_MOD_TYPE_Msk (0xff00UL) |
| |
| #define | PMU_ID_MOD_NUMBER_Pos (16UL) |
| |
| #define | PMU_ID_MOD_NUMBER_Msk (0xffff0000UL) |
| |
| #define | WDT_ID_MOD_REV_Pos (0UL) |
| |
| #define | WDT_ID_MOD_REV_Msk (0xffUL) |
| |
| #define | WDT_ID_MOD_TYPE_Pos (8UL) |
| |
| #define | WDT_ID_MOD_TYPE_Msk (0xff00UL) |
| |
| #define | WDT_ID_MOD_NUMBER_Pos (16UL) |
| |
| #define | WDT_ID_MOD_NUMBER_Msk (0xffff0000UL) |
| |
| #define | WDT_CTR_ENB_Pos (0UL) |
| |
| #define | WDT_CTR_ENB_Msk (0x1UL) |
| |
| #define | WDT_CTR_PRE_Pos (1UL) |
| |
| #define | WDT_CTR_PRE_Msk (0x2UL) |
| |
| #define | WDT_CTR_DSP_Pos (4UL) |
| |
| #define | WDT_CTR_DSP_Msk (0x10UL) |
| |
| #define | WDT_CTR_SPW_Pos (8UL) |
| |
| #define | WDT_CTR_SPW_Msk (0xff00UL) |
| |
| #define | WDT_SRV_SRV_Pos (0UL) |
| |
| #define | WDT_SRV_SRV_Msk (0xffffffffUL) |
| |
| #define | WDT_TIM_TIM_Pos (0UL) |
| |
| #define | WDT_TIM_TIM_Msk (0xffffffffUL) |
| |
| #define | WDT_WLB_WLB_Pos (0UL) |
| |
| #define | WDT_WLB_WLB_Msk (0xffffffffUL) |
| |
| #define | WDT_WUB_WUB_Pos (0UL) |
| |
| #define | WDT_WUB_WUB_Msk (0xffffffffUL) |
| |
| #define | WDT_WDTSTS_ALMS_Pos (0UL) |
| |
| #define | WDT_WDTSTS_ALMS_Msk (0x1UL) |
| |
| #define | WDT_WDTCLR_ALMC_Pos (0UL) |
| |
| #define | WDT_WDTCLR_ALMC_Msk (0x1UL) |
| |
| #define | RTC_ID_MOD_REV_Pos (0UL) |
| |
| #define | RTC_ID_MOD_REV_Msk (0xffUL) |
| |
| #define | RTC_ID_MOD_TYPE_Pos (8UL) |
| |
| #define | RTC_ID_MOD_TYPE_Msk (0xff00UL) |
| |
| #define | RTC_ID_MOD_NUMBER_Pos (16UL) |
| |
| #define | RTC_ID_MOD_NUMBER_Msk (0xffff0000UL) |
| |
| #define | RTC_CTR_ENB_Pos (0UL) |
| |
| #define | RTC_CTR_ENB_Msk (0x1UL) |
| |
| #define | RTC_CTR_TAE_Pos (2UL) |
| |
| #define | RTC_CTR_TAE_Msk (0x4UL) |
| |
| #define | RTC_CTR_ESEC_Pos (8UL) |
| |
| #define | RTC_CTR_ESEC_Msk (0x100UL) |
| |
| #define | RTC_CTR_EMIC_Pos (9UL) |
| |
| #define | RTC_CTR_EMIC_Msk (0x200UL) |
| |
| #define | RTC_CTR_EHOC_Pos (10UL) |
| |
| #define | RTC_CTR_EHOC_Msk (0x400UL) |
| |
| #define | RTC_CTR_EDAC_Pos (11UL) |
| |
| #define | RTC_CTR_EDAC_Msk (0x800UL) |
| |
| #define | RTC_CTR_EMOC_Pos (13UL) |
| |
| #define | RTC_CTR_EMOC_Msk (0x2000UL) |
| |
| #define | RTC_CTR_EYEC_Pos (14UL) |
| |
| #define | RTC_CTR_EYEC_Msk (0x4000UL) |
| |
| #define | RTC_CTR_DIV_Pos (16UL) |
| |
| #define | RTC_CTR_DIV_Msk (0xffff0000UL) |
| |
| #define | RTC_RAWSTAT_RPSE_Pos (0UL) |
| |
| #define | RTC_RAWSTAT_RPSE_Msk (0x1UL) |
| |
| #define | RTC_RAWSTAT_RPMI_Pos (1UL) |
| |
| #define | RTC_RAWSTAT_RPMI_Msk (0x2UL) |
| |
| #define | RTC_RAWSTAT_RPHO_Pos (2UL) |
| |
| #define | RTC_RAWSTAT_RPHO_Msk (0x4UL) |
| |
| #define | RTC_RAWSTAT_RPDA_Pos (3UL) |
| |
| #define | RTC_RAWSTAT_RPDA_Msk (0x8UL) |
| |
| #define | RTC_RAWSTAT_RPMO_Pos (5UL) |
| |
| #define | RTC_RAWSTAT_RPMO_Msk (0x20UL) |
| |
| #define | RTC_RAWSTAT_RPYE_Pos (6UL) |
| |
| #define | RTC_RAWSTAT_RPYE_Msk (0x40UL) |
| |
| #define | RTC_RAWSTAT_RAI_Pos (8UL) |
| |
| #define | RTC_RAWSTAT_RAI_Msk (0x100UL) |
| |
| #define | RTC_STSSR_SPSE_Pos (0UL) |
| |
| #define | RTC_STSSR_SPSE_Msk (0x1UL) |
| |
| #define | RTC_STSSR_SPMI_Pos (1UL) |
| |
| #define | RTC_STSSR_SPMI_Msk (0x2UL) |
| |
| #define | RTC_STSSR_SPHO_Pos (2UL) |
| |
| #define | RTC_STSSR_SPHO_Msk (0x4UL) |
| |
| #define | RTC_STSSR_SPDA_Pos (3UL) |
| |
| #define | RTC_STSSR_SPDA_Msk (0x8UL) |
| |
| #define | RTC_STSSR_SPMO_Pos (5UL) |
| |
| #define | RTC_STSSR_SPMO_Msk (0x20UL) |
| |
| #define | RTC_STSSR_SPYE_Pos (6UL) |
| |
| #define | RTC_STSSR_SPYE_Msk (0x40UL) |
| |
| #define | RTC_STSSR_SAI_Pos (8UL) |
| |
| #define | RTC_STSSR_SAI_Msk (0x100UL) |
| |
| #define | RTC_MSKSR_MPSE_Pos (0UL) |
| |
| #define | RTC_MSKSR_MPSE_Msk (0x1UL) |
| |
| #define | RTC_MSKSR_MPMI_Pos (1UL) |
| |
| #define | RTC_MSKSR_MPMI_Msk (0x2UL) |
| |
| #define | RTC_MSKSR_MPHO_Pos (2UL) |
| |
| #define | RTC_MSKSR_MPHO_Msk (0x4UL) |
| |
| #define | RTC_MSKSR_MPDA_Pos (3UL) |
| |
| #define | RTC_MSKSR_MPDA_Msk (0x8UL) |
| |
| #define | RTC_MSKSR_MPMO_Pos (5UL) |
| |
| #define | RTC_MSKSR_MPMO_Msk (0x20UL) |
| |
| #define | RTC_MSKSR_MPYE_Pos (6UL) |
| |
| #define | RTC_MSKSR_MPYE_Msk (0x40UL) |
| |
| #define | RTC_MSKSR_MAI_Pos (8UL) |
| |
| #define | RTC_MSKSR_MAI_Msk (0x100UL) |
| |
| #define | RTC_CLRSR_RPSE_Pos (0UL) |
| |
| #define | RTC_CLRSR_RPSE_Msk (0x1UL) |
| |
| #define | RTC_CLRSR_RPMI_Pos (1UL) |
| |
| #define | RTC_CLRSR_RPMI_Msk (0x2UL) |
| |
| #define | RTC_CLRSR_RPHO_Pos (2UL) |
| |
| #define | RTC_CLRSR_RPHO_Msk (0x4UL) |
| |
| #define | RTC_CLRSR_RPDA_Pos (3UL) |
| |
| #define | RTC_CLRSR_RPDA_Msk (0x8UL) |
| |
| #define | RTC_CLRSR_RPMO_Pos (5UL) |
| |
| #define | RTC_CLRSR_RPMO_Msk (0x20UL) |
| |
| #define | RTC_CLRSR_RPYE_Pos (6UL) |
| |
| #define | RTC_CLRSR_RPYE_Msk (0x40UL) |
| |
| #define | RTC_CLRSR_RAI_Pos (8UL) |
| |
| #define | RTC_CLRSR_RAI_Msk (0x100UL) |
| |
| #define | RTC_ATIM0_ASE_Pos (0UL) |
| |
| #define | RTC_ATIM0_ASE_Msk (0x3fUL) |
| |
| #define | RTC_ATIM0_AMI_Pos (8UL) |
| |
| #define | RTC_ATIM0_AMI_Msk (0x3f00UL) |
| |
| #define | RTC_ATIM0_AHO_Pos (16UL) |
| |
| #define | RTC_ATIM0_AHO_Msk (0x1f0000UL) |
| |
| #define | RTC_ATIM0_ADA_Pos (24UL) |
| |
| #define | RTC_ATIM0_ADA_Msk (0x1f000000UL) |
| |
| #define | RTC_ATIM1_AMO_Pos (8UL) |
| |
| #define | RTC_ATIM1_AMO_Msk (0xf00UL) |
| |
| #define | RTC_ATIM1_AYE_Pos (16UL) |
| |
| #define | RTC_ATIM1_AYE_Msk (0xffff0000UL) |
| |
| #define | RTC_TIM0_SE_Pos (0UL) |
| |
| #define | RTC_TIM0_SE_Msk (0x3fUL) |
| |
| #define | RTC_TIM0_MI_Pos (8UL) |
| |
| #define | RTC_TIM0_MI_Msk (0x3f00UL) |
| |
| #define | RTC_TIM0_HO_Pos (16UL) |
| |
| #define | RTC_TIM0_HO_Msk (0x1f0000UL) |
| |
| #define | RTC_TIM0_DA_Pos (24UL) |
| |
| #define | RTC_TIM0_DA_Msk (0x1f000000UL) |
| |
| #define | RTC_TIM1_DAWE_Pos (0UL) |
| |
| #define | RTC_TIM1_DAWE_Msk (0x7UL) |
| |
| #define | RTC_TIM1_MO_Pos (8UL) |
| |
| #define | RTC_TIM1_MO_Msk (0xf00UL) |
| |
| #define | RTC_TIM1_YE_Pos (16UL) |
| |
| #define | RTC_TIM1_YE_Msk (0xffff0000UL) |
| |
| #define | SCU_CLK_CLKSTAT_USBCST_Pos (0UL) |
| |
| #define | SCU_CLK_CLKSTAT_USBCST_Msk (0x1UL) |
| |
| #define | SCU_CLK_CLKSTAT_MMCCST_Pos (1UL) |
| |
| #define | SCU_CLK_CLKSTAT_MMCCST_Msk (0x2UL) |
| |
| #define | SCU_CLK_CLKSTAT_ETH0CST_Pos (2UL) |
| |
| #define | SCU_CLK_CLKSTAT_ETH0CST_Msk (0x4UL) |
| |
| #define | SCU_CLK_CLKSTAT_EBUCST_Pos (3UL) |
| |
| #define | SCU_CLK_CLKSTAT_EBUCST_Msk (0x8UL) |
| |
| #define | SCU_CLK_CLKSTAT_CCUCST_Pos (4UL) |
| |
| #define | SCU_CLK_CLKSTAT_CCUCST_Msk (0x10UL) |
| |
| #define | SCU_CLK_CLKSTAT_WDTCST_Pos (5UL) |
| |
| #define | SCU_CLK_CLKSTAT_WDTCST_Msk (0x20UL) |
| |
| #define | SCU_CLK_CLKSET_USBCEN_Pos (0UL) |
| |
| #define | SCU_CLK_CLKSET_USBCEN_Msk (0x1UL) |
| |
| #define | SCU_CLK_CLKSET_MMCCEN_Pos (1UL) |
| |
| #define | SCU_CLK_CLKSET_MMCCEN_Msk (0x2UL) |
| |
| #define | SCU_CLK_CLKSET_ETH0CEN_Pos (2UL) |
| |
| #define | SCU_CLK_CLKSET_ETH0CEN_Msk (0x4UL) |
| |
| #define | SCU_CLK_CLKSET_EBUCEN_Pos (3UL) |
| |
| #define | SCU_CLK_CLKSET_EBUCEN_Msk (0x8UL) |
| |
| #define | SCU_CLK_CLKSET_CCUCEN_Pos (4UL) |
| |
| #define | SCU_CLK_CLKSET_CCUCEN_Msk (0x10UL) |
| |
| #define | SCU_CLK_CLKSET_WDTCEN_Pos (5UL) |
| |
| #define | SCU_CLK_CLKSET_WDTCEN_Msk (0x20UL) |
| |
| #define | SCU_CLK_CLKCLR_USBCDI_Pos (0UL) |
| |
| #define | SCU_CLK_CLKCLR_USBCDI_Msk (0x1UL) |
| |
| #define | SCU_CLK_CLKCLR_MMCCDI_Pos (1UL) |
| |
| #define | SCU_CLK_CLKCLR_MMCCDI_Msk (0x2UL) |
| |
| #define | SCU_CLK_CLKCLR_ETH0CDI_Pos (2UL) |
| |
| #define | SCU_CLK_CLKCLR_ETH0CDI_Msk (0x4UL) |
| |
| #define | SCU_CLK_CLKCLR_EBUCDI_Pos (3UL) |
| |
| #define | SCU_CLK_CLKCLR_EBUCDI_Msk (0x8UL) |
| |
| #define | SCU_CLK_CLKCLR_CCUCDI_Pos (4UL) |
| |
| #define | SCU_CLK_CLKCLR_CCUCDI_Msk (0x10UL) |
| |
| #define | SCU_CLK_CLKCLR_WDTCDI_Pos (5UL) |
| |
| #define | SCU_CLK_CLKCLR_WDTCDI_Msk (0x20UL) |
| |
| #define | SCU_CLK_SYSCLKCR_SYSDIV_Pos (0UL) |
| |
| #define | SCU_CLK_SYSCLKCR_SYSDIV_Msk (0xffUL) |
| |
| #define | SCU_CLK_SYSCLKCR_SYSSEL_Pos (16UL) |
| |
| #define | SCU_CLK_SYSCLKCR_SYSSEL_Msk (0x10000UL) |
| |
| #define | SCU_CLK_CPUCLKCR_CPUDIV_Pos (0UL) |
| |
| #define | SCU_CLK_CPUCLKCR_CPUDIV_Msk (0x1UL) |
| |
| #define | SCU_CLK_PBCLKCR_PBDIV_Pos (0UL) |
| |
| #define | SCU_CLK_PBCLKCR_PBDIV_Msk (0x1UL) |
| |
| #define | SCU_CLK_USBCLKCR_USBDIV_Pos (0UL) |
| |
| #define | SCU_CLK_USBCLKCR_USBDIV_Msk (0x7UL) |
| |
| #define | SCU_CLK_USBCLKCR_USBSEL_Pos (16UL) |
| |
| #define | SCU_CLK_USBCLKCR_USBSEL_Msk (0x10000UL) |
| |
| #define | SCU_CLK_EBUCLKCR_EBUDIV_Pos (0UL) |
| |
| #define | SCU_CLK_EBUCLKCR_EBUDIV_Msk (0x3fUL) |
| |
| #define | SCU_CLK_CCUCLKCR_CCUDIV_Pos (0UL) |
| |
| #define | SCU_CLK_CCUCLKCR_CCUDIV_Msk (0x1UL) |
| |
| #define | SCU_CLK_WDTCLKCR_WDTDIV_Pos (0UL) |
| |
| #define | SCU_CLK_WDTCLKCR_WDTDIV_Msk (0xffUL) |
| |
| #define | SCU_CLK_WDTCLKCR_WDTSEL_Pos (16UL) |
| |
| #define | SCU_CLK_WDTCLKCR_WDTSEL_Msk (0x30000UL) |
| |
| #define | SCU_CLK_EXTCLKCR_ECKSEL_Pos (0UL) |
| |
| #define | SCU_CLK_EXTCLKCR_ECKSEL_Msk (0x3UL) |
| |
| #define | SCU_CLK_EXTCLKCR_ECKDIV_Pos (16UL) |
| |
| #define | SCU_CLK_EXTCLKCR_ECKDIV_Msk (0x1ff0000UL) |
| |
| #define | SCU_CLK_MLINKCLKCR_SYSDIV_Pos (0UL) |
| |
| #define | SCU_CLK_MLINKCLKCR_SYSDIV_Msk (0xffUL) |
| |
| #define | SCU_CLK_MLINKCLKCR_SYSSEL_Pos (8UL) |
| |
| #define | SCU_CLK_MLINKCLKCR_SYSSEL_Msk (0x100UL) |
| |
| #define | SCU_CLK_MLINKCLKCR_CPUDIV_Pos (10UL) |
| |
| #define | SCU_CLK_MLINKCLKCR_CPUDIV_Msk (0x400UL) |
| |
| #define | SCU_CLK_MLINKCLKCR_PBDIV_Pos (12UL) |
| |
| #define | SCU_CLK_MLINKCLKCR_PBDIV_Msk (0x1000UL) |
| |
| #define | SCU_CLK_MLINKCLKCR_CCUDIV_Pos (14UL) |
| |
| #define | SCU_CLK_MLINKCLKCR_CCUDIV_Msk (0x4000UL) |
| |
| #define | SCU_CLK_MLINKCLKCR_WDTDIV_Pos (16UL) |
| |
| #define | SCU_CLK_MLINKCLKCR_WDTDIV_Msk (0xff0000UL) |
| |
| #define | SCU_CLK_MLINKCLKCR_WDTSEL_Pos (24UL) |
| |
| #define | SCU_CLK_MLINKCLKCR_WDTSEL_Msk (0x3000000UL) |
| |
| #define | SCU_CLK_MLINKCLKCR_EBUDIV_Pos (26UL) |
| |
| #define | SCU_CLK_MLINKCLKCR_EBUDIV_Msk (0xfc000000UL) |
| |
| #define | SCU_CLK_SLEEPCR_SYSSEL_Pos (0UL) |
| |
| #define | SCU_CLK_SLEEPCR_SYSSEL_Msk (0x1UL) |
| |
| #define | SCU_CLK_SLEEPCR_USBCR_Pos (16UL) |
| |
| #define | SCU_CLK_SLEEPCR_USBCR_Msk (0x10000UL) |
| |
| #define | SCU_CLK_SLEEPCR_MMCCR_Pos (17UL) |
| |
| #define | SCU_CLK_SLEEPCR_MMCCR_Msk (0x20000UL) |
| |
| #define | SCU_CLK_SLEEPCR_ETH0CR_Pos (18UL) |
| |
| #define | SCU_CLK_SLEEPCR_ETH0CR_Msk (0x40000UL) |
| |
| #define | SCU_CLK_SLEEPCR_EBUCR_Pos (19UL) |
| |
| #define | SCU_CLK_SLEEPCR_EBUCR_Msk (0x80000UL) |
| |
| #define | SCU_CLK_SLEEPCR_CCUCR_Pos (20UL) |
| |
| #define | SCU_CLK_SLEEPCR_CCUCR_Msk (0x100000UL) |
| |
| #define | SCU_CLK_SLEEPCR_WDTCR_Pos (21UL) |
| |
| #define | SCU_CLK_SLEEPCR_WDTCR_Msk (0x200000UL) |
| |
| #define | SCU_CLK_DSLEEPCR_SYSSEL_Pos (0UL) |
| |
| #define | SCU_CLK_DSLEEPCR_SYSSEL_Msk (0x3UL) |
| |
| #define | SCU_CLK_DSLEEPCR_FPDN_Pos (11UL) |
| |
| #define | SCU_CLK_DSLEEPCR_FPDN_Msk (0x800UL) |
| |
| #define | SCU_CLK_DSLEEPCR_PLLPDN_Pos (12UL) |
| |
| #define | SCU_CLK_DSLEEPCR_PLLPDN_Msk (0x1000UL) |
| |
| #define | SCU_CLK_DSLEEPCR_VCOPDN_Pos (13UL) |
| |
| #define | SCU_CLK_DSLEEPCR_VCOPDN_Msk (0x2000UL) |
| |
| #define | SCU_CLK_DSLEEPCR_USBCR_Pos (16UL) |
| |
| #define | SCU_CLK_DSLEEPCR_USBCR_Msk (0x10000UL) |
| |
| #define | SCU_CLK_DSLEEPCR_MMCCR_Pos (17UL) |
| |
| #define | SCU_CLK_DSLEEPCR_MMCCR_Msk (0x20000UL) |
| |
| #define | SCU_CLK_DSLEEPCR_ETH0CR_Pos (18UL) |
| |
| #define | SCU_CLK_DSLEEPCR_ETH0CR_Msk (0x40000UL) |
| |
| #define | SCU_CLK_DSLEEPCR_EBUCR_Pos (19UL) |
| |
| #define | SCU_CLK_DSLEEPCR_EBUCR_Msk (0x80000UL) |
| |
| #define | SCU_CLK_DSLEEPCR_CCUCR_Pos (20UL) |
| |
| #define | SCU_CLK_DSLEEPCR_CCUCR_Msk (0x100000UL) |
| |
| #define | SCU_CLK_DSLEEPCR_WDTCR_Pos (21UL) |
| |
| #define | SCU_CLK_DSLEEPCR_WDTCR_Msk (0x200000UL) |
| |
| #define | SCU_CLK_ECATCLKCR_ECADIV_Pos (0UL) |
| |
| #define | SCU_CLK_ECATCLKCR_ECADIV_Msk (0x3UL) |
| |
| #define | SCU_CLK_ECATCLKCR_ECATSEL_Pos (16UL) |
| |
| #define | SCU_CLK_ECATCLKCR_ECATSEL_Msk (0x10000UL) |
| |
| #define | SCU_CLK_CGATSTAT0_VADC_Pos (0UL) |
| |
| #define | SCU_CLK_CGATSTAT0_VADC_Msk (0x1UL) |
| |
| #define | SCU_CLK_CGATSTAT0_DSD_Pos (1UL) |
| |
| #define | SCU_CLK_CGATSTAT0_DSD_Msk (0x2UL) |
| |
| #define | SCU_CLK_CGATSTAT0_CCU40_Pos (2UL) |
| |
| #define | SCU_CLK_CGATSTAT0_CCU40_Msk (0x4UL) |
| |
| #define | SCU_CLK_CGATSTAT0_CCU41_Pos (3UL) |
| |
| #define | SCU_CLK_CGATSTAT0_CCU41_Msk (0x8UL) |
| |
| #define | SCU_CLK_CGATSTAT0_CCU42_Pos (4UL) |
| |
| #define | SCU_CLK_CGATSTAT0_CCU42_Msk (0x10UL) |
| |
| #define | SCU_CLK_CGATSTAT0_CCU80_Pos (7UL) |
| |
| #define | SCU_CLK_CGATSTAT0_CCU80_Msk (0x80UL) |
| |
| #define | SCU_CLK_CGATSTAT0_CCU81_Pos (8UL) |
| |
| #define | SCU_CLK_CGATSTAT0_CCU81_Msk (0x100UL) |
| |
| #define | SCU_CLK_CGATSTAT0_POSIF0_Pos (9UL) |
| |
| #define | SCU_CLK_CGATSTAT0_POSIF0_Msk (0x200UL) |
| |
| #define | SCU_CLK_CGATSTAT0_POSIF1_Pos (10UL) |
| |
| #define | SCU_CLK_CGATSTAT0_POSIF1_Msk (0x400UL) |
| |
| #define | SCU_CLK_CGATSTAT0_USIC0_Pos (11UL) |
| |
| #define | SCU_CLK_CGATSTAT0_USIC0_Msk (0x800UL) |
| |
| #define | SCU_CLK_CGATSTAT0_ERU1_Pos (16UL) |
| |
| #define | SCU_CLK_CGATSTAT0_ERU1_Msk (0x10000UL) |
| |
| #define | SCU_CLK_CGATSET0_VADC_Pos (0UL) |
| |
| #define | SCU_CLK_CGATSET0_VADC_Msk (0x1UL) |
| |
| #define | SCU_CLK_CGATSET0_DSD_Pos (1UL) |
| |
| #define | SCU_CLK_CGATSET0_DSD_Msk (0x2UL) |
| |
| #define | SCU_CLK_CGATSET0_CCU40_Pos (2UL) |
| |
| #define | SCU_CLK_CGATSET0_CCU40_Msk (0x4UL) |
| |
| #define | SCU_CLK_CGATSET0_CCU41_Pos (3UL) |
| |
| #define | SCU_CLK_CGATSET0_CCU41_Msk (0x8UL) |
| |
| #define | SCU_CLK_CGATSET0_CCU42_Pos (4UL) |
| |
| #define | SCU_CLK_CGATSET0_CCU42_Msk (0x10UL) |
| |
| #define | SCU_CLK_CGATSET0_CCU80_Pos (7UL) |
| |
| #define | SCU_CLK_CGATSET0_CCU80_Msk (0x80UL) |
| |
| #define | SCU_CLK_CGATSET0_CCU81_Pos (8UL) |
| |
| #define | SCU_CLK_CGATSET0_CCU81_Msk (0x100UL) |
| |
| #define | SCU_CLK_CGATSET0_POSIF0_Pos (9UL) |
| |
| #define | SCU_CLK_CGATSET0_POSIF0_Msk (0x200UL) |
| |
| #define | SCU_CLK_CGATSET0_POSIF1_Pos (10UL) |
| |
| #define | SCU_CLK_CGATSET0_POSIF1_Msk (0x400UL) |
| |
| #define | SCU_CLK_CGATSET0_USIC0_Pos (11UL) |
| |
| #define | SCU_CLK_CGATSET0_USIC0_Msk (0x800UL) |
| |
| #define | SCU_CLK_CGATSET0_ERU1_Pos (16UL) |
| |
| #define | SCU_CLK_CGATSET0_ERU1_Msk (0x10000UL) |
| |
| #define | SCU_CLK_CGATCLR0_VADC_Pos (0UL) |
| |
| #define | SCU_CLK_CGATCLR0_VADC_Msk (0x1UL) |
| |
| #define | SCU_CLK_CGATCLR0_DSD_Pos (1UL) |
| |
| #define | SCU_CLK_CGATCLR0_DSD_Msk (0x2UL) |
| |
| #define | SCU_CLK_CGATCLR0_CCU40_Pos (2UL) |
| |
| #define | SCU_CLK_CGATCLR0_CCU40_Msk (0x4UL) |
| |
| #define | SCU_CLK_CGATCLR0_CCU41_Pos (3UL) |
| |
| #define | SCU_CLK_CGATCLR0_CCU41_Msk (0x8UL) |
| |
| #define | SCU_CLK_CGATCLR0_CCU42_Pos (4UL) |
| |
| #define | SCU_CLK_CGATCLR0_CCU42_Msk (0x10UL) |
| |
| #define | SCU_CLK_CGATCLR0_CCU80_Pos (7UL) |
| |
| #define | SCU_CLK_CGATCLR0_CCU80_Msk (0x80UL) |
| |
| #define | SCU_CLK_CGATCLR0_CCU81_Pos (8UL) |
| |
| #define | SCU_CLK_CGATCLR0_CCU81_Msk (0x100UL) |
| |
| #define | SCU_CLK_CGATCLR0_POSIF0_Pos (9UL) |
| |
| #define | SCU_CLK_CGATCLR0_POSIF0_Msk (0x200UL) |
| |
| #define | SCU_CLK_CGATCLR0_POSIF1_Pos (10UL) |
| |
| #define | SCU_CLK_CGATCLR0_POSIF1_Msk (0x400UL) |
| |
| #define | SCU_CLK_CGATCLR0_USIC0_Pos (11UL) |
| |
| #define | SCU_CLK_CGATCLR0_USIC0_Msk (0x800UL) |
| |
| #define | SCU_CLK_CGATCLR0_ERU1_Pos (16UL) |
| |
| #define | SCU_CLK_CGATCLR0_ERU1_Msk (0x10000UL) |
| |
| #define | SCU_CLK_CGATSTAT1_CCU43_Pos (0UL) |
| |
| #define | SCU_CLK_CGATSTAT1_CCU43_Msk (0x1UL) |
| |
| #define | SCU_CLK_CGATSTAT1_LEDTSCU0_Pos (3UL) |
| |
| #define | SCU_CLK_CGATSTAT1_LEDTSCU0_Msk (0x8UL) |
| |
| #define | SCU_CLK_CGATSTAT1_MCAN0_Pos (4UL) |
| |
| #define | SCU_CLK_CGATSTAT1_MCAN0_Msk (0x10UL) |
| |
| #define | SCU_CLK_CGATSTAT1_DAC_Pos (5UL) |
| |
| #define | SCU_CLK_CGATSTAT1_DAC_Msk (0x20UL) |
| |
| #define | SCU_CLK_CGATSTAT1_MMCI_Pos (6UL) |
| |
| #define | SCU_CLK_CGATSTAT1_MMCI_Msk (0x40UL) |
| |
| #define | SCU_CLK_CGATSTAT1_USIC1_Pos (7UL) |
| |
| #define | SCU_CLK_CGATSTAT1_USIC1_Msk (0x80UL) |
| |
| #define | SCU_CLK_CGATSTAT1_USIC2_Pos (8UL) |
| |
| #define | SCU_CLK_CGATSTAT1_USIC2_Msk (0x100UL) |
| |
| #define | SCU_CLK_CGATSTAT1_PPORTS_Pos (9UL) |
| |
| #define | SCU_CLK_CGATSTAT1_PPORTS_Msk (0x200UL) |
| |
| #define | SCU_CLK_CGATSET1_CCU43_Pos (0UL) |
| |
| #define | SCU_CLK_CGATSET1_CCU43_Msk (0x1UL) |
| |
| #define | SCU_CLK_CGATSET1_LEDTSCU0_Pos (3UL) |
| |
| #define | SCU_CLK_CGATSET1_LEDTSCU0_Msk (0x8UL) |
| |
| #define | SCU_CLK_CGATSET1_MCAN0_Pos (4UL) |
| |
| #define | SCU_CLK_CGATSET1_MCAN0_Msk (0x10UL) |
| |
| #define | SCU_CLK_CGATSET1_DAC_Pos (5UL) |
| |
| #define | SCU_CLK_CGATSET1_DAC_Msk (0x20UL) |
| |
| #define | SCU_CLK_CGATSET1_MMCI_Pos (6UL) |
| |
| #define | SCU_CLK_CGATSET1_MMCI_Msk (0x40UL) |
| |
| #define | SCU_CLK_CGATSET1_USIC1_Pos (7UL) |
| |
| #define | SCU_CLK_CGATSET1_USIC1_Msk (0x80UL) |
| |
| #define | SCU_CLK_CGATSET1_USIC2_Pos (8UL) |
| |
| #define | SCU_CLK_CGATSET1_USIC2_Msk (0x100UL) |
| |
| #define | SCU_CLK_CGATSET1_PPORTS_Pos (9UL) |
| |
| #define | SCU_CLK_CGATSET1_PPORTS_Msk (0x200UL) |
| |
| #define | SCU_CLK_CGATCLR1_CCU43_Pos (0UL) |
| |
| #define | SCU_CLK_CGATCLR1_CCU43_Msk (0x1UL) |
| |
| #define | SCU_CLK_CGATCLR1_LEDTSCU0_Pos (3UL) |
| |
| #define | SCU_CLK_CGATCLR1_LEDTSCU0_Msk (0x8UL) |
| |
| #define | SCU_CLK_CGATCLR1_MCAN0_Pos (4UL) |
| |
| #define | SCU_CLK_CGATCLR1_MCAN0_Msk (0x10UL) |
| |
| #define | SCU_CLK_CGATCLR1_DAC_Pos (5UL) |
| |
| #define | SCU_CLK_CGATCLR1_DAC_Msk (0x20UL) |
| |
| #define | SCU_CLK_CGATCLR1_MMCI_Pos (6UL) |
| |
| #define | SCU_CLK_CGATCLR1_MMCI_Msk (0x40UL) |
| |
| #define | SCU_CLK_CGATCLR1_USIC1_Pos (7UL) |
| |
| #define | SCU_CLK_CGATCLR1_USIC1_Msk (0x80UL) |
| |
| #define | SCU_CLK_CGATCLR1_USIC2_Pos (8UL) |
| |
| #define | SCU_CLK_CGATCLR1_USIC2_Msk (0x100UL) |
| |
| #define | SCU_CLK_CGATCLR1_PPORTS_Pos (9UL) |
| |
| #define | SCU_CLK_CGATCLR1_PPORTS_Msk (0x200UL) |
| |
| #define | SCU_CLK_CGATSTAT2_WDT_Pos (1UL) |
| |
| #define | SCU_CLK_CGATSTAT2_WDT_Msk (0x2UL) |
| |
| #define | SCU_CLK_CGATSTAT2_ETH0_Pos (2UL) |
| |
| #define | SCU_CLK_CGATSTAT2_ETH0_Msk (0x4UL) |
| |
| #define | SCU_CLK_CGATSTAT2_DMA0_Pos (4UL) |
| |
| #define | SCU_CLK_CGATSTAT2_DMA0_Msk (0x10UL) |
| |
| #define | SCU_CLK_CGATSTAT2_DMA1_Pos (5UL) |
| |
| #define | SCU_CLK_CGATSTAT2_DMA1_Msk (0x20UL) |
| |
| #define | SCU_CLK_CGATSTAT2_FCE_Pos (6UL) |
| |
| #define | SCU_CLK_CGATSTAT2_FCE_Msk (0x40UL) |
| |
| #define | SCU_CLK_CGATSTAT2_USB_Pos (7UL) |
| |
| #define | SCU_CLK_CGATSTAT2_USB_Msk (0x80UL) |
| |
| #define | SCU_CLK_CGATSTAT2_ECAT0_Pos (10UL) |
| |
| #define | SCU_CLK_CGATSTAT2_ECAT0_Msk (0x400UL) |
| |
| #define | SCU_CLK_CGATSET2_WDT_Pos (1UL) |
| |
| #define | SCU_CLK_CGATSET2_WDT_Msk (0x2UL) |
| |
| #define | SCU_CLK_CGATSET2_ETH0_Pos (2UL) |
| |
| #define | SCU_CLK_CGATSET2_ETH0_Msk (0x4UL) |
| |
| #define | SCU_CLK_CGATSET2_DMA0_Pos (4UL) |
| |
| #define | SCU_CLK_CGATSET2_DMA0_Msk (0x10UL) |
| |
| #define | SCU_CLK_CGATSET2_DMA1_Pos (5UL) |
| |
| #define | SCU_CLK_CGATSET2_DMA1_Msk (0x20UL) |
| |
| #define | SCU_CLK_CGATSET2_FCE_Pos (6UL) |
| |
| #define | SCU_CLK_CGATSET2_FCE_Msk (0x40UL) |
| |
| #define | SCU_CLK_CGATSET2_USB_Pos (7UL) |
| |
| #define | SCU_CLK_CGATSET2_USB_Msk (0x80UL) |
| |
| #define | SCU_CLK_CGATSET2_ECAT0_Pos (10UL) |
| |
| #define | SCU_CLK_CGATSET2_ECAT0_Msk (0x400UL) |
| |
| #define | SCU_CLK_CGATCLR2_WDT_Pos (1UL) |
| |
| #define | SCU_CLK_CGATCLR2_WDT_Msk (0x2UL) |
| |
| #define | SCU_CLK_CGATCLR2_ETH0_Pos (2UL) |
| |
| #define | SCU_CLK_CGATCLR2_ETH0_Msk (0x4UL) |
| |
| #define | SCU_CLK_CGATCLR2_DMA0_Pos (4UL) |
| |
| #define | SCU_CLK_CGATCLR2_DMA0_Msk (0x10UL) |
| |
| #define | SCU_CLK_CGATCLR2_DMA1_Pos (5UL) |
| |
| #define | SCU_CLK_CGATCLR2_DMA1_Msk (0x20UL) |
| |
| #define | SCU_CLK_CGATCLR2_FCE_Pos (6UL) |
| |
| #define | SCU_CLK_CGATCLR2_FCE_Msk (0x40UL) |
| |
| #define | SCU_CLK_CGATCLR2_USB_Pos (7UL) |
| |
| #define | SCU_CLK_CGATCLR2_USB_Msk (0x80UL) |
| |
| #define | SCU_CLK_CGATCLR2_ECAT0_Pos (10UL) |
| |
| #define | SCU_CLK_CGATCLR2_ECAT0_Msk (0x400UL) |
| |
| #define | SCU_CLK_CGATSTAT3_EBU_Pos (2UL) |
| |
| #define | SCU_CLK_CGATSTAT3_EBU_Msk (0x4UL) |
| |
| #define | SCU_CLK_CGATSET3_EBU_Pos (2UL) |
| |
| #define | SCU_CLK_CGATSET3_EBU_Msk (0x4UL) |
| |
| #define | SCU_CLK_CGATCLR3_EBU_Pos (2UL) |
| |
| #define | SCU_CLK_CGATCLR3_EBU_Msk (0x4UL) |
| |
| #define | SCU_OSC_OSCHPSTAT_X1D_Pos (0UL) |
| |
| #define | SCU_OSC_OSCHPSTAT_X1D_Msk (0x1UL) |
| |
| #define | SCU_OSC_OSCHPCTRL_X1DEN_Pos (0UL) |
| |
| #define | SCU_OSC_OSCHPCTRL_X1DEN_Msk (0x1UL) |
| |
| #define | SCU_OSC_OSCHPCTRL_SHBY_Pos (1UL) |
| |
| #define | SCU_OSC_OSCHPCTRL_SHBY_Msk (0x2UL) |
| |
| #define | SCU_OSC_OSCHPCTRL_GAINSEL_Pos (2UL) |
| |
| #define | SCU_OSC_OSCHPCTRL_GAINSEL_Msk (0xcUL) |
| |
| #define | SCU_OSC_OSCHPCTRL_MODE_Pos (4UL) |
| |
| #define | SCU_OSC_OSCHPCTRL_MODE_Msk (0x30UL) |
| |
| #define | SCU_OSC_OSCHPCTRL_OSCVAL_Pos (16UL) |
| |
| #define | SCU_OSC_OSCHPCTRL_OSCVAL_Msk (0xf0000UL) |
| |
| #define | SCU_OSC_CLKCALCONST_CALIBCONST_Pos (0UL) |
| |
| #define | SCU_OSC_CLKCALCONST_CALIBCONST_Msk (0xfUL) |
| |
| #define | SCU_PLL_PLLSTAT_VCOBYST_Pos (0UL) |
| |
| #define | SCU_PLL_PLLSTAT_VCOBYST_Msk (0x1UL) |
| |
| #define | SCU_PLL_PLLSTAT_PWDSTAT_Pos (1UL) |
| |
| #define | SCU_PLL_PLLSTAT_PWDSTAT_Msk (0x2UL) |
| |
| #define | SCU_PLL_PLLSTAT_VCOLOCK_Pos (2UL) |
| |
| #define | SCU_PLL_PLLSTAT_VCOLOCK_Msk (0x4UL) |
| |
| #define | SCU_PLL_PLLSTAT_K1RDY_Pos (4UL) |
| |
| #define | SCU_PLL_PLLSTAT_K1RDY_Msk (0x10UL) |
| |
| #define | SCU_PLL_PLLSTAT_K2RDY_Pos (5UL) |
| |
| #define | SCU_PLL_PLLSTAT_K2RDY_Msk (0x20UL) |
| |
| #define | SCU_PLL_PLLSTAT_BY_Pos (6UL) |
| |
| #define | SCU_PLL_PLLSTAT_BY_Msk (0x40UL) |
| |
| #define | SCU_PLL_PLLSTAT_PLLLV_Pos (7UL) |
| |
| #define | SCU_PLL_PLLSTAT_PLLLV_Msk (0x80UL) |
| |
| #define | SCU_PLL_PLLSTAT_PLLHV_Pos (8UL) |
| |
| #define | SCU_PLL_PLLSTAT_PLLHV_Msk (0x100UL) |
| |
| #define | SCU_PLL_PLLSTAT_PLLSP_Pos (9UL) |
| |
| #define | SCU_PLL_PLLSTAT_PLLSP_Msk (0x200UL) |
| |
| #define | SCU_PLL_PLLCON0_VCOBYP_Pos (0UL) |
| |
| #define | SCU_PLL_PLLCON0_VCOBYP_Msk (0x1UL) |
| |
| #define | SCU_PLL_PLLCON0_VCOPWD_Pos (1UL) |
| |
| #define | SCU_PLL_PLLCON0_VCOPWD_Msk (0x2UL) |
| |
| #define | SCU_PLL_PLLCON0_VCOTR_Pos (2UL) |
| |
| #define | SCU_PLL_PLLCON0_VCOTR_Msk (0x4UL) |
| |
| #define | SCU_PLL_PLLCON0_FINDIS_Pos (4UL) |
| |
| #define | SCU_PLL_PLLCON0_FINDIS_Msk (0x10UL) |
| |
| #define | SCU_PLL_PLLCON0_OSCDISCDIS_Pos (6UL) |
| |
| #define | SCU_PLL_PLLCON0_OSCDISCDIS_Msk (0x40UL) |
| |
| #define | SCU_PLL_PLLCON0_PLLPWD_Pos (16UL) |
| |
| #define | SCU_PLL_PLLCON0_PLLPWD_Msk (0x10000UL) |
| |
| #define | SCU_PLL_PLLCON0_OSCRES_Pos (17UL) |
| |
| #define | SCU_PLL_PLLCON0_OSCRES_Msk (0x20000UL) |
| |
| #define | SCU_PLL_PLLCON0_RESLD_Pos (18UL) |
| |
| #define | SCU_PLL_PLLCON0_RESLD_Msk (0x40000UL) |
| |
| #define | SCU_PLL_PLLCON0_AOTREN_Pos (19UL) |
| |
| #define | SCU_PLL_PLLCON0_AOTREN_Msk (0x80000UL) |
| |
| #define | SCU_PLL_PLLCON0_FOTR_Pos (20UL) |
| |
| #define | SCU_PLL_PLLCON0_FOTR_Msk (0x100000UL) |
| |
| #define | SCU_PLL_PLLCON1_K1DIV_Pos (0UL) |
| |
| #define | SCU_PLL_PLLCON1_K1DIV_Msk (0x7fUL) |
| |
| #define | SCU_PLL_PLLCON1_NDIV_Pos (8UL) |
| |
| #define | SCU_PLL_PLLCON1_NDIV_Msk (0x7f00UL) |
| |
| #define | SCU_PLL_PLLCON1_K2DIV_Pos (16UL) |
| |
| #define | SCU_PLL_PLLCON1_K2DIV_Msk (0x7f0000UL) |
| |
| #define | SCU_PLL_PLLCON1_PDIV_Pos (24UL) |
| |
| #define | SCU_PLL_PLLCON1_PDIV_Msk (0xf000000UL) |
| |
| #define | SCU_PLL_PLLCON2_PINSEL_Pos (0UL) |
| |
| #define | SCU_PLL_PLLCON2_PINSEL_Msk (0x1UL) |
| |
| #define | SCU_PLL_PLLCON2_K1INSEL_Pos (8UL) |
| |
| #define | SCU_PLL_PLLCON2_K1INSEL_Msk (0x100UL) |
| |
| #define | SCU_PLL_USBPLLSTAT_VCOBYST_Pos (0UL) |
| |
| #define | SCU_PLL_USBPLLSTAT_VCOBYST_Msk (0x1UL) |
| |
| #define | SCU_PLL_USBPLLSTAT_PWDSTAT_Pos (1UL) |
| |
| #define | SCU_PLL_USBPLLSTAT_PWDSTAT_Msk (0x2UL) |
| |
| #define | SCU_PLL_USBPLLSTAT_VCOLOCK_Pos (2UL) |
| |
| #define | SCU_PLL_USBPLLSTAT_VCOLOCK_Msk (0x4UL) |
| |
| #define | SCU_PLL_USBPLLSTAT_BY_Pos (6UL) |
| |
| #define | SCU_PLL_USBPLLSTAT_BY_Msk (0x40UL) |
| |
| #define | SCU_PLL_USBPLLSTAT_VCOLOCKED_Pos (7UL) |
| |
| #define | SCU_PLL_USBPLLSTAT_VCOLOCKED_Msk (0x80UL) |
| |
| #define | SCU_PLL_USBPLLCON_VCOBYP_Pos (0UL) |
| |
| #define | SCU_PLL_USBPLLCON_VCOBYP_Msk (0x1UL) |
| |
| #define | SCU_PLL_USBPLLCON_VCOPWD_Pos (1UL) |
| |
| #define | SCU_PLL_USBPLLCON_VCOPWD_Msk (0x2UL) |
| |
| #define | SCU_PLL_USBPLLCON_VCOTR_Pos (2UL) |
| |
| #define | SCU_PLL_USBPLLCON_VCOTR_Msk (0x4UL) |
| |
| #define | SCU_PLL_USBPLLCON_FINDIS_Pos (4UL) |
| |
| #define | SCU_PLL_USBPLLCON_FINDIS_Msk (0x10UL) |
| |
| #define | SCU_PLL_USBPLLCON_OSCDISCDIS_Pos (6UL) |
| |
| #define | SCU_PLL_USBPLLCON_OSCDISCDIS_Msk (0x40UL) |
| |
| #define | SCU_PLL_USBPLLCON_NDIV_Pos (8UL) |
| |
| #define | SCU_PLL_USBPLLCON_NDIV_Msk (0x7f00UL) |
| |
| #define | SCU_PLL_USBPLLCON_PLLPWD_Pos (16UL) |
| |
| #define | SCU_PLL_USBPLLCON_PLLPWD_Msk (0x10000UL) |
| |
| #define | SCU_PLL_USBPLLCON_RESLD_Pos (18UL) |
| |
| #define | SCU_PLL_USBPLLCON_RESLD_Msk (0x40000UL) |
| |
| #define | SCU_PLL_USBPLLCON_PDIV_Pos (24UL) |
| |
| #define | SCU_PLL_USBPLLCON_PDIV_Msk (0xf000000UL) |
| |
| #define | SCU_PLL_CLKMXSTAT_SYSCLKMUX_Pos (0UL) |
| |
| #define | SCU_PLL_CLKMXSTAT_SYSCLKMUX_Msk (0x3UL) |
| |
| #define | SCU_GENERAL_ID_MOD_REV_Pos (0UL) |
| |
| #define | SCU_GENERAL_ID_MOD_REV_Msk (0xffUL) |
| |
| #define | SCU_GENERAL_ID_MOD_TYPE_Pos (8UL) |
| |
| #define | SCU_GENERAL_ID_MOD_TYPE_Msk (0xff00UL) |
| |
| #define | SCU_GENERAL_ID_MOD_NUMBER_Pos (16UL) |
| |
| #define | SCU_GENERAL_ID_MOD_NUMBER_Msk (0xffff0000UL) |
| |
| #define | SCU_GENERAL_IDCHIP_IDCHIP_Pos (0UL) |
| |
| #define | SCU_GENERAL_IDCHIP_IDCHIP_Msk (0xffffffffUL) |
| |
| #define | SCU_GENERAL_IDMANUF_DEPT_Pos (0UL) |
| |
| #define | SCU_GENERAL_IDMANUF_DEPT_Msk (0x1fUL) |
| |
| #define | SCU_GENERAL_IDMANUF_MANUF_Pos (5UL) |
| |
| #define | SCU_GENERAL_IDMANUF_MANUF_Msk (0xffe0UL) |
| |
| #define | SCU_GENERAL_STCON_HWCON_Pos (0UL) |
| |
| #define | SCU_GENERAL_STCON_HWCON_Msk (0x3UL) |
| |
| #define | SCU_GENERAL_STCON_SWCON_Pos (8UL) |
| |
| #define | SCU_GENERAL_STCON_SWCON_Msk (0xf00UL) |
| |
| #define | SCU_GENERAL_GPR_DAT_Pos (0UL) |
| |
| #define | SCU_GENERAL_GPR_DAT_Msk (0xffffffffUL) |
| |
| #define | SCU_GENERAL_CCUCON_GSC40_Pos (0UL) |
| |
| #define | SCU_GENERAL_CCUCON_GSC40_Msk (0x1UL) |
| |
| #define | SCU_GENERAL_CCUCON_GSC41_Pos (1UL) |
| |
| #define | SCU_GENERAL_CCUCON_GSC41_Msk (0x2UL) |
| |
| #define | SCU_GENERAL_CCUCON_GSC42_Pos (2UL) |
| |
| #define | SCU_GENERAL_CCUCON_GSC42_Msk (0x4UL) |
| |
| #define | SCU_GENERAL_CCUCON_GSC43_Pos (3UL) |
| |
| #define | SCU_GENERAL_CCUCON_GSC43_Msk (0x8UL) |
| |
| #define | SCU_GENERAL_CCUCON_GSC80_Pos (8UL) |
| |
| #define | SCU_GENERAL_CCUCON_GSC80_Msk (0x100UL) |
| |
| #define | SCU_GENERAL_CCUCON_GSC81_Pos (9UL) |
| |
| #define | SCU_GENERAL_CCUCON_GSC81_Msk (0x200UL) |
| |
| #define | SCU_GENERAL_DTSCON_PWD_Pos (0UL) |
| |
| #define | SCU_GENERAL_DTSCON_PWD_Msk (0x1UL) |
| |
| #define | SCU_GENERAL_DTSCON_START_Pos (1UL) |
| |
| #define | SCU_GENERAL_DTSCON_START_Msk (0x2UL) |
| |
| #define | SCU_GENERAL_DTSCON_OFFSET_Pos (4UL) |
| |
| #define | SCU_GENERAL_DTSCON_OFFSET_Msk (0x7f0UL) |
| |
| #define | SCU_GENERAL_DTSCON_GAIN_Pos (11UL) |
| |
| #define | SCU_GENERAL_DTSCON_GAIN_Msk (0x1f800UL) |
| |
| #define | SCU_GENERAL_DTSCON_REFTRIM_Pos (17UL) |
| |
| #define | SCU_GENERAL_DTSCON_REFTRIM_Msk (0xe0000UL) |
| |
| #define | SCU_GENERAL_DTSCON_BGTRIM_Pos (20UL) |
| |
| #define | SCU_GENERAL_DTSCON_BGTRIM_Msk (0xf00000UL) |
| |
| #define | SCU_GENERAL_DTSSTAT_RESULT_Pos (0UL) |
| |
| #define | SCU_GENERAL_DTSSTAT_RESULT_Msk (0x3ffUL) |
| |
| #define | SCU_GENERAL_DTSSTAT_RDY_Pos (14UL) |
| |
| #define | SCU_GENERAL_DTSSTAT_RDY_Msk (0x4000UL) |
| |
| #define | SCU_GENERAL_DTSSTAT_BUSY_Pos (15UL) |
| |
| #define | SCU_GENERAL_DTSSTAT_BUSY_Msk (0x8000UL) |
| |
| #define | SCU_GENERAL_SDMMCDEL_TAPEN_Pos (0UL) |
| |
| #define | SCU_GENERAL_SDMMCDEL_TAPEN_Msk (0x1UL) |
| |
| #define | SCU_GENERAL_SDMMCDEL_TAPDEL_Pos (4UL) |
| |
| #define | SCU_GENERAL_SDMMCDEL_TAPDEL_Msk (0xf0UL) |
| |
| #define | SCU_GENERAL_GORCEN_ENORC6_Pos (6UL) |
| |
| #define | SCU_GENERAL_GORCEN_ENORC6_Msk (0x40UL) |
| |
| #define | SCU_GENERAL_GORCEN_ENORC7_Pos (7UL) |
| |
| #define | SCU_GENERAL_GORCEN_ENORC7_Msk (0x80UL) |
| |
| #define | SCU_GENERAL_MIRRSTS_HDCLR_Pos (1UL) |
| |
| #define | SCU_GENERAL_MIRRSTS_HDCLR_Msk (0x2UL) |
| |
| #define | SCU_GENERAL_MIRRSTS_HDSET_Pos (2UL) |
| |
| #define | SCU_GENERAL_MIRRSTS_HDSET_Msk (0x4UL) |
| |
| #define | SCU_GENERAL_MIRRSTS_HDCR_Pos (3UL) |
| |
| #define | SCU_GENERAL_MIRRSTS_HDCR_Msk (0x8UL) |
| |
| #define | SCU_GENERAL_MIRRSTS_OSCSICTRL_Pos (5UL) |
| |
| #define | SCU_GENERAL_MIRRSTS_OSCSICTRL_Msk (0x20UL) |
| |
| #define | SCU_GENERAL_MIRRSTS_OSCULCTRL_Pos (7UL) |
| |
| #define | SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk (0x80UL) |
| |
| #define | SCU_GENERAL_MIRRSTS_RTC_CTR_Pos (8UL) |
| |
| #define | SCU_GENERAL_MIRRSTS_RTC_CTR_Msk (0x100UL) |
| |
| #define | SCU_GENERAL_MIRRSTS_RTC_ATIM0_Pos (9UL) |
| |
| #define | SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk (0x200UL) |
| |
| #define | SCU_GENERAL_MIRRSTS_RTC_ATIM1_Pos (10UL) |
| |
| #define | SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk (0x400UL) |
| |
| #define | SCU_GENERAL_MIRRSTS_RTC_TIM0_Pos (11UL) |
| |
| #define | SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk (0x800UL) |
| |
| #define | SCU_GENERAL_MIRRSTS_RTC_TIM1_Pos (12UL) |
| |
| #define | SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk (0x1000UL) |
| |
| #define | SCU_GENERAL_MIRRSTS_RMX_Pos (13UL) |
| |
| #define | SCU_GENERAL_MIRRSTS_RMX_Msk (0x2000UL) |
| |
| #define | SCU_GENERAL_MIRRSTS_RTC_MSKSR_Pos (14UL) |
| |
| #define | SCU_GENERAL_MIRRSTS_RTC_MSKSR_Msk (0x4000UL) |
| |
| #define | SCU_GENERAL_MIRRSTS_RTC_CLRSR_Pos (15UL) |
| |
| #define | SCU_GENERAL_MIRRSTS_RTC_CLRSR_Msk (0x8000UL) |
| |
| #define | SCU_GENERAL_RMACR_RDWR_Pos (0UL) |
| |
| #define | SCU_GENERAL_RMACR_RDWR_Msk (0x1UL) |
| |
| #define | SCU_GENERAL_RMACR_ADDR_Pos (16UL) |
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| #define | SCU_GENERAL_RMACR_ADDR_Msk (0xf0000UL) |
| |
| #define | SCU_GENERAL_RMDATA_DATA_Pos (0UL) |
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| #define | SCU_GENERAL_RMDATA_DATA_Msk (0xffffffffUL) |
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| #define | SCU_INTERRUPT_SRSTAT_PRWARN_Pos (0UL) |
| |
| #define | SCU_INTERRUPT_SRSTAT_PRWARN_Msk (0x1UL) |
| |
| #define | SCU_INTERRUPT_SRSTAT_PI_Pos (1UL) |
| |
| #define | SCU_INTERRUPT_SRSTAT_PI_Msk (0x2UL) |
| |
| #define | SCU_INTERRUPT_SRSTAT_AI_Pos (2UL) |
| |
| #define | SCU_INTERRUPT_SRSTAT_AI_Msk (0x4UL) |
| |
| #define | SCU_INTERRUPT_SRSTAT_DLROVR_Pos (3UL) |
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| #define | SCU_INTERRUPT_SRSTAT_DLROVR_Msk (0x8UL) |
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| #define | SCU_INTERRUPT_SRSTAT_HDCLR_Pos (17UL) |
| |
| #define | SCU_INTERRUPT_SRSTAT_HDCLR_Msk (0x20000UL) |
| |
| #define | SCU_INTERRUPT_SRSTAT_HDSET_Pos (18UL) |
| |
| #define | SCU_INTERRUPT_SRSTAT_HDSET_Msk (0x40000UL) |
| |
| #define | SCU_INTERRUPT_SRSTAT_HDCR_Pos (19UL) |
| |
| #define | SCU_INTERRUPT_SRSTAT_HDCR_Msk (0x80000UL) |
| |
| #define | SCU_INTERRUPT_SRSTAT_OSCSICTRL_Pos (21UL) |
| |
| #define | SCU_INTERRUPT_SRSTAT_OSCSICTRL_Msk (0x200000UL) |
| |
| #define | SCU_INTERRUPT_SRSTAT_OSCULCTRL_Pos (23UL) |
| |
| #define | SCU_INTERRUPT_SRSTAT_OSCULCTRL_Msk (0x800000UL) |
| |
| #define | SCU_INTERRUPT_SRSTAT_RTC_CTR_Pos (24UL) |
| |
| #define | SCU_INTERRUPT_SRSTAT_RTC_CTR_Msk (0x1000000UL) |
| |
| #define | SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Pos (25UL) |
| |
| #define | SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Msk (0x2000000UL) |
| |
| #define | SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Pos (26UL) |
| |
| #define | SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Msk (0x4000000UL) |
| |
| #define | SCU_INTERRUPT_SRSTAT_RTC_TIM0_Pos (27UL) |
| |
| #define | SCU_INTERRUPT_SRSTAT_RTC_TIM0_Msk (0x8000000UL) |
| |
| #define | SCU_INTERRUPT_SRSTAT_RTC_TIM1_Pos (28UL) |
| |
| #define | SCU_INTERRUPT_SRSTAT_RTC_TIM1_Msk (0x10000000UL) |
| |
| #define | SCU_INTERRUPT_SRSTAT_RMX_Pos (29UL) |
| |
| #define | SCU_INTERRUPT_SRSTAT_RMX_Msk (0x20000000UL) |
| |
| #define | SCU_INTERRUPT_SRRAW_PRWARN_Pos (0UL) |
| |
| #define | SCU_INTERRUPT_SRRAW_PRWARN_Msk (0x1UL) |
| |
| #define | SCU_INTERRUPT_SRRAW_PI_Pos (1UL) |
| |
| #define | SCU_INTERRUPT_SRRAW_PI_Msk (0x2UL) |
| |
| #define | SCU_INTERRUPT_SRRAW_AI_Pos (2UL) |
| |
| #define | SCU_INTERRUPT_SRRAW_AI_Msk (0x4UL) |
| |
| #define | SCU_INTERRUPT_SRRAW_DLROVR_Pos (3UL) |
| |
| #define | SCU_INTERRUPT_SRRAW_DLROVR_Msk (0x8UL) |
| |
| #define | SCU_INTERRUPT_SRRAW_HDCLR_Pos (17UL) |
| |
| #define | SCU_INTERRUPT_SRRAW_HDCLR_Msk (0x20000UL) |
| |
| #define | SCU_INTERRUPT_SRRAW_HDSET_Pos (18UL) |
| |
| #define | SCU_INTERRUPT_SRRAW_HDSET_Msk (0x40000UL) |
| |
| #define | SCU_INTERRUPT_SRRAW_HDCR_Pos (19UL) |
| |
| #define | SCU_INTERRUPT_SRRAW_HDCR_Msk (0x80000UL) |
| |
| #define | SCU_INTERRUPT_SRRAW_OSCSICTRL_Pos (21UL) |
| |
| #define | SCU_INTERRUPT_SRRAW_OSCSICTRL_Msk (0x200000UL) |
| |
| #define | SCU_INTERRUPT_SRRAW_OSCULCTRL_Pos (23UL) |
| |
| #define | SCU_INTERRUPT_SRRAW_OSCULCTRL_Msk (0x800000UL) |
| |
| #define | SCU_INTERRUPT_SRRAW_RTC_CTR_Pos (24UL) |
| |
| #define | SCU_INTERRUPT_SRRAW_RTC_CTR_Msk (0x1000000UL) |
| |
| #define | SCU_INTERRUPT_SRRAW_RTC_ATIM0_Pos (25UL) |
| |
| #define | SCU_INTERRUPT_SRRAW_RTC_ATIM0_Msk (0x2000000UL) |
| |
| #define | SCU_INTERRUPT_SRRAW_RTC_ATIM1_Pos (26UL) |
| |
| #define | SCU_INTERRUPT_SRRAW_RTC_ATIM1_Msk (0x4000000UL) |
| |
| #define | SCU_INTERRUPT_SRRAW_RTC_TIM0_Pos (27UL) |
| |
| #define | SCU_INTERRUPT_SRRAW_RTC_TIM0_Msk (0x8000000UL) |
| |
| #define | SCU_INTERRUPT_SRRAW_RTC_TIM1_Pos (28UL) |
| |
| #define | SCU_INTERRUPT_SRRAW_RTC_TIM1_Msk (0x10000000UL) |
| |
| #define | SCU_INTERRUPT_SRRAW_RMX_Pos (29UL) |
| |
| #define | SCU_INTERRUPT_SRRAW_RMX_Msk (0x20000000UL) |
| |
| #define | SCU_INTERRUPT_SRMSK_PRWARN_Pos (0UL) |
| |
| #define | SCU_INTERRUPT_SRMSK_PRWARN_Msk (0x1UL) |
| |
| #define | SCU_INTERRUPT_SRMSK_PI_Pos (1UL) |
| |
| #define | SCU_INTERRUPT_SRMSK_PI_Msk (0x2UL) |
| |
| #define | SCU_INTERRUPT_SRMSK_AI_Pos (2UL) |
| |
| #define | SCU_INTERRUPT_SRMSK_AI_Msk (0x4UL) |
| |
| #define | SCU_INTERRUPT_SRMSK_DLROVR_Pos (3UL) |
| |
| #define | SCU_INTERRUPT_SRMSK_DLROVR_Msk (0x8UL) |
| |
| #define | SCU_INTERRUPT_SRMSK_HDCLR_Pos (17UL) |
| |
| #define | SCU_INTERRUPT_SRMSK_HDCLR_Msk (0x20000UL) |
| |
| #define | SCU_INTERRUPT_SRMSK_HDSET_Pos (18UL) |
| |
| #define | SCU_INTERRUPT_SRMSK_HDSET_Msk (0x40000UL) |
| |
| #define | SCU_INTERRUPT_SRMSK_HDCR_Pos (19UL) |
| |
| #define | SCU_INTERRUPT_SRMSK_HDCR_Msk (0x80000UL) |
| |
| #define | SCU_INTERRUPT_SRMSK_OSCSICTRL_Pos (21UL) |
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| #define | SCU_INTERRUPT_SRMSK_OSCSICTRL_Msk (0x200000UL) |
| |
| #define | SCU_INTERRUPT_SRMSK_OSCULCTRL_Pos (23UL) |
| |
| #define | SCU_INTERRUPT_SRMSK_OSCULCTRL_Msk (0x800000UL) |
| |
| #define | SCU_INTERRUPT_SRMSK_RTC_CTR_Pos (24UL) |
| |
| #define | SCU_INTERRUPT_SRMSK_RTC_CTR_Msk (0x1000000UL) |
| |
| #define | SCU_INTERRUPT_SRMSK_RTC_ATIM0_Pos (25UL) |
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| #define | SCU_INTERRUPT_SRMSK_RTC_ATIM0_Msk (0x2000000UL) |
| |
| #define | SCU_INTERRUPT_SRMSK_RTC_ATIM1_Pos (26UL) |
| |
| #define | SCU_INTERRUPT_SRMSK_RTC_ATIM1_Msk (0x4000000UL) |
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| #define | SCU_INTERRUPT_SRMSK_RTC_TIM0_Pos (27UL) |
| |
| #define | SCU_INTERRUPT_SRMSK_RTC_TIM0_Msk (0x8000000UL) |
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| #define | SCU_INTERRUPT_SRMSK_RTC_TIM1_Pos (28UL) |
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| #define | SCU_INTERRUPT_SRMSK_RTC_TIM1_Msk (0x10000000UL) |
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| #define | SCU_INTERRUPT_SRMSK_RMX_Pos (29UL) |
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| #define | SCU_INTERRUPT_SRMSK_RMX_Msk (0x20000000UL) |
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| #define | SCU_INTERRUPT_SRCLR_PRWARN_Pos (0UL) |
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| #define | SCU_INTERRUPT_SRCLR_PRWARN_Msk (0x1UL) |
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| #define | SCU_INTERRUPT_SRCLR_PI_Pos (1UL) |
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| #define | SCU_INTERRUPT_SRCLR_PI_Msk (0x2UL) |
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| #define | SCU_INTERRUPT_SRCLR_AI_Pos (2UL) |
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| #define | SCU_INTERRUPT_SRCLR_AI_Msk (0x4UL) |
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| #define | SCU_INTERRUPT_SRCLR_DLROVR_Pos (3UL) |
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| #define | SCU_INTERRUPT_SRCLR_DLROVR_Msk (0x8UL) |
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| #define | SCU_INTERRUPT_SRCLR_HDCLR_Pos (17UL) |
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| #define | SCU_INTERRUPT_SRCLR_HDCLR_Msk (0x20000UL) |
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| #define | SCU_INTERRUPT_SRCLR_HDSET_Pos (18UL) |
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| #define | SCU_INTERRUPT_SRCLR_HDSET_Msk (0x40000UL) |
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| #define | SCU_INTERRUPT_SRCLR_HDCR_Pos (19UL) |
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| #define | SCU_INTERRUPT_SRCLR_HDCR_Msk (0x80000UL) |
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| #define | SCU_INTERRUPT_SRCLR_OSCSICTRL_Pos (21UL) |
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| #define | SCU_INTERRUPT_SRCLR_OSCSICTRL_Msk (0x200000UL) |
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| #define | SCU_INTERRUPT_SRCLR_OSCULCTRL_Pos (23UL) |
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| #define | SCU_INTERRUPT_SRCLR_OSCULCTRL_Msk (0x800000UL) |
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| #define | SCU_INTERRUPT_SRCLR_RTC_CTR_Pos (24UL) |
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| #define | SCU_INTERRUPT_SRCLR_RTC_CTR_Msk (0x1000000UL) |
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| #define | SCU_INTERRUPT_SRCLR_RTC_ATIM0_Pos (25UL) |
| |
| #define | SCU_INTERRUPT_SRCLR_RTC_ATIM0_Msk (0x2000000UL) |
| |
| #define | SCU_INTERRUPT_SRCLR_RTC_ATIM1_Pos (26UL) |
| |
| #define | SCU_INTERRUPT_SRCLR_RTC_ATIM1_Msk (0x4000000UL) |
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| #define | SCU_INTERRUPT_SRCLR_RTC_TIM0_Pos (27UL) |
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| #define | SCU_INTERRUPT_SRCLR_RTC_TIM0_Msk (0x8000000UL) |
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| #define | SCU_INTERRUPT_SRCLR_RTC_TIM1_Pos (28UL) |
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| #define | SCU_INTERRUPT_SRCLR_RTC_TIM1_Msk (0x10000000UL) |
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| #define | SCU_INTERRUPT_SRCLR_RMX_Pos (29UL) |
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| #define | SCU_INTERRUPT_SRCLR_RMX_Msk (0x20000000UL) |
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| #define | SCU_INTERRUPT_SRSET_PRWARN_Pos (0UL) |
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| #define | SCU_INTERRUPT_SRSET_PRWARN_Msk (0x1UL) |
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| #define | SCU_INTERRUPT_SRSET_PI_Pos (1UL) |
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| #define | SCU_INTERRUPT_SRSET_PI_Msk (0x2UL) |
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| #define | SCU_INTERRUPT_SRSET_AI_Pos (2UL) |
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| #define | SCU_INTERRUPT_SRSET_AI_Msk (0x4UL) |
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| #define | SCU_INTERRUPT_SRSET_DLROVR_Pos (3UL) |
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| #define | SCU_INTERRUPT_SRSET_DLROVR_Msk (0x8UL) |
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| #define | SCU_INTERRUPT_SRSET_HDCRCLR_Pos (17UL) |
| |
| #define | SCU_INTERRUPT_SRSET_HDCRCLR_Msk (0x20000UL) |
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| #define | SCU_INTERRUPT_SRSET_HDCRSET_Pos (18UL) |
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| #define | SCU_INTERRUPT_SRSET_HDCRSET_Msk (0x40000UL) |
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| #define | SCU_INTERRUPT_SRSET_HDCR_Pos (19UL) |
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| #define | SCU_INTERRUPT_SRSET_HDCR_Msk (0x80000UL) |
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| #define | SCU_INTERRUPT_SRSET_OSCSICTRL_Pos (21UL) |
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| #define | SCU_INTERRUPT_SRSET_OSCSICTRL_Msk (0x200000UL) |
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| #define | SCU_INTERRUPT_SRSET_OSCULCTRL_Pos (23UL) |
| |
| #define | SCU_INTERRUPT_SRSET_OSCULCTRL_Msk (0x800000UL) |
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| #define | SCU_INTERRUPT_SRSET_RTC_CTR_Pos (24UL) |
| |
| #define | SCU_INTERRUPT_SRSET_RTC_CTR_Msk (0x1000000UL) |
| |
| #define | SCU_INTERRUPT_SRSET_RTC_ATIM0_Pos (25UL) |
| |
| #define | SCU_INTERRUPT_SRSET_RTC_ATIM0_Msk (0x2000000UL) |
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| #define | SCU_INTERRUPT_SRSET_RTC_ATIM1_Pos (26UL) |
| |
| #define | SCU_INTERRUPT_SRSET_RTC_ATIM1_Msk (0x4000000UL) |
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| #define | SCU_INTERRUPT_SRSET_RTC_TIM0_Pos (27UL) |
| |
| #define | SCU_INTERRUPT_SRSET_RTC_TIM0_Msk (0x8000000UL) |
| |
| #define | SCU_INTERRUPT_SRSET_RTC_TIM1_Pos (28UL) |
| |
| #define | SCU_INTERRUPT_SRSET_RTC_TIM1_Msk (0x10000000UL) |
| |
| #define | SCU_INTERRUPT_SRSET_RMX_Pos (29UL) |
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| #define | SCU_INTERRUPT_SRSET_RMX_Msk (0x20000000UL) |
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| #define | SCU_INTERRUPT_NMIREQEN_PRWARN_Pos (0UL) |
| |
| #define | SCU_INTERRUPT_NMIREQEN_PRWARN_Msk (0x1UL) |
| |
| #define | SCU_INTERRUPT_NMIREQEN_PI_Pos (1UL) |
| |
| #define | SCU_INTERRUPT_NMIREQEN_PI_Msk (0x2UL) |
| |
| #define | SCU_INTERRUPT_NMIREQEN_AI_Pos (2UL) |
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| #define | SCU_INTERRUPT_NMIREQEN_AI_Msk (0x4UL) |
| |
| #define | SCU_INTERRUPT_NMIREQEN_ERU00_Pos (16UL) |
| |
| #define | SCU_INTERRUPT_NMIREQEN_ERU00_Msk (0x10000UL) |
| |
| #define | SCU_INTERRUPT_NMIREQEN_ERU01_Pos (17UL) |
| |
| #define | SCU_INTERRUPT_NMIREQEN_ERU01_Msk (0x20000UL) |
| |
| #define | SCU_INTERRUPT_NMIREQEN_ERU02_Pos (18UL) |
| |
| #define | SCU_INTERRUPT_NMIREQEN_ERU02_Msk (0x40000UL) |
| |
| #define | SCU_INTERRUPT_NMIREQEN_ERU03_Pos (19UL) |
| |
| #define | SCU_INTERRUPT_NMIREQEN_ERU03_Msk (0x80000UL) |
| |
| #define | SCU_PARITY_PEEN_PEENPS_Pos (0UL) |
| |
| #define | SCU_PARITY_PEEN_PEENPS_Msk (0x1UL) |
| |
| #define | SCU_PARITY_PEEN_PEENDS1_Pos (1UL) |
| |
| #define | SCU_PARITY_PEEN_PEENDS1_Msk (0x2UL) |
| |
| #define | SCU_PARITY_PEEN_PEENDS2_Pos (2UL) |
| |
| #define | SCU_PARITY_PEEN_PEENDS2_Msk (0x4UL) |
| |
| #define | SCU_PARITY_PEEN_PEENU0_Pos (8UL) |
| |
| #define | SCU_PARITY_PEEN_PEENU0_Msk (0x100UL) |
| |
| #define | SCU_PARITY_PEEN_PEENU1_Pos (9UL) |
| |
| #define | SCU_PARITY_PEEN_PEENU1_Msk (0x200UL) |
| |
| #define | SCU_PARITY_PEEN_PEENU2_Pos (10UL) |
| |
| #define | SCU_PARITY_PEEN_PEENU2_Msk (0x400UL) |
| |
| #define | SCU_PARITY_PEEN_PEENMC_Pos (12UL) |
| |
| #define | SCU_PARITY_PEEN_PEENMC_Msk (0x1000UL) |
| |
| #define | SCU_PARITY_PEEN_PEENPPRF_Pos (13UL) |
| |
| #define | SCU_PARITY_PEEN_PEENPPRF_Msk (0x2000UL) |
| |
| #define | SCU_PARITY_PEEN_PEENUSB_Pos (16UL) |
| |
| #define | SCU_PARITY_PEEN_PEENUSB_Msk (0x10000UL) |
| |
| #define | SCU_PARITY_PEEN_PEENETH0TX_Pos (17UL) |
| |
| #define | SCU_PARITY_PEEN_PEENETH0TX_Msk (0x20000UL) |
| |
| #define | SCU_PARITY_PEEN_PEENETH0RX_Pos (18UL) |
| |
| #define | SCU_PARITY_PEEN_PEENETH0RX_Msk (0x40000UL) |
| |
| #define | SCU_PARITY_PEEN_PEENSD0_Pos (19UL) |
| |
| #define | SCU_PARITY_PEEN_PEENSD0_Msk (0x80000UL) |
| |
| #define | SCU_PARITY_PEEN_PEENSD1_Pos (20UL) |
| |
| #define | SCU_PARITY_PEEN_PEENSD1_Msk (0x100000UL) |
| |
| #define | SCU_PARITY_PEEN_PEENECAT0_Pos (24UL) |
| |
| #define | SCU_PARITY_PEEN_PEENECAT0_Msk (0x1000000UL) |
| |
| #define | SCU_PARITY_MCHKCON_SELPS_Pos (0UL) |
| |
| #define | SCU_PARITY_MCHKCON_SELPS_Msk (0x1UL) |
| |
| #define | SCU_PARITY_MCHKCON_SELDS1_Pos (1UL) |
| |
| #define | SCU_PARITY_MCHKCON_SELDS1_Msk (0x2UL) |
| |
| #define | SCU_PARITY_MCHKCON_SELDS2_Pos (2UL) |
| |
| #define | SCU_PARITY_MCHKCON_SELDS2_Msk (0x4UL) |
| |
| #define | SCU_PARITY_MCHKCON_USIC0DRA_Pos (8UL) |
| |
| #define | SCU_PARITY_MCHKCON_USIC0DRA_Msk (0x100UL) |
| |
| #define | SCU_PARITY_MCHKCON_USIC1DRA_Pos (9UL) |
| |
| #define | SCU_PARITY_MCHKCON_USIC1DRA_Msk (0x200UL) |
| |
| #define | SCU_PARITY_MCHKCON_USIC2DRA_Pos (10UL) |
| |
| #define | SCU_PARITY_MCHKCON_USIC2DRA_Msk (0x400UL) |
| |
| #define | SCU_PARITY_MCHKCON_MCANDRA_Pos (12UL) |
| |
| #define | SCU_PARITY_MCHKCON_MCANDRA_Msk (0x1000UL) |
| |
| #define | SCU_PARITY_MCHKCON_PPRFDRA_Pos (13UL) |
| |
| #define | SCU_PARITY_MCHKCON_PPRFDRA_Msk (0x2000UL) |
| |
| #define | SCU_PARITY_MCHKCON_SELUSB_Pos (16UL) |
| |
| #define | SCU_PARITY_MCHKCON_SELUSB_Msk (0x10000UL) |
| |
| #define | SCU_PARITY_MCHKCON_SELETH0TX_Pos (17UL) |
| |
| #define | SCU_PARITY_MCHKCON_SELETH0TX_Msk (0x20000UL) |
| |
| #define | SCU_PARITY_MCHKCON_SELETH0RX_Pos (18UL) |
| |
| #define | SCU_PARITY_MCHKCON_SELETH0RX_Msk (0x40000UL) |
| |
| #define | SCU_PARITY_MCHKCON_SELSD0_Pos (19UL) |
| |
| #define | SCU_PARITY_MCHKCON_SELSD0_Msk (0x80000UL) |
| |
| #define | SCU_PARITY_MCHKCON_SELSD1_Pos (20UL) |
| |
| #define | SCU_PARITY_MCHKCON_SELSD1_Msk (0x100000UL) |
| |
| #define | SCU_PARITY_MCHKCON_SELECAT0_Pos (24UL) |
| |
| #define | SCU_PARITY_MCHKCON_SELECAT0_Msk (0x1000000UL) |
| |
| #define | SCU_PARITY_PETE_PETEPS_Pos (0UL) |
| |
| #define | SCU_PARITY_PETE_PETEPS_Msk (0x1UL) |
| |
| #define | SCU_PARITY_PETE_PETEDS1_Pos (1UL) |
| |
| #define | SCU_PARITY_PETE_PETEDS1_Msk (0x2UL) |
| |
| #define | SCU_PARITY_PETE_PETEDS2_Pos (2UL) |
| |
| #define | SCU_PARITY_PETE_PETEDS2_Msk (0x4UL) |
| |
| #define | SCU_PARITY_PETE_PETEU0_Pos (8UL) |
| |
| #define | SCU_PARITY_PETE_PETEU0_Msk (0x100UL) |
| |
| #define | SCU_PARITY_PETE_PETEU1_Pos (9UL) |
| |
| #define | SCU_PARITY_PETE_PETEU1_Msk (0x200UL) |
| |
| #define | SCU_PARITY_PETE_PETEU2_Pos (10UL) |
| |
| #define | SCU_PARITY_PETE_PETEU2_Msk (0x400UL) |
| |
| #define | SCU_PARITY_PETE_PETEMC_Pos (12UL) |
| |
| #define | SCU_PARITY_PETE_PETEMC_Msk (0x1000UL) |
| |
| #define | SCU_PARITY_PETE_PETEPPRF_Pos (13UL) |
| |
| #define | SCU_PARITY_PETE_PETEPPRF_Msk (0x2000UL) |
| |
| #define | SCU_PARITY_PETE_PETEUSB_Pos (16UL) |
| |
| #define | SCU_PARITY_PETE_PETEUSB_Msk (0x10000UL) |
| |
| #define | SCU_PARITY_PETE_PETEETH0TX_Pos (17UL) |
| |
| #define | SCU_PARITY_PETE_PETEETH0TX_Msk (0x20000UL) |
| |
| #define | SCU_PARITY_PETE_PETEETH0RX_Pos (18UL) |
| |
| #define | SCU_PARITY_PETE_PETEETH0RX_Msk (0x40000UL) |
| |
| #define | SCU_PARITY_PETE_PETESD0_Pos (19UL) |
| |
| #define | SCU_PARITY_PETE_PETESD0_Msk (0x80000UL) |
| |
| #define | SCU_PARITY_PETE_PETESD1_Pos (20UL) |
| |
| #define | SCU_PARITY_PETE_PETESD1_Msk (0x100000UL) |
| |
| #define | SCU_PARITY_PETE_PETEECAT0_Pos (24UL) |
| |
| #define | SCU_PARITY_PETE_PETEECAT0_Msk (0x1000000UL) |
| |
| #define | SCU_PARITY_PERSTEN_RSEN_Pos (0UL) |
| |
| #define | SCU_PARITY_PERSTEN_RSEN_Msk (0x1UL) |
| |
| #define | SCU_PARITY_PEFLAG_PEFPS_Pos (0UL) |
| |
| #define | SCU_PARITY_PEFLAG_PEFPS_Msk (0x1UL) |
| |
| #define | SCU_PARITY_PEFLAG_PEFDS1_Pos (1UL) |
| |
| #define | SCU_PARITY_PEFLAG_PEFDS1_Msk (0x2UL) |
| |
| #define | SCU_PARITY_PEFLAG_PEFDS2_Pos (2UL) |
| |
| #define | SCU_PARITY_PEFLAG_PEFDS2_Msk (0x4UL) |
| |
| #define | SCU_PARITY_PEFLAG_PEFU0_Pos (8UL) |
| |
| #define | SCU_PARITY_PEFLAG_PEFU0_Msk (0x100UL) |
| |
| #define | SCU_PARITY_PEFLAG_PEFU1_Pos (9UL) |
| |
| #define | SCU_PARITY_PEFLAG_PEFU1_Msk (0x200UL) |
| |
| #define | SCU_PARITY_PEFLAG_PEFU2_Pos (10UL) |
| |
| #define | SCU_PARITY_PEFLAG_PEFU2_Msk (0x400UL) |
| |
| #define | SCU_PARITY_PEFLAG_PEFMC_Pos (12UL) |
| |
| #define | SCU_PARITY_PEFLAG_PEFMC_Msk (0x1000UL) |
| |
| #define | SCU_PARITY_PEFLAG_PEFPPRF_Pos (13UL) |
| |
| #define | SCU_PARITY_PEFLAG_PEFPPRF_Msk (0x2000UL) |
| |
| #define | SCU_PARITY_PEFLAG_PEUSB_Pos (16UL) |
| |
| #define | SCU_PARITY_PEFLAG_PEUSB_Msk (0x10000UL) |
| |
| #define | SCU_PARITY_PEFLAG_PEETH0TX_Pos (17UL) |
| |
| #define | SCU_PARITY_PEFLAG_PEETH0TX_Msk (0x20000UL) |
| |
| #define | SCU_PARITY_PEFLAG_PEETH0RX_Pos (18UL) |
| |
| #define | SCU_PARITY_PEFLAG_PEETH0RX_Msk (0x40000UL) |
| |
| #define | SCU_PARITY_PEFLAG_PESD0_Pos (19UL) |
| |
| #define | SCU_PARITY_PEFLAG_PESD0_Msk (0x80000UL) |
| |
| #define | SCU_PARITY_PEFLAG_PESD1_Pos (20UL) |
| |
| #define | SCU_PARITY_PEFLAG_PESD1_Msk (0x100000UL) |
| |
| #define | SCU_PARITY_PEFLAG_PEECAT0_Pos (24UL) |
| |
| #define | SCU_PARITY_PEFLAG_PEECAT0_Msk (0x1000000UL) |
| |
| #define | SCU_PARITY_PMTPR_PWR_Pos (0UL) |
| |
| #define | SCU_PARITY_PMTPR_PWR_Msk (0xffUL) |
| |
| #define | SCU_PARITY_PMTPR_PRD_Pos (8UL) |
| |
| #define | SCU_PARITY_PMTPR_PRD_Msk (0xff00UL) |
| |
| #define | SCU_PARITY_PMTSR_MTENPS_Pos (0UL) |
| |
| #define | SCU_PARITY_PMTSR_MTENPS_Msk (0x1UL) |
| |
| #define | SCU_PARITY_PMTSR_MTENDS1_Pos (1UL) |
| |
| #define | SCU_PARITY_PMTSR_MTENDS1_Msk (0x2UL) |
| |
| #define | SCU_PARITY_PMTSR_MTENDS2_Pos (2UL) |
| |
| #define | SCU_PARITY_PMTSR_MTENDS2_Msk (0x4UL) |
| |
| #define | SCU_PARITY_PMTSR_MTEU0_Pos (8UL) |
| |
| #define | SCU_PARITY_PMTSR_MTEU0_Msk (0x100UL) |
| |
| #define | SCU_PARITY_PMTSR_MTEU1_Pos (9UL) |
| |
| #define | SCU_PARITY_PMTSR_MTEU1_Msk (0x200UL) |
| |
| #define | SCU_PARITY_PMTSR_MTEU2_Pos (10UL) |
| |
| #define | SCU_PARITY_PMTSR_MTEU2_Msk (0x400UL) |
| |
| #define | SCU_PARITY_PMTSR_MTEMC_Pos (12UL) |
| |
| #define | SCU_PARITY_PMTSR_MTEMC_Msk (0x1000UL) |
| |
| #define | SCU_PARITY_PMTSR_MTEPPRF_Pos (13UL) |
| |
| #define | SCU_PARITY_PMTSR_MTEPPRF_Msk (0x2000UL) |
| |
| #define | SCU_PARITY_PMTSR_MTUSB_Pos (16UL) |
| |
| #define | SCU_PARITY_PMTSR_MTUSB_Msk (0x10000UL) |
| |
| #define | SCU_PARITY_PMTSR_MTETH0TX_Pos (17UL) |
| |
| #define | SCU_PARITY_PMTSR_MTETH0TX_Msk (0x20000UL) |
| |
| #define | SCU_PARITY_PMTSR_MTETH0RX_Pos (18UL) |
| |
| #define | SCU_PARITY_PMTSR_MTETH0RX_Msk (0x40000UL) |
| |
| #define | SCU_PARITY_PMTSR_MTSD0_Pos (19UL) |
| |
| #define | SCU_PARITY_PMTSR_MTSD0_Msk (0x80000UL) |
| |
| #define | SCU_PARITY_PMTSR_MTSD1_Pos (20UL) |
| |
| #define | SCU_PARITY_PMTSR_MTSD1_Msk (0x100000UL) |
| |
| #define | SCU_PARITY_PMTSR_MTECAT0_Pos (24UL) |
| |
| #define | SCU_PARITY_PMTSR_MTECAT0_Msk (0x1000000UL) |
| |
| #define | SCU_TRAP_TRAPSTAT_SOSCWDGT_Pos (0UL) |
| |
| #define | SCU_TRAP_TRAPSTAT_SOSCWDGT_Msk (0x1UL) |
| |
| #define | SCU_TRAP_TRAPSTAT_SVCOLCKT_Pos (2UL) |
| |
| #define | SCU_TRAP_TRAPSTAT_SVCOLCKT_Msk (0x4UL) |
| |
| #define | SCU_TRAP_TRAPSTAT_UVCOLCKT_Pos (3UL) |
| |
| #define | SCU_TRAP_TRAPSTAT_UVCOLCKT_Msk (0x8UL) |
| |
| #define | SCU_TRAP_TRAPSTAT_PET_Pos (4UL) |
| |
| #define | SCU_TRAP_TRAPSTAT_PET_Msk (0x10UL) |
| |
| #define | SCU_TRAP_TRAPSTAT_BRWNT_Pos (5UL) |
| |
| #define | SCU_TRAP_TRAPSTAT_BRWNT_Msk (0x20UL) |
| |
| #define | SCU_TRAP_TRAPSTAT_ULPWDGT_Pos (6UL) |
| |
| #define | SCU_TRAP_TRAPSTAT_ULPWDGT_Msk (0x40UL) |
| |
| #define | SCU_TRAP_TRAPSTAT_BWERR0T_Pos (7UL) |
| |
| #define | SCU_TRAP_TRAPSTAT_BWERR0T_Msk (0x80UL) |
| |
| #define | SCU_TRAP_TRAPSTAT_BWERR1T_Pos (8UL) |
| |
| #define | SCU_TRAP_TRAPSTAT_BWERR1T_Msk (0x100UL) |
| |
| #define | SCU_TRAP_TRAPSTAT_ECAT0RST_Pos (16UL) |
| |
| #define | SCU_TRAP_TRAPSTAT_ECAT0RST_Msk (0x10000UL) |
| |
| #define | SCU_TRAP_TRAPRAW_SOSCWDGT_Pos (0UL) |
| |
| #define | SCU_TRAP_TRAPRAW_SOSCWDGT_Msk (0x1UL) |
| |
| #define | SCU_TRAP_TRAPRAW_SVCOLCKT_Pos (2UL) |
| |
| #define | SCU_TRAP_TRAPRAW_SVCOLCKT_Msk (0x4UL) |
| |
| #define | SCU_TRAP_TRAPRAW_UVCOLCKT_Pos (3UL) |
| |
| #define | SCU_TRAP_TRAPRAW_UVCOLCKT_Msk (0x8UL) |
| |
| #define | SCU_TRAP_TRAPRAW_PET_Pos (4UL) |
| |
| #define | SCU_TRAP_TRAPRAW_PET_Msk (0x10UL) |
| |
| #define | SCU_TRAP_TRAPRAW_BRWNT_Pos (5UL) |
| |
| #define | SCU_TRAP_TRAPRAW_BRWNT_Msk (0x20UL) |
| |
| #define | SCU_TRAP_TRAPRAW_ULPWDGT_Pos (6UL) |
| |
| #define | SCU_TRAP_TRAPRAW_ULPWDGT_Msk (0x40UL) |
| |
| #define | SCU_TRAP_TRAPRAW_BWERR0T_Pos (7UL) |
| |
| #define | SCU_TRAP_TRAPRAW_BWERR0T_Msk (0x80UL) |
| |
| #define | SCU_TRAP_TRAPRAW_BWERR1T_Pos (8UL) |
| |
| #define | SCU_TRAP_TRAPRAW_BWERR1T_Msk (0x100UL) |
| |
| #define | SCU_TRAP_TRAPRAW_ECAT0RST_Pos (16UL) |
| |
| #define | SCU_TRAP_TRAPRAW_ECAT0RST_Msk (0x10000UL) |
| |
| #define | SCU_TRAP_TRAPDIS_SOSCWDGT_Pos (0UL) |
| |
| #define | SCU_TRAP_TRAPDIS_SOSCWDGT_Msk (0x1UL) |
| |
| #define | SCU_TRAP_TRAPDIS_SVCOLCKT_Pos (2UL) |
| |
| #define | SCU_TRAP_TRAPDIS_SVCOLCKT_Msk (0x4UL) |
| |
| #define | SCU_TRAP_TRAPDIS_UVCOLCKT_Pos (3UL) |
| |
| #define | SCU_TRAP_TRAPDIS_UVCOLCKT_Msk (0x8UL) |
| |
| #define | SCU_TRAP_TRAPDIS_PET_Pos (4UL) |
| |
| #define | SCU_TRAP_TRAPDIS_PET_Msk (0x10UL) |
| |
| #define | SCU_TRAP_TRAPDIS_BRWNT_Pos (5UL) |
| |
| #define | SCU_TRAP_TRAPDIS_BRWNT_Msk (0x20UL) |
| |
| #define | SCU_TRAP_TRAPDIS_ULPWDGT_Pos (6UL) |
| |
| #define | SCU_TRAP_TRAPDIS_ULPWDGT_Msk (0x40UL) |
| |
| #define | SCU_TRAP_TRAPDIS_BWERR0T_Pos (7UL) |
| |
| #define | SCU_TRAP_TRAPDIS_BWERR0T_Msk (0x80UL) |
| |
| #define | SCU_TRAP_TRAPDIS_BWERR1T_Pos (8UL) |
| |
| #define | SCU_TRAP_TRAPDIS_BWERR1T_Msk (0x100UL) |
| |
| #define | SCU_TRAP_TRAPDIS_ECAT0RST_Pos (16UL) |
| |
| #define | SCU_TRAP_TRAPDIS_ECAT0RST_Msk (0x10000UL) |
| |
| #define | SCU_TRAP_TRAPCLR_SOSCWDGT_Pos (0UL) |
| |
| #define | SCU_TRAP_TRAPCLR_SOSCWDGT_Msk (0x1UL) |
| |
| #define | SCU_TRAP_TRAPCLR_SVCOLCKT_Pos (2UL) |
| |
| #define | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk (0x4UL) |
| |
| #define | SCU_TRAP_TRAPCLR_UVCOLCKT_Pos (3UL) |
| |
| #define | SCU_TRAP_TRAPCLR_UVCOLCKT_Msk (0x8UL) |
| |
| #define | SCU_TRAP_TRAPCLR_PET_Pos (4UL) |
| |
| #define | SCU_TRAP_TRAPCLR_PET_Msk (0x10UL) |
| |
| #define | SCU_TRAP_TRAPCLR_BRWNT_Pos (5UL) |
| |
| #define | SCU_TRAP_TRAPCLR_BRWNT_Msk (0x20UL) |
| |
| #define | SCU_TRAP_TRAPCLR_ULPWDGT_Pos (6UL) |
| |
| #define | SCU_TRAP_TRAPCLR_ULPWDGT_Msk (0x40UL) |
| |
| #define | SCU_TRAP_TRAPCLR_BWERR0T_Pos (7UL) |
| |
| #define | SCU_TRAP_TRAPCLR_BWERR0T_Msk (0x80UL) |
| |
| #define | SCU_TRAP_TRAPCLR_BWERR1T_Pos (8UL) |
| |
| #define | SCU_TRAP_TRAPCLR_BWERR1T_Msk (0x100UL) |
| |
| #define | SCU_TRAP_TRAPCLR_ECAT0RST_Pos (16UL) |
| |
| #define | SCU_TRAP_TRAPCLR_ECAT0RST_Msk (0x10000UL) |
| |
| #define | SCU_TRAP_TRAPSET_SOSCWDGT_Pos (0UL) |
| |
| #define | SCU_TRAP_TRAPSET_SOSCWDGT_Msk (0x1UL) |
| |
| #define | SCU_TRAP_TRAPSET_SVCOLCKT_Pos (2UL) |
| |
| #define | SCU_TRAP_TRAPSET_SVCOLCKT_Msk (0x4UL) |
| |
| #define | SCU_TRAP_TRAPSET_UVCOLCKT_Pos (3UL) |
| |
| #define | SCU_TRAP_TRAPSET_UVCOLCKT_Msk (0x8UL) |
| |
| #define | SCU_TRAP_TRAPSET_PET_Pos (4UL) |
| |
| #define | SCU_TRAP_TRAPSET_PET_Msk (0x10UL) |
| |
| #define | SCU_TRAP_TRAPSET_BRWNT_Pos (5UL) |
| |
| #define | SCU_TRAP_TRAPSET_BRWNT_Msk (0x20UL) |
| |
| #define | SCU_TRAP_TRAPSET_ULPWDT_Pos (6UL) |
| |
| #define | SCU_TRAP_TRAPSET_ULPWDT_Msk (0x40UL) |
| |
| #define | SCU_TRAP_TRAPSET_BWERR0T_Pos (7UL) |
| |
| #define | SCU_TRAP_TRAPSET_BWERR0T_Msk (0x80UL) |
| |
| #define | SCU_TRAP_TRAPSET_BWERR1T_Pos (8UL) |
| |
| #define | SCU_TRAP_TRAPSET_BWERR1T_Msk (0x100UL) |
| |
| #define | SCU_TRAP_TRAPSET_ECAT0RST_Pos (16UL) |
| |
| #define | SCU_TRAP_TRAPSET_ECAT0RST_Msk (0x10000UL) |
| |
| #define | SCU_HIBERNATE_HDSTAT_EPEV_Pos (0UL) |
| |
| #define | SCU_HIBERNATE_HDSTAT_EPEV_Msk (0x1UL) |
| |
| #define | SCU_HIBERNATE_HDSTAT_ENEV_Pos (1UL) |
| |
| #define | SCU_HIBERNATE_HDSTAT_ENEV_Msk (0x2UL) |
| |
| #define | SCU_HIBERNATE_HDSTAT_RTCEV_Pos (2UL) |
| |
| #define | SCU_HIBERNATE_HDSTAT_RTCEV_Msk (0x4UL) |
| |
| #define | SCU_HIBERNATE_HDSTAT_ULPWDG_Pos (3UL) |
| |
| #define | SCU_HIBERNATE_HDSTAT_ULPWDG_Msk (0x8UL) |
| |
| #define | SCU_HIBERNATE_HDSTAT_HIBNOUT_Pos (4UL) |
| |
| #define | SCU_HIBERNATE_HDSTAT_HIBNOUT_Msk (0x10UL) |
| |
| #define | SCU_HIBERNATE_HDCLR_EPEV_Pos (0UL) |
| |
| #define | SCU_HIBERNATE_HDCLR_EPEV_Msk (0x1UL) |
| |
| #define | SCU_HIBERNATE_HDCLR_ENEV_Pos (1UL) |
| |
| #define | SCU_HIBERNATE_HDCLR_ENEV_Msk (0x2UL) |
| |
| #define | SCU_HIBERNATE_HDCLR_RTCEV_Pos (2UL) |
| |
| #define | SCU_HIBERNATE_HDCLR_RTCEV_Msk (0x4UL) |
| |
| #define | SCU_HIBERNATE_HDCLR_ULPWDG_Pos (3UL) |
| |
| #define | SCU_HIBERNATE_HDCLR_ULPWDG_Msk (0x8UL) |
| |
| #define | SCU_HIBERNATE_HDSET_EPEV_Pos (0UL) |
| |
| #define | SCU_HIBERNATE_HDSET_EPEV_Msk (0x1UL) |
| |
| #define | SCU_HIBERNATE_HDSET_ENEV_Pos (1UL) |
| |
| #define | SCU_HIBERNATE_HDSET_ENEV_Msk (0x2UL) |
| |
| #define | SCU_HIBERNATE_HDSET_RTCEV_Pos (2UL) |
| |
| #define | SCU_HIBERNATE_HDSET_RTCEV_Msk (0x4UL) |
| |
| #define | SCU_HIBERNATE_HDSET_ULPWDG_Pos (3UL) |
| |
| #define | SCU_HIBERNATE_HDSET_ULPWDG_Msk (0x8UL) |
| |
| #define | SCU_HIBERNATE_HDCR_WKPEP_Pos (0UL) |
| |
| #define | SCU_HIBERNATE_HDCR_WKPEP_Msk (0x1UL) |
| |
| #define | SCU_HIBERNATE_HDCR_WKPEN_Pos (1UL) |
| |
| #define | SCU_HIBERNATE_HDCR_WKPEN_Msk (0x2UL) |
| |
| #define | SCU_HIBERNATE_HDCR_RTCE_Pos (2UL) |
| |
| #define | SCU_HIBERNATE_HDCR_RTCE_Msk (0x4UL) |
| |
| #define | SCU_HIBERNATE_HDCR_ULPWDGEN_Pos (3UL) |
| |
| #define | SCU_HIBERNATE_HDCR_ULPWDGEN_Msk (0x8UL) |
| |
| #define | SCU_HIBERNATE_HDCR_HIB_Pos (4UL) |
| |
| #define | SCU_HIBERNATE_HDCR_HIB_Msk (0x10UL) |
| |
| #define | SCU_HIBERNATE_HDCR_RCS_Pos (6UL) |
| |
| #define | SCU_HIBERNATE_HDCR_RCS_Msk (0x40UL) |
| |
| #define | SCU_HIBERNATE_HDCR_STDBYSEL_Pos (7UL) |
| |
| #define | SCU_HIBERNATE_HDCR_STDBYSEL_Msk (0x80UL) |
| |
| #define | SCU_HIBERNATE_HDCR_WKUPSEL_Pos (8UL) |
| |
| #define | SCU_HIBERNATE_HDCR_WKUPSEL_Msk (0x100UL) |
| |
| #define | SCU_HIBERNATE_HDCR_GPI0SEL_Pos (10UL) |
| |
| #define | SCU_HIBERNATE_HDCR_GPI0SEL_Msk (0x400UL) |
| |
| #define | SCU_HIBERNATE_HDCR_HIBIO0POL_Pos (12UL) |
| |
| #define | SCU_HIBERNATE_HDCR_HIBIO0POL_Msk (0x1000UL) |
| |
| #define | SCU_HIBERNATE_HDCR_HIBIO1POL_Pos (13UL) |
| |
| #define | SCU_HIBERNATE_HDCR_HIBIO1POL_Msk (0x2000UL) |
| |
| #define | SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos (16UL) |
| |
| #define | SCU_HIBERNATE_HDCR_HIBIO0SEL_Msk (0xf0000UL) |
| |
| #define | SCU_HIBERNATE_HDCR_HIBIO1SEL_Pos (20UL) |
| |
| #define | SCU_HIBERNATE_HDCR_HIBIO1SEL_Msk (0xf00000UL) |
| |
| #define | SCU_HIBERNATE_OSCSICTRL_PWD_Pos (0UL) |
| |
| #define | SCU_HIBERNATE_OSCSICTRL_PWD_Msk (0x1UL) |
| |
| #define | SCU_HIBERNATE_OSCULSTAT_X1D_Pos (0UL) |
| |
| #define | SCU_HIBERNATE_OSCULSTAT_X1D_Msk (0x1UL) |
| |
| #define | SCU_HIBERNATE_OSCULCTRL_X1DEN_Pos (0UL) |
| |
| #define | SCU_HIBERNATE_OSCULCTRL_X1DEN_Msk (0x1UL) |
| |
| #define | SCU_HIBERNATE_OSCULCTRL_MODE_Pos (4UL) |
| |
| #define | SCU_HIBERNATE_OSCULCTRL_MODE_Msk (0x30UL) |
| |
| #define | SCU_POWER_PWRSTAT_HIBEN_Pos (0UL) |
| |
| #define | SCU_POWER_PWRSTAT_HIBEN_Msk (0x1UL) |
| |
| #define | SCU_POWER_PWRSTAT_USBPHYPDQ_Pos (16UL) |
| |
| #define | SCU_POWER_PWRSTAT_USBPHYPDQ_Msk (0x10000UL) |
| |
| #define | SCU_POWER_PWRSTAT_USBOTGEN_Pos (17UL) |
| |
| #define | SCU_POWER_PWRSTAT_USBOTGEN_Msk (0x20000UL) |
| |
| #define | SCU_POWER_PWRSTAT_USBPUWQ_Pos (18UL) |
| |
| #define | SCU_POWER_PWRSTAT_USBPUWQ_Msk (0x40000UL) |
| |
| #define | SCU_POWER_PWRSET_HIB_Pos (0UL) |
| |
| #define | SCU_POWER_PWRSET_HIB_Msk (0x1UL) |
| |
| #define | SCU_POWER_PWRSET_USBPHYPDQ_Pos (16UL) |
| |
| #define | SCU_POWER_PWRSET_USBPHYPDQ_Msk (0x10000UL) |
| |
| #define | SCU_POWER_PWRSET_USBOTGEN_Pos (17UL) |
| |
| #define | SCU_POWER_PWRSET_USBOTGEN_Msk (0x20000UL) |
| |
| #define | SCU_POWER_PWRSET_USBPUWQ_Pos (18UL) |
| |
| #define | SCU_POWER_PWRSET_USBPUWQ_Msk (0x40000UL) |
| |
| #define | SCU_POWER_PWRCLR_HIB_Pos (0UL) |
| |
| #define | SCU_POWER_PWRCLR_HIB_Msk (0x1UL) |
| |
| #define | SCU_POWER_PWRCLR_USBPHYPDQ_Pos (16UL) |
| |
| #define | SCU_POWER_PWRCLR_USBPHYPDQ_Msk (0x10000UL) |
| |
| #define | SCU_POWER_PWRCLR_USBOTGEN_Pos (17UL) |
| |
| #define | SCU_POWER_PWRCLR_USBOTGEN_Msk (0x20000UL) |
| |
| #define | SCU_POWER_PWRCLR_USBPUWQ_Pos (18UL) |
| |
| #define | SCU_POWER_PWRCLR_USBPUWQ_Msk (0x40000UL) |
| |
| #define | SCU_POWER_EVRSTAT_OV13_Pos (1UL) |
| |
| #define | SCU_POWER_EVRSTAT_OV13_Msk (0x2UL) |
| |
| #define | SCU_POWER_EVRVADCSTAT_VADC13V_Pos (0UL) |
| |
| #define | SCU_POWER_EVRVADCSTAT_VADC13V_Msk (0xffUL) |
| |
| #define | SCU_POWER_EVRVADCSTAT_VADC33V_Pos (8UL) |
| |
| #define | SCU_POWER_EVRVADCSTAT_VADC33V_Msk (0xff00UL) |
| |
| #define | SCU_POWER_PWRMON_THRS_Pos (0UL) |
| |
| #define | SCU_POWER_PWRMON_THRS_Msk (0xffUL) |
| |
| #define | SCU_POWER_PWRMON_INTV_Pos (8UL) |
| |
| #define | SCU_POWER_PWRMON_INTV_Msk (0xff00UL) |
| |
| #define | SCU_POWER_PWRMON_ENB_Pos (16UL) |
| |
| #define | SCU_POWER_PWRMON_ENB_Msk (0x10000UL) |
| |
| #define | SCU_RESET_RSTSTAT_RSTSTAT_Pos (0UL) |
| |
| #define | SCU_RESET_RSTSTAT_RSTSTAT_Msk (0xffUL) |
| |
| #define | SCU_RESET_RSTSTAT_HIBWK_Pos (8UL) |
| |
| #define | SCU_RESET_RSTSTAT_HIBWK_Msk (0x100UL) |
| |
| #define | SCU_RESET_RSTSTAT_HIBRS_Pos (9UL) |
| |
| #define | SCU_RESET_RSTSTAT_HIBRS_Msk (0x200UL) |
| |
| #define | SCU_RESET_RSTSTAT_LCKEN_Pos (10UL) |
| |
| #define | SCU_RESET_RSTSTAT_LCKEN_Msk (0x400UL) |
| |
| #define | SCU_RESET_RSTSTAT_ECAT0RS_Pos (12UL) |
| |
| #define | SCU_RESET_RSTSTAT_ECAT0RS_Msk (0x1000UL) |
| |
| #define | SCU_RESET_RSTSET_HIBWK_Pos (8UL) |
| |
| #define | SCU_RESET_RSTSET_HIBWK_Msk (0x100UL) |
| |
| #define | SCU_RESET_RSTSET_HIBRS_Pos (9UL) |
| |
| #define | SCU_RESET_RSTSET_HIBRS_Msk (0x200UL) |
| |
| #define | SCU_RESET_RSTSET_LCKEN_Pos (10UL) |
| |
| #define | SCU_RESET_RSTSET_LCKEN_Msk (0x400UL) |
| |
| #define | SCU_RESET_RSTSET_ECAT0RS_Pos (12UL) |
| |
| #define | SCU_RESET_RSTSET_ECAT0RS_Msk (0x1000UL) |
| |
| #define | SCU_RESET_RSTCLR_RSCLR_Pos (0UL) |
| |
| #define | SCU_RESET_RSTCLR_RSCLR_Msk (0x1UL) |
| |
| #define | SCU_RESET_RSTCLR_HIBWK_Pos (8UL) |
| |
| #define | SCU_RESET_RSTCLR_HIBWK_Msk (0x100UL) |
| |
| #define | SCU_RESET_RSTCLR_HIBRS_Pos (9UL) |
| |
| #define | SCU_RESET_RSTCLR_HIBRS_Msk (0x200UL) |
| |
| #define | SCU_RESET_RSTCLR_LCKEN_Pos (10UL) |
| |
| #define | SCU_RESET_RSTCLR_LCKEN_Msk (0x400UL) |
| |
| #define | SCU_RESET_RSTCLR_ECAT0RS_Pos (12UL) |
| |
| #define | SCU_RESET_RSTCLR_ECAT0RS_Msk (0x1000UL) |
| |
| #define | SCU_RESET_PRSTAT0_VADCRS_Pos (0UL) |
| |
| #define | SCU_RESET_PRSTAT0_VADCRS_Msk (0x1UL) |
| |
| #define | SCU_RESET_PRSTAT0_DSDRS_Pos (1UL) |
| |
| #define | SCU_RESET_PRSTAT0_DSDRS_Msk (0x2UL) |
| |
| #define | SCU_RESET_PRSTAT0_CCU40RS_Pos (2UL) |
| |
| #define | SCU_RESET_PRSTAT0_CCU40RS_Msk (0x4UL) |
| |
| #define | SCU_RESET_PRSTAT0_CCU41RS_Pos (3UL) |
| |
| #define | SCU_RESET_PRSTAT0_CCU41RS_Msk (0x8UL) |
| |
| #define | SCU_RESET_PRSTAT0_CCU42RS_Pos (4UL) |
| |
| #define | SCU_RESET_PRSTAT0_CCU42RS_Msk (0x10UL) |
| |
| #define | SCU_RESET_PRSTAT0_CCU80RS_Pos (7UL) |
| |
| #define | SCU_RESET_PRSTAT0_CCU80RS_Msk (0x80UL) |
| |
| #define | SCU_RESET_PRSTAT0_CCU81RS_Pos (8UL) |
| |
| #define | SCU_RESET_PRSTAT0_CCU81RS_Msk (0x100UL) |
| |
| #define | SCU_RESET_PRSTAT0_POSIF0RS_Pos (9UL) |
| |
| #define | SCU_RESET_PRSTAT0_POSIF0RS_Msk (0x200UL) |
| |
| #define | SCU_RESET_PRSTAT0_POSIF1RS_Pos (10UL) |
| |
| #define | SCU_RESET_PRSTAT0_POSIF1RS_Msk (0x400UL) |
| |
| #define | SCU_RESET_PRSTAT0_USIC0RS_Pos (11UL) |
| |
| #define | SCU_RESET_PRSTAT0_USIC0RS_Msk (0x800UL) |
| |
| #define | SCU_RESET_PRSTAT0_ERU1RS_Pos (16UL) |
| |
| #define | SCU_RESET_PRSTAT0_ERU1RS_Msk (0x10000UL) |
| |
| #define | SCU_RESET_PRSET0_VADCRS_Pos (0UL) |
| |
| #define | SCU_RESET_PRSET0_VADCRS_Msk (0x1UL) |
| |
| #define | SCU_RESET_PRSET0_DSDRS_Pos (1UL) |
| |
| #define | SCU_RESET_PRSET0_DSDRS_Msk (0x2UL) |
| |
| #define | SCU_RESET_PRSET0_CCU40RS_Pos (2UL) |
| |
| #define | SCU_RESET_PRSET0_CCU40RS_Msk (0x4UL) |
| |
| #define | SCU_RESET_PRSET0_CCU41RS_Pos (3UL) |
| |
| #define | SCU_RESET_PRSET0_CCU41RS_Msk (0x8UL) |
| |
| #define | SCU_RESET_PRSET0_CCU42RS_Pos (4UL) |
| |
| #define | SCU_RESET_PRSET0_CCU42RS_Msk (0x10UL) |
| |
| #define | SCU_RESET_PRSET0_CCU80RS_Pos (7UL) |
| |
| #define | SCU_RESET_PRSET0_CCU80RS_Msk (0x80UL) |
| |
| #define | SCU_RESET_PRSET0_CCU81RS_Pos (8UL) |
| |
| #define | SCU_RESET_PRSET0_CCU81RS_Msk (0x100UL) |
| |
| #define | SCU_RESET_PRSET0_POSIF0RS_Pos (9UL) |
| |
| #define | SCU_RESET_PRSET0_POSIF0RS_Msk (0x200UL) |
| |
| #define | SCU_RESET_PRSET0_POSIF1RS_Pos (10UL) |
| |
| #define | SCU_RESET_PRSET0_POSIF1RS_Msk (0x400UL) |
| |
| #define | SCU_RESET_PRSET0_USIC0RS_Pos (11UL) |
| |
| #define | SCU_RESET_PRSET0_USIC0RS_Msk (0x800UL) |
| |
| #define | SCU_RESET_PRSET0_ERU1RS_Pos (16UL) |
| |
| #define | SCU_RESET_PRSET0_ERU1RS_Msk (0x10000UL) |
| |
| #define | SCU_RESET_PRCLR0_VADCRS_Pos (0UL) |
| |
| #define | SCU_RESET_PRCLR0_VADCRS_Msk (0x1UL) |
| |
| #define | SCU_RESET_PRCLR0_DSDRS_Pos (1UL) |
| |
| #define | SCU_RESET_PRCLR0_DSDRS_Msk (0x2UL) |
| |
| #define | SCU_RESET_PRCLR0_CCU40RS_Pos (2UL) |
| |
| #define | SCU_RESET_PRCLR0_CCU40RS_Msk (0x4UL) |
| |
| #define | SCU_RESET_PRCLR0_CCU41RS_Pos (3UL) |
| |
| #define | SCU_RESET_PRCLR0_CCU41RS_Msk (0x8UL) |
| |
| #define | SCU_RESET_PRCLR0_CCU42RS_Pos (4UL) |
| |
| #define | SCU_RESET_PRCLR0_CCU42RS_Msk (0x10UL) |
| |
| #define | SCU_RESET_PRCLR0_CCU80RS_Pos (7UL) |
| |
| #define | SCU_RESET_PRCLR0_CCU80RS_Msk (0x80UL) |
| |
| #define | SCU_RESET_PRCLR0_CCU81RS_Pos (8UL) |
| |
| #define | SCU_RESET_PRCLR0_CCU81RS_Msk (0x100UL) |
| |
| #define | SCU_RESET_PRCLR0_POSIF0RS_Pos (9UL) |
| |
| #define | SCU_RESET_PRCLR0_POSIF0RS_Msk (0x200UL) |
| |
| #define | SCU_RESET_PRCLR0_POSIF1RS_Pos (10UL) |
| |
| #define | SCU_RESET_PRCLR0_POSIF1RS_Msk (0x400UL) |
| |
| #define | SCU_RESET_PRCLR0_USIC0RS_Pos (11UL) |
| |
| #define | SCU_RESET_PRCLR0_USIC0RS_Msk (0x800UL) |
| |
| #define | SCU_RESET_PRCLR0_ERU1RS_Pos (16UL) |
| |
| #define | SCU_RESET_PRCLR0_ERU1RS_Msk (0x10000UL) |
| |
| #define | SCU_RESET_PRSTAT1_CCU43RS_Pos (0UL) |
| |
| #define | SCU_RESET_PRSTAT1_CCU43RS_Msk (0x1UL) |
| |
| #define | SCU_RESET_PRSTAT1_LEDTSCU0RS_Pos (3UL) |
| |
| #define | SCU_RESET_PRSTAT1_LEDTSCU0RS_Msk (0x8UL) |
| |
| #define | SCU_RESET_PRSTAT1_MCAN0RS_Pos (4UL) |
| |
| #define | SCU_RESET_PRSTAT1_MCAN0RS_Msk (0x10UL) |
| |
| #define | SCU_RESET_PRSTAT1_DACRS_Pos (5UL) |
| |
| #define | SCU_RESET_PRSTAT1_DACRS_Msk (0x20UL) |
| |
| #define | SCU_RESET_PRSTAT1_MMCIRS_Pos (6UL) |
| |
| #define | SCU_RESET_PRSTAT1_MMCIRS_Msk (0x40UL) |
| |
| #define | SCU_RESET_PRSTAT1_USIC1RS_Pos (7UL) |
| |
| #define | SCU_RESET_PRSTAT1_USIC1RS_Msk (0x80UL) |
| |
| #define | SCU_RESET_PRSTAT1_USIC2RS_Pos (8UL) |
| |
| #define | SCU_RESET_PRSTAT1_USIC2RS_Msk (0x100UL) |
| |
| #define | SCU_RESET_PRSTAT1_PPORTSRS_Pos (9UL) |
| |
| #define | SCU_RESET_PRSTAT1_PPORTSRS_Msk (0x200UL) |
| |
| #define | SCU_RESET_PRSET1_CCU43RS_Pos (0UL) |
| |
| #define | SCU_RESET_PRSET1_CCU43RS_Msk (0x1UL) |
| |
| #define | SCU_RESET_PRSET1_LEDTSCU0RS_Pos (3UL) |
| |
| #define | SCU_RESET_PRSET1_LEDTSCU0RS_Msk (0x8UL) |
| |
| #define | SCU_RESET_PRSET1_MCAN0RS_Pos (4UL) |
| |
| #define | SCU_RESET_PRSET1_MCAN0RS_Msk (0x10UL) |
| |
| #define | SCU_RESET_PRSET1_DACRS_Pos (5UL) |
| |
| #define | SCU_RESET_PRSET1_DACRS_Msk (0x20UL) |
| |
| #define | SCU_RESET_PRSET1_MMCIRS_Pos (6UL) |
| |
| #define | SCU_RESET_PRSET1_MMCIRS_Msk (0x40UL) |
| |
| #define | SCU_RESET_PRSET1_USIC1RS_Pos (7UL) |
| |
| #define | SCU_RESET_PRSET1_USIC1RS_Msk (0x80UL) |
| |
| #define | SCU_RESET_PRSET1_USIC2RS_Pos (8UL) |
| |
| #define | SCU_RESET_PRSET1_USIC2RS_Msk (0x100UL) |
| |
| #define | SCU_RESET_PRSET1_PPORTSRS_Pos (9UL) |
| |
| #define | SCU_RESET_PRSET1_PPORTSRS_Msk (0x200UL) |
| |
| #define | SCU_RESET_PRCLR1_CCU43RS_Pos (0UL) |
| |
| #define | SCU_RESET_PRCLR1_CCU43RS_Msk (0x1UL) |
| |
| #define | SCU_RESET_PRCLR1_LEDTSCU0RS_Pos (3UL) |
| |
| #define | SCU_RESET_PRCLR1_LEDTSCU0RS_Msk (0x8UL) |
| |
| #define | SCU_RESET_PRCLR1_MCAN0RS_Pos (4UL) |
| |
| #define | SCU_RESET_PRCLR1_MCAN0RS_Msk (0x10UL) |
| |
| #define | SCU_RESET_PRCLR1_DACRS_Pos (5UL) |
| |
| #define | SCU_RESET_PRCLR1_DACRS_Msk (0x20UL) |
| |
| #define | SCU_RESET_PRCLR1_MMCIRS_Pos (6UL) |
| |
| #define | SCU_RESET_PRCLR1_MMCIRS_Msk (0x40UL) |
| |
| #define | SCU_RESET_PRCLR1_USIC1RS_Pos (7UL) |
| |
| #define | SCU_RESET_PRCLR1_USIC1RS_Msk (0x80UL) |
| |
| #define | SCU_RESET_PRCLR1_USIC2RS_Pos (8UL) |
| |
| #define | SCU_RESET_PRCLR1_USIC2RS_Msk (0x100UL) |
| |
| #define | SCU_RESET_PRCLR1_PPORTSRS_Pos (9UL) |
| |
| #define | SCU_RESET_PRCLR1_PPORTSRS_Msk (0x200UL) |
| |
| #define | SCU_RESET_PRSTAT2_WDTRS_Pos (1UL) |
| |
| #define | SCU_RESET_PRSTAT2_WDTRS_Msk (0x2UL) |
| |
| #define | SCU_RESET_PRSTAT2_ETH0RS_Pos (2UL) |
| |
| #define | SCU_RESET_PRSTAT2_ETH0RS_Msk (0x4UL) |
| |
| #define | SCU_RESET_PRSTAT2_DMA0RS_Pos (4UL) |
| |
| #define | SCU_RESET_PRSTAT2_DMA0RS_Msk (0x10UL) |
| |
| #define | SCU_RESET_PRSTAT2_DMA1RS_Pos (5UL) |
| |
| #define | SCU_RESET_PRSTAT2_DMA1RS_Msk (0x20UL) |
| |
| #define | SCU_RESET_PRSTAT2_FCERS_Pos (6UL) |
| |
| #define | SCU_RESET_PRSTAT2_FCERS_Msk (0x40UL) |
| |
| #define | SCU_RESET_PRSTAT2_USBRS_Pos (7UL) |
| |
| #define | SCU_RESET_PRSTAT2_USBRS_Msk (0x80UL) |
| |
| #define | SCU_RESET_PRSTAT2_ECAT0RS_Pos (10UL) |
| |
| #define | SCU_RESET_PRSTAT2_ECAT0RS_Msk (0x400UL) |
| |
| #define | SCU_RESET_PRSET2_WDTRS_Pos (1UL) |
| |
| #define | SCU_RESET_PRSET2_WDTRS_Msk (0x2UL) |
| |
| #define | SCU_RESET_PRSET2_ETH0RS_Pos (2UL) |
| |
| #define | SCU_RESET_PRSET2_ETH0RS_Msk (0x4UL) |
| |
| #define | SCU_RESET_PRSET2_DMA0RS_Pos (4UL) |
| |
| #define | SCU_RESET_PRSET2_DMA0RS_Msk (0x10UL) |
| |
| #define | SCU_RESET_PRSET2_DMA1RS_Pos (5UL) |
| |
| #define | SCU_RESET_PRSET2_DMA1RS_Msk (0x20UL) |
| |
| #define | SCU_RESET_PRSET2_FCERS_Pos (6UL) |
| |
| #define | SCU_RESET_PRSET2_FCERS_Msk (0x40UL) |
| |
| #define | SCU_RESET_PRSET2_USBRS_Pos (7UL) |
| |
| #define | SCU_RESET_PRSET2_USBRS_Msk (0x80UL) |
| |
| #define | SCU_RESET_PRSET2_ECAT0RS_Pos (10UL) |
| |
| #define | SCU_RESET_PRSET2_ECAT0RS_Msk (0x400UL) |
| |
| #define | SCU_RESET_PRCLR2_WDTRS_Pos (1UL) |
| |
| #define | SCU_RESET_PRCLR2_WDTRS_Msk (0x2UL) |
| |
| #define | SCU_RESET_PRCLR2_ETH0RS_Pos (2UL) |
| |
| #define | SCU_RESET_PRCLR2_ETH0RS_Msk (0x4UL) |
| |
| #define | SCU_RESET_PRCLR2_DMA0RS_Pos (4UL) |
| |
| #define | SCU_RESET_PRCLR2_DMA0RS_Msk (0x10UL) |
| |
| #define | SCU_RESET_PRCLR2_DMA1RS_Pos (5UL) |
| |
| #define | SCU_RESET_PRCLR2_DMA1RS_Msk (0x20UL) |
| |
| #define | SCU_RESET_PRCLR2_FCERS_Pos (6UL) |
| |
| #define | SCU_RESET_PRCLR2_FCERS_Msk (0x40UL) |
| |
| #define | SCU_RESET_PRCLR2_USBRS_Pos (7UL) |
| |
| #define | SCU_RESET_PRCLR2_USBRS_Msk (0x80UL) |
| |
| #define | SCU_RESET_PRCLR2_ECAT0RS_Pos (10UL) |
| |
| #define | SCU_RESET_PRCLR2_ECAT0RS_Msk (0x400UL) |
| |
| #define | SCU_RESET_PRSTAT3_EBURS_Pos (2UL) |
| |
| #define | SCU_RESET_PRSTAT3_EBURS_Msk (0x4UL) |
| |
| #define | SCU_RESET_PRSET3_EBURS_Pos (2UL) |
| |
| #define | SCU_RESET_PRSET3_EBURS_Msk (0x4UL) |
| |
| #define | SCU_RESET_PRCLR3_EBURS_Pos (2UL) |
| |
| #define | SCU_RESET_PRCLR3_EBURS_Msk (0x4UL) |
| |
| #define | LEDTS_ID_MOD_REV_Pos (0UL) |
| |
| #define | LEDTS_ID_MOD_REV_Msk (0xffUL) |
| |
| #define | LEDTS_ID_MOD_TYPE_Pos (8UL) |
| |
| #define | LEDTS_ID_MOD_TYPE_Msk (0xff00UL) |
| |
| #define | LEDTS_ID_MOD_NUMBER_Pos (16UL) |
| |
| #define | LEDTS_ID_MOD_NUMBER_Msk (0xffff0000UL) |
| |
| #define | LEDTS_GLOBCTL_TS_EN_Pos (0UL) |
| |
| #define | LEDTS_GLOBCTL_TS_EN_Msk (0x1UL) |
| |
| #define | LEDTS_GLOBCTL_LD_EN_Pos (1UL) |
| |
| #define | LEDTS_GLOBCTL_LD_EN_Msk (0x2UL) |
| |
| #define | LEDTS_GLOBCTL_CMTR_Pos (2UL) |
| |
| #define | LEDTS_GLOBCTL_CMTR_Msk (0x4UL) |
| |
| #define | LEDTS_GLOBCTL_ENSYNC_Pos (3UL) |
| |
| #define | LEDTS_GLOBCTL_ENSYNC_Msk (0x8UL) |
| |
| #define | LEDTS_GLOBCTL_SUSCFG_Pos (8UL) |
| |
| #define | LEDTS_GLOBCTL_SUSCFG_Msk (0x100UL) |
| |
| #define | LEDTS_GLOBCTL_MASKVAL_Pos (9UL) |
| |
| #define | LEDTS_GLOBCTL_MASKVAL_Msk (0xe00UL) |
| |
| #define | LEDTS_GLOBCTL_FENVAL_Pos (12UL) |
| |
| #define | LEDTS_GLOBCTL_FENVAL_Msk (0x1000UL) |
| |
| #define | LEDTS_GLOBCTL_ITS_EN_Pos (13UL) |
| |
| #define | LEDTS_GLOBCTL_ITS_EN_Msk (0x2000UL) |
| |
| #define | LEDTS_GLOBCTL_ITF_EN_Pos (14UL) |
| |
| #define | LEDTS_GLOBCTL_ITF_EN_Msk (0x4000UL) |
| |
| #define | LEDTS_GLOBCTL_ITP_EN_Pos (15UL) |
| |
| #define | LEDTS_GLOBCTL_ITP_EN_Msk (0x8000UL) |
| |
| #define | LEDTS_GLOBCTL_CLK_PS_Pos (16UL) |
| |
| #define | LEDTS_GLOBCTL_CLK_PS_Msk (0xffff0000UL) |
| |
| #define | LEDTS_FNCTL_PADT_Pos (0UL) |
| |
| #define | LEDTS_FNCTL_PADT_Msk (0x7UL) |
| |
| #define | LEDTS_FNCTL_PADTSW_Pos (3UL) |
| |
| #define | LEDTS_FNCTL_PADTSW_Msk (0x8UL) |
| |
| #define | LEDTS_FNCTL_EPULL_Pos (4UL) |
| |
| #define | LEDTS_FNCTL_EPULL_Msk (0x10UL) |
| |
| #define | LEDTS_FNCTL_FNCOL_Pos (5UL) |
| |
| #define | LEDTS_FNCTL_FNCOL_Msk (0xe0UL) |
| |
| #define | LEDTS_FNCTL_ACCCNT_Pos (16UL) |
| |
| #define | LEDTS_FNCTL_ACCCNT_Msk (0xf0000UL) |
| |
| #define | LEDTS_FNCTL_TSCCMP_Pos (20UL) |
| |
| #define | LEDTS_FNCTL_TSCCMP_Msk (0x100000UL) |
| |
| #define | LEDTS_FNCTL_TSOEXT_Pos (21UL) |
| |
| #define | LEDTS_FNCTL_TSOEXT_Msk (0x600000UL) |
| |
| #define | LEDTS_FNCTL_TSCTRR_Pos (23UL) |
| |
| #define | LEDTS_FNCTL_TSCTRR_Msk (0x800000UL) |
| |
| #define | LEDTS_FNCTL_TSCTRSAT_Pos (24UL) |
| |
| #define | LEDTS_FNCTL_TSCTRSAT_Msk (0x1000000UL) |
| |
| #define | LEDTS_FNCTL_NR_TSIN_Pos (25UL) |
| |
| #define | LEDTS_FNCTL_NR_TSIN_Msk (0xe000000UL) |
| |
| #define | LEDTS_FNCTL_COLLEV_Pos (28UL) |
| |
| #define | LEDTS_FNCTL_COLLEV_Msk (0x10000000UL) |
| |
| #define | LEDTS_FNCTL_NR_LEDCOL_Pos (29UL) |
| |
| #define | LEDTS_FNCTL_NR_LEDCOL_Msk (0xe0000000UL) |
| |
| #define | LEDTS_EVFR_TSF_Pos (0UL) |
| |
| #define | LEDTS_EVFR_TSF_Msk (0x1UL) |
| |
| #define | LEDTS_EVFR_TFF_Pos (1UL) |
| |
| #define | LEDTS_EVFR_TFF_Msk (0x2UL) |
| |
| #define | LEDTS_EVFR_TPF_Pos (2UL) |
| |
| #define | LEDTS_EVFR_TPF_Msk (0x4UL) |
| |
| #define | LEDTS_EVFR_TSCTROVF_Pos (3UL) |
| |
| #define | LEDTS_EVFR_TSCTROVF_Msk (0x8UL) |
| |
| #define | LEDTS_EVFR_CTSF_Pos (16UL) |
| |
| #define | LEDTS_EVFR_CTSF_Msk (0x10000UL) |
| |
| #define | LEDTS_EVFR_CTFF_Pos (17UL) |
| |
| #define | LEDTS_EVFR_CTFF_Msk (0x20000UL) |
| |
| #define | LEDTS_EVFR_CTPF_Pos (18UL) |
| |
| #define | LEDTS_EVFR_CTPF_Msk (0x40000UL) |
| |
| #define | LEDTS_TSVAL_TSCTRVALR_Pos (0UL) |
| |
| #define | LEDTS_TSVAL_TSCTRVALR_Msk (0xffffUL) |
| |
| #define | LEDTS_TSVAL_TSCTRVAL_Pos (16UL) |
| |
| #define | LEDTS_TSVAL_TSCTRVAL_Msk (0xffff0000UL) |
| |
| #define | LEDTS_LINE0_LINE_0_Pos (0UL) |
| |
| #define | LEDTS_LINE0_LINE_0_Msk (0xffUL) |
| |
| #define | LEDTS_LINE0_LINE_1_Pos (8UL) |
| |
| #define | LEDTS_LINE0_LINE_1_Msk (0xff00UL) |
| |
| #define | LEDTS_LINE0_LINE_2_Pos (16UL) |
| |
| #define | LEDTS_LINE0_LINE_2_Msk (0xff0000UL) |
| |
| #define | LEDTS_LINE0_LINE_3_Pos (24UL) |
| |
| #define | LEDTS_LINE0_LINE_3_Msk (0xff000000UL) |
| |
| #define | LEDTS_LINE1_LINE_4_Pos (0UL) |
| |
| #define | LEDTS_LINE1_LINE_4_Msk (0xffUL) |
| |
| #define | LEDTS_LINE1_LINE_5_Pos (8UL) |
| |
| #define | LEDTS_LINE1_LINE_5_Msk (0xff00UL) |
| |
| #define | LEDTS_LINE1_LINE_6_Pos (16UL) |
| |
| #define | LEDTS_LINE1_LINE_6_Msk (0xff0000UL) |
| |
| #define | LEDTS_LINE1_LINE_A_Pos (24UL) |
| |
| #define | LEDTS_LINE1_LINE_A_Msk (0xff000000UL) |
| |
| #define | LEDTS_LDCMP0_CMP_LD0_Pos (0UL) |
| |
| #define | LEDTS_LDCMP0_CMP_LD0_Msk (0xffUL) |
| |
| #define | LEDTS_LDCMP0_CMP_LD1_Pos (8UL) |
| |
| #define | LEDTS_LDCMP0_CMP_LD1_Msk (0xff00UL) |
| |
| #define | LEDTS_LDCMP0_CMP_LD2_Pos (16UL) |
| |
| #define | LEDTS_LDCMP0_CMP_LD2_Msk (0xff0000UL) |
| |
| #define | LEDTS_LDCMP0_CMP_LD3_Pos (24UL) |
| |
| #define | LEDTS_LDCMP0_CMP_LD3_Msk (0xff000000UL) |
| |
| #define | LEDTS_LDCMP1_CMP_LD4_Pos (0UL) |
| |
| #define | LEDTS_LDCMP1_CMP_LD4_Msk (0xffUL) |
| |
| #define | LEDTS_LDCMP1_CMP_LD5_Pos (8UL) |
| |
| #define | LEDTS_LDCMP1_CMP_LD5_Msk (0xff00UL) |
| |
| #define | LEDTS_LDCMP1_CMP_LD6_Pos (16UL) |
| |
| #define | LEDTS_LDCMP1_CMP_LD6_Msk (0xff0000UL) |
| |
| #define | LEDTS_LDCMP1_CMP_LDA_TSCOM_Pos (24UL) |
| |
| #define | LEDTS_LDCMP1_CMP_LDA_TSCOM_Msk (0xff000000UL) |
| |
| #define | LEDTS_TSCMP0_CMP_TS0_Pos (0UL) |
| |
| #define | LEDTS_TSCMP0_CMP_TS0_Msk (0xffUL) |
| |
| #define | LEDTS_TSCMP0_CMP_TS1_Pos (8UL) |
| |
| #define | LEDTS_TSCMP0_CMP_TS1_Msk (0xff00UL) |
| |
| #define | LEDTS_TSCMP0_CMP_TS2_Pos (16UL) |
| |
| #define | LEDTS_TSCMP0_CMP_TS2_Msk (0xff0000UL) |
| |
| #define | LEDTS_TSCMP0_CMP_TS3_Pos (24UL) |
| |
| #define | LEDTS_TSCMP0_CMP_TS3_Msk (0xff000000UL) |
| |
| #define | LEDTS_TSCMP1_CMP_TS4_Pos (0UL) |
| |
| #define | LEDTS_TSCMP1_CMP_TS4_Msk (0xffUL) |
| |
| #define | LEDTS_TSCMP1_CMP_TS5_Pos (8UL) |
| |
| #define | LEDTS_TSCMP1_CMP_TS5_Msk (0xff00UL) |
| |
| #define | LEDTS_TSCMP1_CMP_TS6_Pos (16UL) |
| |
| #define | LEDTS_TSCMP1_CMP_TS6_Msk (0xff0000UL) |
| |
| #define | LEDTS_TSCMP1_CMP_TS7_Pos (24UL) |
| |
| #define | LEDTS_TSCMP1_CMP_TS7_Msk (0xff000000UL) |
| |
| #define | SDMMC_BLOCK_SIZE_TX_BLOCK_SIZE_Pos (0UL) |
| |
| #define | SDMMC_BLOCK_SIZE_TX_BLOCK_SIZE_Msk (0xfffUL) |
| |
| #define | SDMMC_BLOCK_SIZE_TX_BLOCK_SIZE_12_Pos (15UL) |
| |
| #define | SDMMC_BLOCK_SIZE_TX_BLOCK_SIZE_12_Msk (0x8000UL) |
| |
| #define | SDMMC_BLOCK_COUNT_BLOCK_COUNT_Pos (0UL) |
| |
| #define | SDMMC_BLOCK_COUNT_BLOCK_COUNT_Msk (0xffffUL) |
| |
| #define | SDMMC_ARGUMENT1_ARGUMENT1_Pos (0UL) |
| |
| #define | SDMMC_ARGUMENT1_ARGUMENT1_Msk (0xffffffffUL) |
| |
| #define | SDMMC_TRANSFER_MODE_BLOCK_COUNT_EN_Pos (1UL) |
| |
| #define | SDMMC_TRANSFER_MODE_BLOCK_COUNT_EN_Msk (0x2UL) |
| |
| #define | SDMMC_TRANSFER_MODE_ACMD_EN_Pos (2UL) |
| |
| #define | SDMMC_TRANSFER_MODE_ACMD_EN_Msk (0xcUL) |
| |
| #define | SDMMC_TRANSFER_MODE_TX_DIR_SELECT_Pos (4UL) |
| |
| #define | SDMMC_TRANSFER_MODE_TX_DIR_SELECT_Msk (0x10UL) |
| |
| #define | SDMMC_TRANSFER_MODE_MULTI_BLOCK_SELECT_Pos (5UL) |
| |
| #define | SDMMC_TRANSFER_MODE_MULTI_BLOCK_SELECT_Msk (0x20UL) |
| |
| #define | SDMMC_TRANSFER_MODE_CMD_COMP_ATA_Pos (6UL) |
| |
| #define | SDMMC_TRANSFER_MODE_CMD_COMP_ATA_Msk (0x40UL) |
| |
| #define | SDMMC_COMMAND_RESP_TYPE_SELECT_Pos (0UL) |
| |
| #define | SDMMC_COMMAND_RESP_TYPE_SELECT_Msk (0x3UL) |
| |
| #define | SDMMC_COMMAND_CMD_CRC_CHECK_EN_Pos (3UL) |
| |
| #define | SDMMC_COMMAND_CMD_CRC_CHECK_EN_Msk (0x8UL) |
| |
| #define | SDMMC_COMMAND_CMD_IND_CHECK_EN_Pos (4UL) |
| |
| #define | SDMMC_COMMAND_CMD_IND_CHECK_EN_Msk (0x10UL) |
| |
| #define | SDMMC_COMMAND_DATA_PRESENT_SELECT_Pos (5UL) |
| |
| #define | SDMMC_COMMAND_DATA_PRESENT_SELECT_Msk (0x20UL) |
| |
| #define | SDMMC_COMMAND_CMD_TYPE_Pos (6UL) |
| |
| #define | SDMMC_COMMAND_CMD_TYPE_Msk (0xc0UL) |
| |
| #define | SDMMC_COMMAND_CMD_IND_Pos (8UL) |
| |
| #define | SDMMC_COMMAND_CMD_IND_Msk (0x3f00UL) |
| |
| #define | SDMMC_RESPONSE0_RESPONSE0_Pos (0UL) |
| |
| #define | SDMMC_RESPONSE0_RESPONSE0_Msk (0xffffUL) |
| |
| #define | SDMMC_RESPONSE0_RESPONSE1_Pos (16UL) |
| |
| #define | SDMMC_RESPONSE0_RESPONSE1_Msk (0xffff0000UL) |
| |
| #define | SDMMC_RESPONSE2_RESPONSE2_Pos (0UL) |
| |
| #define | SDMMC_RESPONSE2_RESPONSE2_Msk (0xffffUL) |
| |
| #define | SDMMC_RESPONSE2_RESPONSE3_Pos (16UL) |
| |
| #define | SDMMC_RESPONSE2_RESPONSE3_Msk (0xffff0000UL) |
| |
| #define | SDMMC_RESPONSE4_RESPONSE4_Pos (0UL) |
| |
| #define | SDMMC_RESPONSE4_RESPONSE4_Msk (0xffffUL) |
| |
| #define | SDMMC_RESPONSE4_RESPONSE5_Pos (16UL) |
| |
| #define | SDMMC_RESPONSE4_RESPONSE5_Msk (0xffff0000UL) |
| |
| #define | SDMMC_RESPONSE6_RESPONSE6_Pos (0UL) |
| |
| #define | SDMMC_RESPONSE6_RESPONSE6_Msk (0xffffUL) |
| |
| #define | SDMMC_RESPONSE6_RESPONSE7_Pos (16UL) |
| |
| #define | SDMMC_RESPONSE6_RESPONSE7_Msk (0xffff0000UL) |
| |
| #define | SDMMC_DATA_BUFFER_DATA_BUFFER_Pos (0UL) |
| |
| #define | SDMMC_DATA_BUFFER_DATA_BUFFER_Msk (0xffffffffUL) |
| |
| #define | SDMMC_PRESENT_STATE_COMMAND_INHIBIT_CMD_Pos (0UL) |
| |
| #define | SDMMC_PRESENT_STATE_COMMAND_INHIBIT_CMD_Msk (0x1UL) |
| |
| #define | SDMMC_PRESENT_STATE_COMMAND_INHIBIT_DAT_Pos (1UL) |
| |
| #define | SDMMC_PRESENT_STATE_COMMAND_INHIBIT_DAT_Msk (0x2UL) |
| |
| #define | SDMMC_PRESENT_STATE_DAT_LINE_ACTIVE_Pos (2UL) |
| |
| #define | SDMMC_PRESENT_STATE_DAT_LINE_ACTIVE_Msk (0x4UL) |
| |
| #define | SDMMC_PRESENT_STATE_WRITE_TRANSFER_ACTIVE_Pos (8UL) |
| |
| #define | SDMMC_PRESENT_STATE_WRITE_TRANSFER_ACTIVE_Msk (0x100UL) |
| |
| #define | SDMMC_PRESENT_STATE_READ_TRANSFER_ACTIVE_Pos (9UL) |
| |
| #define | SDMMC_PRESENT_STATE_READ_TRANSFER_ACTIVE_Msk (0x200UL) |
| |
| #define | SDMMC_PRESENT_STATE_BUFFER_WRITE_ENABLE_Pos (10UL) |
| |
| #define | SDMMC_PRESENT_STATE_BUFFER_WRITE_ENABLE_Msk (0x400UL) |
| |
| #define | SDMMC_PRESENT_STATE_BUFFER_READ_ENABLE_Pos (11UL) |
| |
| #define | SDMMC_PRESENT_STATE_BUFFER_READ_ENABLE_Msk (0x800UL) |
| |
| #define | SDMMC_PRESENT_STATE_CARD_INSERTED_Pos (16UL) |
| |
| #define | SDMMC_PRESENT_STATE_CARD_INSERTED_Msk (0x10000UL) |
| |
| #define | SDMMC_PRESENT_STATE_CARD_STATE_STABLE_Pos (17UL) |
| |
| #define | SDMMC_PRESENT_STATE_CARD_STATE_STABLE_Msk (0x20000UL) |
| |
| #define | SDMMC_PRESENT_STATE_CARD_DETECT_PIN_LEVEL_Pos (18UL) |
| |
| #define | SDMMC_PRESENT_STATE_CARD_DETECT_PIN_LEVEL_Msk (0x40000UL) |
| |
| #define | SDMMC_PRESENT_STATE_WRITE_PROTECT_PIN_LEVEL_Pos (19UL) |
| |
| #define | SDMMC_PRESENT_STATE_WRITE_PROTECT_PIN_LEVEL_Msk (0x80000UL) |
| |
| #define | SDMMC_PRESENT_STATE_DAT_3_0_PIN_LEVEL_Pos (20UL) |
| |
| #define | SDMMC_PRESENT_STATE_DAT_3_0_PIN_LEVEL_Msk (0xf00000UL) |
| |
| #define | SDMMC_PRESENT_STATE_CMD_LINE_LEVEL_Pos (24UL) |
| |
| #define | SDMMC_PRESENT_STATE_CMD_LINE_LEVEL_Msk (0x1000000UL) |
| |
| #define | SDMMC_PRESENT_STATE_DAT_7_4_PIN_LEVEL_Pos (25UL) |
| |
| #define | SDMMC_PRESENT_STATE_DAT_7_4_PIN_LEVEL_Msk (0x1e000000UL) |
| |
| #define | SDMMC_HOST_CTRL_LED_CTRL_Pos (0UL) |
| |
| #define | SDMMC_HOST_CTRL_LED_CTRL_Msk (0x1UL) |
| |
| #define | SDMMC_HOST_CTRL_DATA_TX_WIDTH_Pos (1UL) |
| |
| #define | SDMMC_HOST_CTRL_DATA_TX_WIDTH_Msk (0x2UL) |
| |
| #define | SDMMC_HOST_CTRL_HIGH_SPEED_EN_Pos (2UL) |
| |
| #define | SDMMC_HOST_CTRL_HIGH_SPEED_EN_Msk (0x4UL) |
| |
| #define | SDMMC_HOST_CTRL_SD_8BIT_MODE_Pos (5UL) |
| |
| #define | SDMMC_HOST_CTRL_SD_8BIT_MODE_Msk (0x20UL) |
| |
| #define | SDMMC_HOST_CTRL_CARD_DETECT_TEST_LEVEL_Pos (6UL) |
| |
| #define | SDMMC_HOST_CTRL_CARD_DETECT_TEST_LEVEL_Msk (0x40UL) |
| |
| #define | SDMMC_HOST_CTRL_CARD_DET_SIGNAL_DETECT_Pos (7UL) |
| |
| #define | SDMMC_HOST_CTRL_CARD_DET_SIGNAL_DETECT_Msk (0x80UL) |
| |
| #define | SDMMC_POWER_CTRL_SD_BUS_POWER_Pos (0UL) |
| |
| #define | SDMMC_POWER_CTRL_SD_BUS_POWER_Msk (0x1UL) |
| |
| #define | SDMMC_POWER_CTRL_SD_BUS_VOLTAGE_SEL_Pos (1UL) |
| |
| #define | SDMMC_POWER_CTRL_SD_BUS_VOLTAGE_SEL_Msk (0xeUL) |
| |
| #define | SDMMC_POWER_CTRL_HARDWARE_RESET_Pos (4UL) |
| |
| #define | SDMMC_POWER_CTRL_HARDWARE_RESET_Msk (0x10UL) |
| |
| #define | SDMMC_BLOCK_GAP_CTRL_STOP_AT_BLOCK_GAP_Pos (0UL) |
| |
| #define | SDMMC_BLOCK_GAP_CTRL_STOP_AT_BLOCK_GAP_Msk (0x1UL) |
| |
| #define | SDMMC_BLOCK_GAP_CTRL_CONTINUE_REQ_Pos (1UL) |
| |
| #define | SDMMC_BLOCK_GAP_CTRL_CONTINUE_REQ_Msk (0x2UL) |
| |
| #define | SDMMC_BLOCK_GAP_CTRL_READ_WAIT_CTRL_Pos (2UL) |
| |
| #define | SDMMC_BLOCK_GAP_CTRL_READ_WAIT_CTRL_Msk (0x4UL) |
| |
| #define | SDMMC_BLOCK_GAP_CTRL_INT_AT_BLOCK_GAP_Pos (3UL) |
| |
| #define | SDMMC_BLOCK_GAP_CTRL_INT_AT_BLOCK_GAP_Msk (0x8UL) |
| |
| #define | SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INT_Pos (0UL) |
| |
| #define | SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INT_Msk (0x1UL) |
| |
| #define | SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INS_Pos (1UL) |
| |
| #define | SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INS_Msk (0x2UL) |
| |
| #define | SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_REM_Pos (2UL) |
| |
| #define | SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_REM_Msk (0x4UL) |
| |
| #define | SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_EN_Pos (0UL) |
| |
| #define | SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_EN_Msk (0x1UL) |
| |
| #define | SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_STABLE_Pos (1UL) |
| |
| #define | SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_STABLE_Msk (0x2UL) |
| |
| #define | SDMMC_CLOCK_CTRL_SDCLOCK_EN_Pos (2UL) |
| |
| #define | SDMMC_CLOCK_CTRL_SDCLOCK_EN_Msk (0x4UL) |
| |
| #define | SDMMC_CLOCK_CTRL_SDCLK_FREQ_SEL_Pos (8UL) |
| |
| #define | SDMMC_CLOCK_CTRL_SDCLK_FREQ_SEL_Msk (0xff00UL) |
| |
| #define | SDMMC_TIMEOUT_CTRL_DAT_TIMEOUT_CNT_VAL_Pos (0UL) |
| |
| #define | SDMMC_TIMEOUT_CTRL_DAT_TIMEOUT_CNT_VAL_Msk (0xfUL) |
| |
| #define | SDMMC_SW_RESET_SW_RST_ALL_Pos (0UL) |
| |
| #define | SDMMC_SW_RESET_SW_RST_ALL_Msk (0x1UL) |
| |
| #define | SDMMC_SW_RESET_SW_RST_CMD_LINE_Pos (1UL) |
| |
| #define | SDMMC_SW_RESET_SW_RST_CMD_LINE_Msk (0x2UL) |
| |
| #define | SDMMC_SW_RESET_SW_RST_DAT_LINE_Pos (2UL) |
| |
| #define | SDMMC_SW_RESET_SW_RST_DAT_LINE_Msk (0x4UL) |
| |
| #define | SDMMC_INT_STATUS_NORM_CMD_COMPLETE_Pos (0UL) |
| |
| #define | SDMMC_INT_STATUS_NORM_CMD_COMPLETE_Msk (0x1UL) |
| |
| #define | SDMMC_INT_STATUS_NORM_TX_COMPLETE_Pos (1UL) |
| |
| #define | SDMMC_INT_STATUS_NORM_TX_COMPLETE_Msk (0x2UL) |
| |
| #define | SDMMC_INT_STATUS_NORM_BLOCK_GAP_EVENT_Pos (2UL) |
| |
| #define | SDMMC_INT_STATUS_NORM_BLOCK_GAP_EVENT_Msk (0x4UL) |
| |
| #define | SDMMC_INT_STATUS_NORM_BUFF_WRITE_READY_Pos (4UL) |
| |
| #define | SDMMC_INT_STATUS_NORM_BUFF_WRITE_READY_Msk (0x10UL) |
| |
| #define | SDMMC_INT_STATUS_NORM_BUFF_READ_READY_Pos (5UL) |
| |
| #define | SDMMC_INT_STATUS_NORM_BUFF_READ_READY_Msk (0x20UL) |
| |
| #define | SDMMC_INT_STATUS_NORM_CARD_INS_Pos (6UL) |
| |
| #define | SDMMC_INT_STATUS_NORM_CARD_INS_Msk (0x40UL) |
| |
| #define | SDMMC_INT_STATUS_NORM_CARD_REMOVAL_Pos (7UL) |
| |
| #define | SDMMC_INT_STATUS_NORM_CARD_REMOVAL_Msk (0x80UL) |
| |
| #define | SDMMC_INT_STATUS_NORM_CARD_INT_Pos (8UL) |
| |
| #define | SDMMC_INT_STATUS_NORM_CARD_INT_Msk (0x100UL) |
| |
| #define | SDMMC_INT_STATUS_NORM_ERR_INT_Pos (15UL) |
| |
| #define | SDMMC_INT_STATUS_NORM_ERR_INT_Msk (0x8000UL) |
| |
| #define | SDMMC_INT_STATUS_ERR_CMD_TIMEOUT_ERR_Pos (0UL) |
| |
| #define | SDMMC_INT_STATUS_ERR_CMD_TIMEOUT_ERR_Msk (0x1UL) |
| |
| #define | SDMMC_INT_STATUS_ERR_CMD_CRC_ERR_Pos (1UL) |
| |
| #define | SDMMC_INT_STATUS_ERR_CMD_CRC_ERR_Msk (0x2UL) |
| |
| #define | SDMMC_INT_STATUS_ERR_CMD_END_BIT_ERR_Pos (2UL) |
| |
| #define | SDMMC_INT_STATUS_ERR_CMD_END_BIT_ERR_Msk (0x4UL) |
| |
| #define | SDMMC_INT_STATUS_ERR_CMD_IND_ERR_Pos (3UL) |
| |
| #define | SDMMC_INT_STATUS_ERR_CMD_IND_ERR_Msk (0x8UL) |
| |
| #define | SDMMC_INT_STATUS_ERR_DATA_TIMEOUT_ERR_Pos (4UL) |
| |
| #define | SDMMC_INT_STATUS_ERR_DATA_TIMEOUT_ERR_Msk (0x10UL) |
| |
| #define | SDMMC_INT_STATUS_ERR_DATA_CRC_ERR_Pos (5UL) |
| |
| #define | SDMMC_INT_STATUS_ERR_DATA_CRC_ERR_Msk (0x20UL) |
| |
| #define | SDMMC_INT_STATUS_ERR_DATA_END_BIT_ERR_Pos (6UL) |
| |
| #define | SDMMC_INT_STATUS_ERR_DATA_END_BIT_ERR_Msk (0x40UL) |
| |
| #define | SDMMC_INT_STATUS_ERR_CURRENT_LIMIT_ERR_Pos (7UL) |
| |
| #define | SDMMC_INT_STATUS_ERR_CURRENT_LIMIT_ERR_Msk (0x80UL) |
| |
| #define | SDMMC_INT_STATUS_ERR_ACMD_ERR_Pos (8UL) |
| |
| #define | SDMMC_INT_STATUS_ERR_ACMD_ERR_Msk (0x100UL) |
| |
| #define | SDMMC_INT_STATUS_ERR_CEATA_ERR_Pos (13UL) |
| |
| #define | SDMMC_INT_STATUS_ERR_CEATA_ERR_Msk (0x2000UL) |
| |
| #define | SDMMC_EN_INT_STATUS_NORM_CMD_COMPLETE_EN_Pos (0UL) |
| |
| #define | SDMMC_EN_INT_STATUS_NORM_CMD_COMPLETE_EN_Msk (0x1UL) |
| |
| #define | SDMMC_EN_INT_STATUS_NORM_TX_COMPLETE_EN_Pos (1UL) |
| |
| #define | SDMMC_EN_INT_STATUS_NORM_TX_COMPLETE_EN_Msk (0x2UL) |
| |
| #define | SDMMC_EN_INT_STATUS_NORM_BLOCK_GAP_EVENT_EN_Pos (2UL) |
| |
| #define | SDMMC_EN_INT_STATUS_NORM_BLOCK_GAP_EVENT_EN_Msk (0x4UL) |
| |
| #define | SDMMC_EN_INT_STATUS_NORM_BUFF_WRITE_READY_EN_Pos (4UL) |
| |
| #define | SDMMC_EN_INT_STATUS_NORM_BUFF_WRITE_READY_EN_Msk (0x10UL) |
| |
| #define | SDMMC_EN_INT_STATUS_NORM_BUFF_READ_READY_EN_Pos (5UL) |
| |
| #define | SDMMC_EN_INT_STATUS_NORM_BUFF_READ_READY_EN_Msk (0x20UL) |
| |
| #define | SDMMC_EN_INT_STATUS_NORM_CARD_INS_EN_Pos (6UL) |
| |
| #define | SDMMC_EN_INT_STATUS_NORM_CARD_INS_EN_Msk (0x40UL) |
| |
| #define | SDMMC_EN_INT_STATUS_NORM_CARD_REMOVAL_EN_Pos (7UL) |
| |
| #define | SDMMC_EN_INT_STATUS_NORM_CARD_REMOVAL_EN_Msk (0x80UL) |
| |
| #define | SDMMC_EN_INT_STATUS_NORM_CARD_INT_EN_Pos (8UL) |
| |
| #define | SDMMC_EN_INT_STATUS_NORM_CARD_INT_EN_Msk (0x100UL) |
| |
| #define | SDMMC_EN_INT_STATUS_NORM_FIXED_TO_0_Pos (15UL) |
| |
| #define | SDMMC_EN_INT_STATUS_NORM_FIXED_TO_0_Msk (0x8000UL) |
| |
| #define | SDMMC_EN_INT_STATUS_ERR_CMD_TIMEOUT_ERR_EN_Pos (0UL) |
| |
| #define | SDMMC_EN_INT_STATUS_ERR_CMD_TIMEOUT_ERR_EN_Msk (0x1UL) |
| |
| #define | SDMMC_EN_INT_STATUS_ERR_CMD_CRC_ERR_EN_Pos (1UL) |
| |
| #define | SDMMC_EN_INT_STATUS_ERR_CMD_CRC_ERR_EN_Msk (0x2UL) |
| |
| #define | SDMMC_EN_INT_STATUS_ERR_CMD_END_BIT_ERR_EN_Pos (2UL) |
| |
| #define | SDMMC_EN_INT_STATUS_ERR_CMD_END_BIT_ERR_EN_Msk (0x4UL) |
| |
| #define | SDMMC_EN_INT_STATUS_ERR_CMD_IND_ERR_EN_Pos (3UL) |
| |
| #define | SDMMC_EN_INT_STATUS_ERR_CMD_IND_ERR_EN_Msk (0x8UL) |
| |
| #define | SDMMC_EN_INT_STATUS_ERR_DATA_TIMEOUT_ERR_EN_Pos (4UL) |
| |
| #define | SDMMC_EN_INT_STATUS_ERR_DATA_TIMEOUT_ERR_EN_Msk (0x10UL) |
| |
| #define | SDMMC_EN_INT_STATUS_ERR_DATA_CRC_ERR_EN_Pos (5UL) |
| |
| #define | SDMMC_EN_INT_STATUS_ERR_DATA_CRC_ERR_EN_Msk (0x20UL) |
| |
| #define | SDMMC_EN_INT_STATUS_ERR_DATA_END_BIT_ERR_EN_Pos (6UL) |
| |
| #define | SDMMC_EN_INT_STATUS_ERR_DATA_END_BIT_ERR_EN_Msk (0x40UL) |
| |
| #define | SDMMC_EN_INT_STATUS_ERR_CURRENT_LIMIT_ERR_EN_Pos (7UL) |
| |
| #define | SDMMC_EN_INT_STATUS_ERR_CURRENT_LIMIT_ERR_EN_Msk (0x80UL) |
| |
| #define | SDMMC_EN_INT_STATUS_ERR_ACMD_ERR_EN_Pos (8UL) |
| |
| #define | SDMMC_EN_INT_STATUS_ERR_ACMD_ERR_EN_Msk (0x100UL) |
| |
| #define | SDMMC_EN_INT_STATUS_ERR_TARGET_RESP_ERR_EN_Pos (12UL) |
| |
| #define | SDMMC_EN_INT_STATUS_ERR_TARGET_RESP_ERR_EN_Msk (0x1000UL) |
| |
| #define | SDMMC_EN_INT_STATUS_ERR_CEATA_ERR_EN_Pos (13UL) |
| |
| #define | SDMMC_EN_INT_STATUS_ERR_CEATA_ERR_EN_Msk (0x2000UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_NORM_CMD_COMPLETE_EN_Pos (0UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_NORM_CMD_COMPLETE_EN_Msk (0x1UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_NORM_TX_COMPLETE_EN_Pos (1UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_NORM_TX_COMPLETE_EN_Msk (0x2UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_NORM_BLOCK_GAP_EVENT_EN_Pos (2UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_NORM_BLOCK_GAP_EVENT_EN_Msk (0x4UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_NORM_BUFF_WRITE_READY_EN_Pos (4UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_NORM_BUFF_WRITE_READY_EN_Msk (0x10UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_NORM_BUFF_READ_READY_EN_Pos (5UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_NORM_BUFF_READ_READY_EN_Msk (0x20UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_NORM_CARD_INS_EN_Pos (6UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_NORM_CARD_INS_EN_Msk (0x40UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_NORM_CARD_REMOVAL_EN_Pos (7UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_NORM_CARD_REMOVAL_EN_Msk (0x80UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_NORM_CARD_INT_EN_Pos (8UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_NORM_CARD_INT_EN_Msk (0x100UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_NORM_FIXED_TO_0_Pos (15UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_NORM_FIXED_TO_0_Msk (0x8000UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_ERR_CMD_TIMEOUT_ERR_EN_Pos (0UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_ERR_CMD_TIMEOUT_ERR_EN_Msk (0x1UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_ERR_CMD_CRC_ERR_EN_Pos (1UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_ERR_CMD_CRC_ERR_EN_Msk (0x2UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_ERR_CMD_END_BIT_ERR_EN_Pos (2UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_ERR_CMD_END_BIT_ERR_EN_Msk (0x4UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_ERR_CMD_IND_ERR_EN_Pos (3UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_ERR_CMD_IND_ERR_EN_Msk (0x8UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_ERR_DATA_TIMEOUT_ERR_EN_Pos (4UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_ERR_DATA_TIMEOUT_ERR_EN_Msk (0x10UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_ERR_DATA_CRC_ERR_EN_Pos (5UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_ERR_DATA_CRC_ERR_EN_Msk (0x20UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_ERR_DATA_END_BIT_ERR_EN_Pos (6UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_ERR_DATA_END_BIT_ERR_EN_Msk (0x40UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_ERR_CURRENT_LIMIT_ERR_EN_Pos (7UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_ERR_CURRENT_LIMIT_ERR_EN_Msk (0x80UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_ERR_ACMD_ERR_EN_Pos (8UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_ERR_ACMD_ERR_EN_Msk (0x100UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_ERR_TARGET_RESP_ERR_EN_Pos (12UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_ERR_TARGET_RESP_ERR_EN_Msk (0x1000UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_ERR_CEATA_ERR_EN_Pos (13UL) |
| |
| #define | SDMMC_EN_INT_SIGNAL_ERR_CEATA_ERR_EN_Msk (0x2000UL) |
| |
| #define | SDMMC_ACMD_ERR_STATUS_ACMD12_NOT_EXEC_ERR_Pos (0UL) |
| |
| #define | SDMMC_ACMD_ERR_STATUS_ACMD12_NOT_EXEC_ERR_Msk (0x1UL) |
| |
| #define | SDMMC_ACMD_ERR_STATUS_ACMD_TIMEOUT_ERR_Pos (1UL) |
| |
| #define | SDMMC_ACMD_ERR_STATUS_ACMD_TIMEOUT_ERR_Msk (0x2UL) |
| |
| #define | SDMMC_ACMD_ERR_STATUS_ACMD_CRC_ERR_Pos (2UL) |
| |
| #define | SDMMC_ACMD_ERR_STATUS_ACMD_CRC_ERR_Msk (0x4UL) |
| |
| #define | SDMMC_ACMD_ERR_STATUS_ACMD_END_BIT_ERR_Pos (3UL) |
| |
| #define | SDMMC_ACMD_ERR_STATUS_ACMD_END_BIT_ERR_Msk (0x8UL) |
| |
| #define | SDMMC_ACMD_ERR_STATUS_ACMD_IND_ERR_Pos (4UL) |
| |
| #define | SDMMC_ACMD_ERR_STATUS_ACMD_IND_ERR_Msk (0x10UL) |
| |
| #define | SDMMC_ACMD_ERR_STATUS_CMD_NOT_ISSUED_BY_ACMD12_ERR_Pos (7UL) |
| |
| #define | SDMMC_ACMD_ERR_STATUS_CMD_NOT_ISSUED_BY_ACMD12_ERR_Msk (0x80UL) |
| |
| #define | SDMMC_CAPABILITIES_TIMEOUT_CLOCK_FREQ_Pos (0UL) |
| |
| #define | SDMMC_CAPABILITIES_TIMEOUT_CLOCK_FREQ_Msk (0x3fUL) |
| |
| #define | SDMMC_CAPABILITIES_TIMEOUT_CLOCK_UNIT_Pos (7UL) |
| |
| #define | SDMMC_CAPABILITIES_TIMEOUT_CLOCK_UNIT_Msk (0x80UL) |
| |
| #define | SDMMC_CAPABILITIES_BASE_SD_CLOCK_FREQ_Pos (8UL) |
| |
| #define | SDMMC_CAPABILITIES_BASE_SD_CLOCK_FREQ_Msk (0xff00UL) |
| |
| #define | SDMMC_CAPABILITIES_MAX_BLOCK_LENGTH_Pos (16UL) |
| |
| #define | SDMMC_CAPABILITIES_MAX_BLOCK_LENGTH_Msk (0x30000UL) |
| |
| #define | SDMMC_CAPABILITIES_EXT_MEDIA_BUS_SUPPORT_Pos (18UL) |
| |
| #define | SDMMC_CAPABILITIES_EXT_MEDIA_BUS_SUPPORT_Msk (0x40000UL) |
| |
| #define | SDMMC_CAPABILITIES_ADMA2_SUPPORT_Pos (19UL) |
| |
| #define | SDMMC_CAPABILITIES_ADMA2_SUPPORT_Msk (0x80000UL) |
| |
| #define | SDMMC_CAPABILITIES_HIGH_SPEED_SUPPORT_Pos (21UL) |
| |
| #define | SDMMC_CAPABILITIES_HIGH_SPEED_SUPPORT_Msk (0x200000UL) |
| |
| #define | SDMMC_CAPABILITIES_SDMA_SUPPORT_Pos (22UL) |
| |
| #define | SDMMC_CAPABILITIES_SDMA_SUPPORT_Msk (0x400000UL) |
| |
| #define | SDMMC_CAPABILITIES_SUSPEND_RESUME_SUPPORT_Pos (23UL) |
| |
| #define | SDMMC_CAPABILITIES_SUSPEND_RESUME_SUPPORT_Msk (0x800000UL) |
| |
| #define | SDMMC_CAPABILITIES_VOLTAGE_SUPPORT_3_3V_Pos (24UL) |
| |
| #define | SDMMC_CAPABILITIES_VOLTAGE_SUPPORT_3_3V_Msk (0x1000000UL) |
| |
| #define | SDMMC_CAPABILITIES_VOLTAGE_SUPPORT_3V_Pos (25UL) |
| |
| #define | SDMMC_CAPABILITIES_VOLTAGE_SUPPORT_3V_Msk (0x2000000UL) |
| |
| #define | SDMMC_CAPABILITIES_VOLTAGE_SUPPORT_1_8V_Pos (26UL) |
| |
| #define | SDMMC_CAPABILITIES_VOLTAGE_SUPPORT_1_8V_Msk (0x4000000UL) |
| |
| #define | SDMMC_CAPABILITIES_SYSBUS_64_SUPPORT_Pos (28UL) |
| |
| #define | SDMMC_CAPABILITIES_SYSBUS_64_SUPPORT_Msk (0x10000000UL) |
| |
| #define | SDMMC_CAPABILITIES_ASYNC_INT_SUPPORT_Pos (29UL) |
| |
| #define | SDMMC_CAPABILITIES_ASYNC_INT_SUPPORT_Msk (0x20000000UL) |
| |
| #define | SDMMC_CAPABILITIES_SLOT_TYPE_Pos (30UL) |
| |
| #define | SDMMC_CAPABILITIES_SLOT_TYPE_Msk (0xc0000000UL) |
| |
| #define | SDMMC_CAPABILITIES_HI_SDR50_SUPPORT_Pos (0UL) |
| |
| #define | SDMMC_CAPABILITIES_HI_SDR50_SUPPORT_Msk (0x1UL) |
| |
| #define | SDMMC_CAPABILITIES_HI_SDR104_SUPPORT_Pos (1UL) |
| |
| #define | SDMMC_CAPABILITIES_HI_SDR104_SUPPORT_Msk (0x2UL) |
| |
| #define | SDMMC_CAPABILITIES_HI_DDR50_SUPPORT_Pos (2UL) |
| |
| #define | SDMMC_CAPABILITIES_HI_DDR50_SUPPORT_Msk (0x4UL) |
| |
| #define | SDMMC_CAPABILITIES_HI_DRV_A_SUPPORT_Pos (4UL) |
| |
| #define | SDMMC_CAPABILITIES_HI_DRV_A_SUPPORT_Msk (0x10UL) |
| |
| #define | SDMMC_CAPABILITIES_HI_DRV_C_SUPPORT_Pos (5UL) |
| |
| #define | SDMMC_CAPABILITIES_HI_DRV_C_SUPPORT_Msk (0x20UL) |
| |
| #define | SDMMC_CAPABILITIES_HI_DRV_D_SUPPORT_Pos (6UL) |
| |
| #define | SDMMC_CAPABILITIES_HI_DRV_D_SUPPORT_Msk (0x40UL) |
| |
| #define | SDMMC_CAPABILITIES_HI_TIM_CNT_RETUNE_Pos (8UL) |
| |
| #define | SDMMC_CAPABILITIES_HI_TIM_CNT_RETUNE_Msk (0xf00UL) |
| |
| #define | SDMMC_CAPABILITIES_HI_USE_TUNING_SDR50_Pos (13UL) |
| |
| #define | SDMMC_CAPABILITIES_HI_USE_TUNING_SDR50_Msk (0x2000UL) |
| |
| #define | SDMMC_CAPABILITIES_HI_RE_TUNING_MODES_Pos (14UL) |
| |
| #define | SDMMC_CAPABILITIES_HI_RE_TUNING_MODES_Msk (0xc000UL) |
| |
| #define | SDMMC_CAPABILITIES_HI_CLK_MULT_Pos (16UL) |
| |
| #define | SDMMC_CAPABILITIES_HI_CLK_MULT_Msk (0xff0000UL) |
| |
| #define | SDMMC_MAX_CURRENT_CAP_MAX_CURRENT_FOR_3_3V_Pos (0UL) |
| |
| #define | SDMMC_MAX_CURRENT_CAP_MAX_CURRENT_FOR_3_3V_Msk (0xffUL) |
| |
| #define | SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_NOT_EXEC_Pos (0UL) |
| |
| #define | SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_NOT_EXEC_Msk (0x1UL) |
| |
| #define | SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_TIMEOUT_ERR_Pos (1UL) |
| |
| #define | SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_TIMEOUT_ERR_Msk (0x2UL) |
| |
| #define | SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_CRC_ERR_Pos (2UL) |
| |
| #define | SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_CRC_ERR_Msk (0x4UL) |
| |
| #define | SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_END_BIT_ERR_Pos (3UL) |
| |
| #define | SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_END_BIT_ERR_Msk (0x8UL) |
| |
| #define | SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_IND_ERR_Pos (4UL) |
| |
| #define | SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_IND_ERR_Msk (0x10UL) |
| |
| #define | SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_CMD_NOT_ISSUED_ACMD12_ERR_Pos (7UL) |
| |
| #define | SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_CMD_NOT_ISSUED_ACMD12_ERR_Msk (0x80UL) |
| |
| #define | SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_TIMEOUT_ERR_Pos (0UL) |
| |
| #define | SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_TIMEOUT_ERR_Msk (0x1UL) |
| |
| #define | SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_CRC_ERR_Pos (1UL) |
| |
| #define | SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_CRC_ERR_Msk (0x2UL) |
| |
| #define | SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_END_BIT_ERR_Pos (2UL) |
| |
| #define | SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_END_BIT_ERR_Msk (0x4UL) |
| |
| #define | SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_IND_ERR_Pos (3UL) |
| |
| #define | SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_IND_ERR_Msk (0x8UL) |
| |
| #define | SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_TIMEOUT_ERR_Pos (4UL) |
| |
| #define | SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_TIMEOUT_ERR_Msk (0x10UL) |
| |
| #define | SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_CRC_ERR_Pos (5UL) |
| |
| #define | SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_CRC_ERR_Msk (0x20UL) |
| |
| #define | SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_END_BIT_ERR_Pos (6UL) |
| |
| #define | SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_END_BIT_ERR_Msk (0x40UL) |
| |
| #define | SDMMC_FORCE_EVENT_ERR_STATUS_FE_CURRENT_LIMIT_ERR_Pos (7UL) |
| |
| #define | SDMMC_FORCE_EVENT_ERR_STATUS_FE_CURRENT_LIMIT_ERR_Msk (0x80UL) |
| |
| #define | SDMMC_FORCE_EVENT_ERR_STATUS_FE_ACMD12_ERR_Pos (8UL) |
| |
| #define | SDMMC_FORCE_EVENT_ERR_STATUS_FE_ACMD12_ERR_Msk (0x100UL) |
| |
| #define | SDMMC_FORCE_EVENT_ERR_STATUS_FE_TARGET_RESPONSE_ERR_Pos (12UL) |
| |
| #define | SDMMC_FORCE_EVENT_ERR_STATUS_FE_TARGET_RESPONSE_ERR_Msk (0x1000UL) |
| |
| #define | SDMMC_FORCE_EVENT_ERR_STATUS_FE_CEATA_ERR_Pos (13UL) |
| |
| #define | SDMMC_FORCE_EVENT_ERR_STATUS_FE_CEATA_ERR_Msk (0x2000UL) |
| |
| #define | SDMMC_DEBUG_SEL_DEBUG_SEL_Pos (0UL) |
| |
| #define | SDMMC_DEBUG_SEL_DEBUG_SEL_Msk (0x1UL) |
| |
| #define | SDMMC_SLOT_INT_STATUS_SLOT_INT_STATUS_Pos (0UL) |
| |
| #define | SDMMC_SLOT_INT_STATUS_SLOT_INT_STATUS_Msk (0xffUL) |
| |
| #define | EBU_CLC_DISR_Pos (0UL) |
| |
| #define | EBU_CLC_DISR_Msk (0x1UL) |
| |
| #define | EBU_CLC_DISS_Pos (1UL) |
| |
| #define | EBU_CLC_DISS_Msk (0x2UL) |
| |
| #define | EBU_CLC_SYNC_Pos (16UL) |
| |
| #define | EBU_CLC_SYNC_Msk (0x10000UL) |
| |
| #define | EBU_CLC_DIV2_Pos (17UL) |
| |
| #define | EBU_CLC_DIV2_Msk (0x20000UL) |
| |
| #define | EBU_CLC_EBUDIV_Pos (18UL) |
| |
| #define | EBU_CLC_EBUDIV_Msk (0xc0000UL) |
| |
| #define | EBU_CLC_SYNCACK_Pos (20UL) |
| |
| #define | EBU_CLC_SYNCACK_Msk (0x100000UL) |
| |
| #define | EBU_CLC_DIV2ACK_Pos (21UL) |
| |
| #define | EBU_CLC_DIV2ACK_Msk (0x200000UL) |
| |
| #define | EBU_CLC_EBUDIVACK_Pos (22UL) |
| |
| #define | EBU_CLC_EBUDIVACK_Msk (0xc00000UL) |
| |
| #define | EBU_MODCON_STS_Pos (0UL) |
| |
| #define | EBU_MODCON_STS_Msk (0x1UL) |
| |
| #define | EBU_MODCON_LCKABRT_Pos (1UL) |
| |
| #define | EBU_MODCON_LCKABRT_Msk (0x2UL) |
| |
| #define | EBU_MODCON_SDTRI_Pos (2UL) |
| |
| #define | EBU_MODCON_SDTRI_Msk (0x4UL) |
| |
| #define | EBU_MODCON_EXTLOCK_Pos (4UL) |
| |
| #define | EBU_MODCON_EXTLOCK_Msk (0x10UL) |
| |
| #define | EBU_MODCON_ARBSYNC_Pos (5UL) |
| |
| #define | EBU_MODCON_ARBSYNC_Msk (0x20UL) |
| |
| #define | EBU_MODCON_ARBMODE_Pos (6UL) |
| |
| #define | EBU_MODCON_ARBMODE_Msk (0xc0UL) |
| |
| #define | EBU_MODCON_TIMEOUTC_Pos (8UL) |
| |
| #define | EBU_MODCON_TIMEOUTC_Msk (0xff00UL) |
| |
| #define | EBU_MODCON_LOCKTIMEOUT_Pos (16UL) |
| |
| #define | EBU_MODCON_LOCKTIMEOUT_Msk (0xff0000UL) |
| |
| #define | EBU_MODCON_GLOBALCS_Pos (24UL) |
| |
| #define | EBU_MODCON_GLOBALCS_Msk (0xf000000UL) |
| |
| #define | EBU_MODCON_ACCSINH_Pos (28UL) |
| |
| #define | EBU_MODCON_ACCSINH_Msk (0x10000000UL) |
| |
| #define | EBU_MODCON_ACCSINHACK_Pos (29UL) |
| |
| #define | EBU_MODCON_ACCSINHACK_Msk (0x20000000UL) |
| |
| #define | EBU_MODCON_ALE_Pos (31UL) |
| |
| #define | EBU_MODCON_ALE_Msk (0x80000000UL) |
| |
| #define | EBU_ID_MOD_REV_Pos (0UL) |
| |
| #define | EBU_ID_MOD_REV_Msk (0xffUL) |
| |
| #define | EBU_ID_MOD_TYPE_Pos (8UL) |
| |
| #define | EBU_ID_MOD_TYPE_Msk (0xff00UL) |
| |
| #define | EBU_ID_MOD_NUMBER_Pos (16UL) |
| |
| #define | EBU_ID_MOD_NUMBER_Msk (0xffff0000UL) |
| |
| #define | EBU_USERCON_DIP_Pos (0UL) |
| |
| #define | EBU_USERCON_DIP_Msk (0x1UL) |
| |
| #define | EBU_USERCON_ADDIO_Pos (16UL) |
| |
| #define | EBU_USERCON_ADDIO_Msk (0x1ff0000UL) |
| |
| #define | EBU_USERCON_ADVIO_Pos (25UL) |
| |
| #define | EBU_USERCON_ADVIO_Msk (0x2000000UL) |
| |
| #define | EBU_ADDRSEL0_REGENAB_Pos (0UL) |
| |
| #define | EBU_ADDRSEL0_REGENAB_Msk (0x1UL) |
| |
| #define | EBU_ADDRSEL0_ALTENAB_Pos (1UL) |
| |
| #define | EBU_ADDRSEL0_ALTENAB_Msk (0x2UL) |
| |
| #define | EBU_ADDRSEL0_WPROT_Pos (2UL) |
| |
| #define | EBU_ADDRSEL0_WPROT_Msk (0x4UL) |
| |
| #define | EBU_ADDRSEL1_REGENAB_Pos (0UL) |
| |
| #define | EBU_ADDRSEL1_REGENAB_Msk (0x1UL) |
| |
| #define | EBU_ADDRSEL1_ALTENAB_Pos (1UL) |
| |
| #define | EBU_ADDRSEL1_ALTENAB_Msk (0x2UL) |
| |
| #define | EBU_ADDRSEL1_WPROT_Pos (2UL) |
| |
| #define | EBU_ADDRSEL1_WPROT_Msk (0x4UL) |
| |
| #define | EBU_ADDRSEL2_REGENAB_Pos (0UL) |
| |
| #define | EBU_ADDRSEL2_REGENAB_Msk (0x1UL) |
| |
| #define | EBU_ADDRSEL2_ALTENAB_Pos (1UL) |
| |
| #define | EBU_ADDRSEL2_ALTENAB_Msk (0x2UL) |
| |
| #define | EBU_ADDRSEL2_WPROT_Pos (2UL) |
| |
| #define | EBU_ADDRSEL2_WPROT_Msk (0x4UL) |
| |
| #define | EBU_ADDRSEL3_REGENAB_Pos (0UL) |
| |
| #define | EBU_ADDRSEL3_REGENAB_Msk (0x1UL) |
| |
| #define | EBU_ADDRSEL3_ALTENAB_Pos (1UL) |
| |
| #define | EBU_ADDRSEL3_ALTENAB_Msk (0x2UL) |
| |
| #define | EBU_ADDRSEL3_WPROT_Pos (2UL) |
| |
| #define | EBU_ADDRSEL3_WPROT_Msk (0x4UL) |
| |
| #define | EBU_BUSRCON0_FETBLEN_Pos (0UL) |
| |
| #define | EBU_BUSRCON0_FETBLEN_Msk (0x7UL) |
| |
| #define | EBU_BUSRCON0_FBBMSEL_Pos (3UL) |
| |
| #define | EBU_BUSRCON0_FBBMSEL_Msk (0x8UL) |
| |
| #define | EBU_BUSRCON0_BFSSS_Pos (4UL) |
| |
| #define | EBU_BUSRCON0_BFSSS_Msk (0x10UL) |
| |
| #define | EBU_BUSRCON0_FDBKEN_Pos (5UL) |
| |
| #define | EBU_BUSRCON0_FDBKEN_Msk (0x20UL) |
| |
| #define | EBU_BUSRCON0_BFCMSEL_Pos (6UL) |
| |
| #define | EBU_BUSRCON0_BFCMSEL_Msk (0x40UL) |
| |
| #define | EBU_BUSRCON0_NAA_Pos (7UL) |
| |
| #define | EBU_BUSRCON0_NAA_Msk (0x80UL) |
| |
| #define | EBU_BUSRCON0_ECSE_Pos (16UL) |
| |
| #define | EBU_BUSRCON0_ECSE_Msk (0x10000UL) |
| |
| #define | EBU_BUSRCON0_EBSE_Pos (17UL) |
| |
| #define | EBU_BUSRCON0_EBSE_Msk (0x20000UL) |
| |
| #define | EBU_BUSRCON0_DBA_Pos (18UL) |
| |
| #define | EBU_BUSRCON0_DBA_Msk (0x40000UL) |
| |
| #define | EBU_BUSRCON0_WAITINV_Pos (19UL) |
| |
| #define | EBU_BUSRCON0_WAITINV_Msk (0x80000UL) |
| |
| #define | EBU_BUSRCON0_BCGEN_Pos (20UL) |
| |
| #define | EBU_BUSRCON0_BCGEN_Msk (0x300000UL) |
| |
| #define | EBU_BUSRCON0_PORTW_Pos (22UL) |
| |
| #define | EBU_BUSRCON0_PORTW_Msk (0xc00000UL) |
| |
| #define | EBU_BUSRCON0_WAIT_Pos (24UL) |
| |
| #define | EBU_BUSRCON0_WAIT_Msk (0x3000000UL) |
| |
| #define | EBU_BUSRCON0_AAP_Pos (26UL) |
| |
| #define | EBU_BUSRCON0_AAP_Msk (0x4000000UL) |
| |
| #define | EBU_BUSRCON0_AGEN_Pos (28UL) |
| |
| #define | EBU_BUSRCON0_AGEN_Msk (0xf0000000UL) |
| |
| #define | EBU_BUSRAP0_RDDTACS_Pos (0UL) |
| |
| #define | EBU_BUSRAP0_RDDTACS_Msk (0xfUL) |
| |
| #define | EBU_BUSRAP0_RDRECOVC_Pos (4UL) |
| |
| #define | EBU_BUSRAP0_RDRECOVC_Msk (0x70UL) |
| |
| #define | EBU_BUSRAP0_WAITRDC_Pos (7UL) |
| |
| #define | EBU_BUSRAP0_WAITRDC_Msk (0xf80UL) |
| |
| #define | EBU_BUSRAP0_DATAC_Pos (12UL) |
| |
| #define | EBU_BUSRAP0_DATAC_Msk (0xf000UL) |
| |
| #define | EBU_BUSRAP0_EXTCLOCK_Pos (16UL) |
| |
| #define | EBU_BUSRAP0_EXTCLOCK_Msk (0x30000UL) |
| |
| #define | EBU_BUSRAP0_EXTDATA_Pos (18UL) |
| |
| #define | EBU_BUSRAP0_EXTDATA_Msk (0xc0000UL) |
| |
| #define | EBU_BUSRAP0_CMDDELAY_Pos (20UL) |
| |
| #define | EBU_BUSRAP0_CMDDELAY_Msk (0xf00000UL) |
| |
| #define | EBU_BUSRAP0_AHOLDC_Pos (24UL) |
| |
| #define | EBU_BUSRAP0_AHOLDC_Msk (0xf000000UL) |
| |
| #define | EBU_BUSRAP0_ADDRC_Pos (28UL) |
| |
| #define | EBU_BUSRAP0_ADDRC_Msk (0xf0000000UL) |
| |
| #define | EBU_BUSWCON0_FETBLEN_Pos (0UL) |
| |
| #define | EBU_BUSWCON0_FETBLEN_Msk (0x7UL) |
| |
| #define | EBU_BUSWCON0_FBBMSEL_Pos (3UL) |
| |
| #define | EBU_BUSWCON0_FBBMSEL_Msk (0x8UL) |
| |
| #define | EBU_BUSWCON0_NAA_Pos (7UL) |
| |
| #define | EBU_BUSWCON0_NAA_Msk (0x80UL) |
| |
| #define | EBU_BUSWCON0_ECSE_Pos (16UL) |
| |
| #define | EBU_BUSWCON0_ECSE_Msk (0x10000UL) |
| |
| #define | EBU_BUSWCON0_EBSE_Pos (17UL) |
| |
| #define | EBU_BUSWCON0_EBSE_Msk (0x20000UL) |
| |
| #define | EBU_BUSWCON0_WAITINV_Pos (19UL) |
| |
| #define | EBU_BUSWCON0_WAITINV_Msk (0x80000UL) |
| |
| #define | EBU_BUSWCON0_BCGEN_Pos (20UL) |
| |
| #define | EBU_BUSWCON0_BCGEN_Msk (0x300000UL) |
| |
| #define | EBU_BUSWCON0_PORTW_Pos (22UL) |
| |
| #define | EBU_BUSWCON0_PORTW_Msk (0xc00000UL) |
| |
| #define | EBU_BUSWCON0_WAIT_Pos (24UL) |
| |
| #define | EBU_BUSWCON0_WAIT_Msk (0x3000000UL) |
| |
| #define | EBU_BUSWCON0_AAP_Pos (26UL) |
| |
| #define | EBU_BUSWCON0_AAP_Msk (0x4000000UL) |
| |
| #define | EBU_BUSWCON0_LOCKCS_Pos (27UL) |
| |
| #define | EBU_BUSWCON0_LOCKCS_Msk (0x8000000UL) |
| |
| #define | EBU_BUSWCON0_AGEN_Pos (28UL) |
| |
| #define | EBU_BUSWCON0_AGEN_Msk (0xf0000000UL) |
| |
| #define | EBU_BUSWAP0_WRDTACS_Pos (0UL) |
| |
| #define | EBU_BUSWAP0_WRDTACS_Msk (0xfUL) |
| |
| #define | EBU_BUSWAP0_WRRECOVC_Pos (4UL) |
| |
| #define | EBU_BUSWAP0_WRRECOVC_Msk (0x70UL) |
| |
| #define | EBU_BUSWAP0_WAITWRC_Pos (7UL) |
| |
| #define | EBU_BUSWAP0_WAITWRC_Msk (0xf80UL) |
| |
| #define | EBU_BUSWAP0_DATAC_Pos (12UL) |
| |
| #define | EBU_BUSWAP0_DATAC_Msk (0xf000UL) |
| |
| #define | EBU_BUSWAP0_EXTCLOCK_Pos (16UL) |
| |
| #define | EBU_BUSWAP0_EXTCLOCK_Msk (0x30000UL) |
| |
| #define | EBU_BUSWAP0_EXTDATA_Pos (18UL) |
| |
| #define | EBU_BUSWAP0_EXTDATA_Msk (0xc0000UL) |
| |
| #define | EBU_BUSWAP0_CMDDELAY_Pos (20UL) |
| |
| #define | EBU_BUSWAP0_CMDDELAY_Msk (0xf00000UL) |
| |
| #define | EBU_BUSWAP0_AHOLDC_Pos (24UL) |
| |
| #define | EBU_BUSWAP0_AHOLDC_Msk (0xf000000UL) |
| |
| #define | EBU_BUSWAP0_ADDRC_Pos (28UL) |
| |
| #define | EBU_BUSWAP0_ADDRC_Msk (0xf0000000UL) |
| |
| #define | EBU_BUSRCON1_FETBLEN_Pos (0UL) |
| |
| #define | EBU_BUSRCON1_FETBLEN_Msk (0x7UL) |
| |
| #define | EBU_BUSRCON1_FBBMSEL_Pos (3UL) |
| |
| #define | EBU_BUSRCON1_FBBMSEL_Msk (0x8UL) |
| |
| #define | EBU_BUSRCON1_BFSSS_Pos (4UL) |
| |
| #define | EBU_BUSRCON1_BFSSS_Msk (0x10UL) |
| |
| #define | EBU_BUSRCON1_FDBKEN_Pos (5UL) |
| |
| #define | EBU_BUSRCON1_FDBKEN_Msk (0x20UL) |
| |
| #define | EBU_BUSRCON1_BFCMSEL_Pos (6UL) |
| |
| #define | EBU_BUSRCON1_BFCMSEL_Msk (0x40UL) |
| |
| #define | EBU_BUSRCON1_NAA_Pos (7UL) |
| |
| #define | EBU_BUSRCON1_NAA_Msk (0x80UL) |
| |
| #define | EBU_BUSRCON1_ECSE_Pos (16UL) |
| |
| #define | EBU_BUSRCON1_ECSE_Msk (0x10000UL) |
| |
| #define | EBU_BUSRCON1_EBSE_Pos (17UL) |
| |
| #define | EBU_BUSRCON1_EBSE_Msk (0x20000UL) |
| |
| #define | EBU_BUSRCON1_DBA_Pos (18UL) |
| |
| #define | EBU_BUSRCON1_DBA_Msk (0x40000UL) |
| |
| #define | EBU_BUSRCON1_WAITINV_Pos (19UL) |
| |
| #define | EBU_BUSRCON1_WAITINV_Msk (0x80000UL) |
| |
| #define | EBU_BUSRCON1_BCGEN_Pos (20UL) |
| |
| #define | EBU_BUSRCON1_BCGEN_Msk (0x300000UL) |
| |
| #define | EBU_BUSRCON1_PORTW_Pos (22UL) |
| |
| #define | EBU_BUSRCON1_PORTW_Msk (0xc00000UL) |
| |
| #define | EBU_BUSRCON1_WAIT_Pos (24UL) |
| |
| #define | EBU_BUSRCON1_WAIT_Msk (0x3000000UL) |
| |
| #define | EBU_BUSRCON1_AAP_Pos (26UL) |
| |
| #define | EBU_BUSRCON1_AAP_Msk (0x4000000UL) |
| |
| #define | EBU_BUSRCON1_AGEN_Pos (28UL) |
| |
| #define | EBU_BUSRCON1_AGEN_Msk (0xf0000000UL) |
| |
| #define | EBU_BUSRAP1_RDDTACS_Pos (0UL) |
| |
| #define | EBU_BUSRAP1_RDDTACS_Msk (0xfUL) |
| |
| #define | EBU_BUSRAP1_RDRECOVC_Pos (4UL) |
| |
| #define | EBU_BUSRAP1_RDRECOVC_Msk (0x70UL) |
| |
| #define | EBU_BUSRAP1_WAITRDC_Pos (7UL) |
| |
| #define | EBU_BUSRAP1_WAITRDC_Msk (0xf80UL) |
| |
| #define | EBU_BUSRAP1_DATAC_Pos (12UL) |
| |
| #define | EBU_BUSRAP1_DATAC_Msk (0xf000UL) |
| |
| #define | EBU_BUSRAP1_EXTCLOCK_Pos (16UL) |
| |
| #define | EBU_BUSRAP1_EXTCLOCK_Msk (0x30000UL) |
| |
| #define | EBU_BUSRAP1_EXTDATA_Pos (18UL) |
| |
| #define | EBU_BUSRAP1_EXTDATA_Msk (0xc0000UL) |
| |
| #define | EBU_BUSRAP1_CMDDELAY_Pos (20UL) |
| |
| #define | EBU_BUSRAP1_CMDDELAY_Msk (0xf00000UL) |
| |
| #define | EBU_BUSRAP1_AHOLDC_Pos (24UL) |
| |
| #define | EBU_BUSRAP1_AHOLDC_Msk (0xf000000UL) |
| |
| #define | EBU_BUSRAP1_ADDRC_Pos (28UL) |
| |
| #define | EBU_BUSRAP1_ADDRC_Msk (0xf0000000UL) |
| |
| #define | EBU_BUSWCON1_FETBLEN_Pos (0UL) |
| |
| #define | EBU_BUSWCON1_FETBLEN_Msk (0x7UL) |
| |
| #define | EBU_BUSWCON1_FBBMSEL_Pos (3UL) |
| |
| #define | EBU_BUSWCON1_FBBMSEL_Msk (0x8UL) |
| |
| #define | EBU_BUSWCON1_NAA_Pos (7UL) |
| |
| #define | EBU_BUSWCON1_NAA_Msk (0x80UL) |
| |
| #define | EBU_BUSWCON1_ECSE_Pos (16UL) |
| |
| #define | EBU_BUSWCON1_ECSE_Msk (0x10000UL) |
| |
| #define | EBU_BUSWCON1_EBSE_Pos (17UL) |
| |
| #define | EBU_BUSWCON1_EBSE_Msk (0x20000UL) |
| |
| #define | EBU_BUSWCON1_WAITINV_Pos (19UL) |
| |
| #define | EBU_BUSWCON1_WAITINV_Msk (0x80000UL) |
| |
| #define | EBU_BUSWCON1_BCGEN_Pos (20UL) |
| |
| #define | EBU_BUSWCON1_BCGEN_Msk (0x300000UL) |
| |
| #define | EBU_BUSWCON1_PORTW_Pos (22UL) |
| |
| #define | EBU_BUSWCON1_PORTW_Msk (0xc00000UL) |
| |
| #define | EBU_BUSWCON1_WAIT_Pos (24UL) |
| |
| #define | EBU_BUSWCON1_WAIT_Msk (0x3000000UL) |
| |
| #define | EBU_BUSWCON1_AAP_Pos (26UL) |
| |
| #define | EBU_BUSWCON1_AAP_Msk (0x4000000UL) |
| |
| #define | EBU_BUSWCON1_LOCKCS_Pos (27UL) |
| |
| #define | EBU_BUSWCON1_LOCKCS_Msk (0x8000000UL) |
| |
| #define | EBU_BUSWCON1_AGEN_Pos (28UL) |
| |
| #define | EBU_BUSWCON1_AGEN_Msk (0xf0000000UL) |
| |
| #define | EBU_BUSWAP1_WRDTACS_Pos (0UL) |
| |
| #define | EBU_BUSWAP1_WRDTACS_Msk (0xfUL) |
| |
| #define | EBU_BUSWAP1_WRRECOVC_Pos (4UL) |
| |
| #define | EBU_BUSWAP1_WRRECOVC_Msk (0x70UL) |
| |
| #define | EBU_BUSWAP1_WAITWRC_Pos (7UL) |
| |
| #define | EBU_BUSWAP1_WAITWRC_Msk (0xf80UL) |
| |
| #define | EBU_BUSWAP1_DATAC_Pos (12UL) |
| |
| #define | EBU_BUSWAP1_DATAC_Msk (0xf000UL) |
| |
| #define | EBU_BUSWAP1_EXTCLOCK_Pos (16UL) |
| |
| #define | EBU_BUSWAP1_EXTCLOCK_Msk (0x30000UL) |
| |
| #define | EBU_BUSWAP1_EXTDATA_Pos (18UL) |
| |
| #define | EBU_BUSWAP1_EXTDATA_Msk (0xc0000UL) |
| |
| #define | EBU_BUSWAP1_CMDDELAY_Pos (20UL) |
| |
| #define | EBU_BUSWAP1_CMDDELAY_Msk (0xf00000UL) |
| |
| #define | EBU_BUSWAP1_AHOLDC_Pos (24UL) |
| |
| #define | EBU_BUSWAP1_AHOLDC_Msk (0xf000000UL) |
| |
| #define | EBU_BUSWAP1_ADDRC_Pos (28UL) |
| |
| #define | EBU_BUSWAP1_ADDRC_Msk (0xf0000000UL) |
| |
| #define | EBU_BUSRCON2_FETBLEN_Pos (0UL) |
| |
| #define | EBU_BUSRCON2_FETBLEN_Msk (0x7UL) |
| |
| #define | EBU_BUSRCON2_FBBMSEL_Pos (3UL) |
| |
| #define | EBU_BUSRCON2_FBBMSEL_Msk (0x8UL) |
| |
| #define | EBU_BUSRCON2_BFSSS_Pos (4UL) |
| |
| #define | EBU_BUSRCON2_BFSSS_Msk (0x10UL) |
| |
| #define | EBU_BUSRCON2_FDBKEN_Pos (5UL) |
| |
| #define | EBU_BUSRCON2_FDBKEN_Msk (0x20UL) |
| |
| #define | EBU_BUSRCON2_BFCMSEL_Pos (6UL) |
| |
| #define | EBU_BUSRCON2_BFCMSEL_Msk (0x40UL) |
| |
| #define | EBU_BUSRCON2_NAA_Pos (7UL) |
| |
| #define | EBU_BUSRCON2_NAA_Msk (0x80UL) |
| |
| #define | EBU_BUSRCON2_ECSE_Pos (16UL) |
| |
| #define | EBU_BUSRCON2_ECSE_Msk (0x10000UL) |
| |
| #define | EBU_BUSRCON2_EBSE_Pos (17UL) |
| |
| #define | EBU_BUSRCON2_EBSE_Msk (0x20000UL) |
| |
| #define | EBU_BUSRCON2_DBA_Pos (18UL) |
| |
| #define | EBU_BUSRCON2_DBA_Msk (0x40000UL) |
| |
| #define | EBU_BUSRCON2_WAITINV_Pos (19UL) |
| |
| #define | EBU_BUSRCON2_WAITINV_Msk (0x80000UL) |
| |
| #define | EBU_BUSRCON2_BCGEN_Pos (20UL) |
| |
| #define | EBU_BUSRCON2_BCGEN_Msk (0x300000UL) |
| |
| #define | EBU_BUSRCON2_PORTW_Pos (22UL) |
| |
| #define | EBU_BUSRCON2_PORTW_Msk (0xc00000UL) |
| |
| #define | EBU_BUSRCON2_WAIT_Pos (24UL) |
| |
| #define | EBU_BUSRCON2_WAIT_Msk (0x3000000UL) |
| |
| #define | EBU_BUSRCON2_AAP_Pos (26UL) |
| |
| #define | EBU_BUSRCON2_AAP_Msk (0x4000000UL) |
| |
| #define | EBU_BUSRCON2_AGEN_Pos (28UL) |
| |
| #define | EBU_BUSRCON2_AGEN_Msk (0xf0000000UL) |
| |
| #define | EBU_BUSRAP2_RDDTACS_Pos (0UL) |
| |
| #define | EBU_BUSRAP2_RDDTACS_Msk (0xfUL) |
| |
| #define | EBU_BUSRAP2_RDRECOVC_Pos (4UL) |
| |
| #define | EBU_BUSRAP2_RDRECOVC_Msk (0x70UL) |
| |
| #define | EBU_BUSRAP2_WAITRDC_Pos (7UL) |
| |
| #define | EBU_BUSRAP2_WAITRDC_Msk (0xf80UL) |
| |
| #define | EBU_BUSRAP2_DATAC_Pos (12UL) |
| |
| #define | EBU_BUSRAP2_DATAC_Msk (0xf000UL) |
| |
| #define | EBU_BUSRAP2_EXTCLOCK_Pos (16UL) |
| |
| #define | EBU_BUSRAP2_EXTCLOCK_Msk (0x30000UL) |
| |
| #define | EBU_BUSRAP2_EXTDATA_Pos (18UL) |
| |
| #define | EBU_BUSRAP2_EXTDATA_Msk (0xc0000UL) |
| |
| #define | EBU_BUSRAP2_CMDDELAY_Pos (20UL) |
| |
| #define | EBU_BUSRAP2_CMDDELAY_Msk (0xf00000UL) |
| |
| #define | EBU_BUSRAP2_AHOLDC_Pos (24UL) |
| |
| #define | EBU_BUSRAP2_AHOLDC_Msk (0xf000000UL) |
| |
| #define | EBU_BUSRAP2_ADDRC_Pos (28UL) |
| |
| #define | EBU_BUSRAP2_ADDRC_Msk (0xf0000000UL) |
| |
| #define | EBU_BUSWCON2_FETBLEN_Pos (0UL) |
| |
| #define | EBU_BUSWCON2_FETBLEN_Msk (0x7UL) |
| |
| #define | EBU_BUSWCON2_FBBMSEL_Pos (3UL) |
| |
| #define | EBU_BUSWCON2_FBBMSEL_Msk (0x8UL) |
| |
| #define | EBU_BUSWCON2_NAA_Pos (7UL) |
| |
| #define | EBU_BUSWCON2_NAA_Msk (0x80UL) |
| |
| #define | EBU_BUSWCON2_ECSE_Pos (16UL) |
| |
| #define | EBU_BUSWCON2_ECSE_Msk (0x10000UL) |
| |
| #define | EBU_BUSWCON2_EBSE_Pos (17UL) |
| |
| #define | EBU_BUSWCON2_EBSE_Msk (0x20000UL) |
| |
| #define | EBU_BUSWCON2_WAITINV_Pos (19UL) |
| |
| #define | EBU_BUSWCON2_WAITINV_Msk (0x80000UL) |
| |
| #define | EBU_BUSWCON2_BCGEN_Pos (20UL) |
| |
| #define | EBU_BUSWCON2_BCGEN_Msk (0x300000UL) |
| |
| #define | EBU_BUSWCON2_PORTW_Pos (22UL) |
| |
| #define | EBU_BUSWCON2_PORTW_Msk (0xc00000UL) |
| |
| #define | EBU_BUSWCON2_WAIT_Pos (24UL) |
| |
| #define | EBU_BUSWCON2_WAIT_Msk (0x3000000UL) |
| |
| #define | EBU_BUSWCON2_AAP_Pos (26UL) |
| |
| #define | EBU_BUSWCON2_AAP_Msk (0x4000000UL) |
| |
| #define | EBU_BUSWCON2_LOCKCS_Pos (27UL) |
| |
| #define | EBU_BUSWCON2_LOCKCS_Msk (0x8000000UL) |
| |
| #define | EBU_BUSWCON2_AGEN_Pos (28UL) |
| |
| #define | EBU_BUSWCON2_AGEN_Msk (0xf0000000UL) |
| |
| #define | EBU_BUSWAP2_WRDTACS_Pos (0UL) |
| |
| #define | EBU_BUSWAP2_WRDTACS_Msk (0xfUL) |
| |
| #define | EBU_BUSWAP2_WRRECOVC_Pos (4UL) |
| |
| #define | EBU_BUSWAP2_WRRECOVC_Msk (0x70UL) |
| |
| #define | EBU_BUSWAP2_WAITWRC_Pos (7UL) |
| |
| #define | EBU_BUSWAP2_WAITWRC_Msk (0xf80UL) |
| |
| #define | EBU_BUSWAP2_DATAC_Pos (12UL) |
| |
| #define | EBU_BUSWAP2_DATAC_Msk (0xf000UL) |
| |
| #define | EBU_BUSWAP2_EXTCLOCK_Pos (16UL) |
| |
| #define | EBU_BUSWAP2_EXTCLOCK_Msk (0x30000UL) |
| |
| #define | EBU_BUSWAP2_EXTDATA_Pos (18UL) |
| |
| #define | EBU_BUSWAP2_EXTDATA_Msk (0xc0000UL) |
| |
| #define | EBU_BUSWAP2_CMDDELAY_Pos (20UL) |
| |
| #define | EBU_BUSWAP2_CMDDELAY_Msk (0xf00000UL) |
| |
| #define | EBU_BUSWAP2_AHOLDC_Pos (24UL) |
| |
| #define | EBU_BUSWAP2_AHOLDC_Msk (0xf000000UL) |
| |
| #define | EBU_BUSWAP2_ADDRC_Pos (28UL) |
| |
| #define | EBU_BUSWAP2_ADDRC_Msk (0xf0000000UL) |
| |
| #define | EBU_BUSRCON3_FETBLEN_Pos (0UL) |
| |
| #define | EBU_BUSRCON3_FETBLEN_Msk (0x7UL) |
| |
| #define | EBU_BUSRCON3_FBBMSEL_Pos (3UL) |
| |
| #define | EBU_BUSRCON3_FBBMSEL_Msk (0x8UL) |
| |
| #define | EBU_BUSRCON3_BFSSS_Pos (4UL) |
| |
| #define | EBU_BUSRCON3_BFSSS_Msk (0x10UL) |
| |
| #define | EBU_BUSRCON3_FDBKEN_Pos (5UL) |
| |
| #define | EBU_BUSRCON3_FDBKEN_Msk (0x20UL) |
| |
| #define | EBU_BUSRCON3_BFCMSEL_Pos (6UL) |
| |
| #define | EBU_BUSRCON3_BFCMSEL_Msk (0x40UL) |
| |
| #define | EBU_BUSRCON3_NAA_Pos (7UL) |
| |
| #define | EBU_BUSRCON3_NAA_Msk (0x80UL) |
| |
| #define | EBU_BUSRCON3_ECSE_Pos (16UL) |
| |
| #define | EBU_BUSRCON3_ECSE_Msk (0x10000UL) |
| |
| #define | EBU_BUSRCON3_EBSE_Pos (17UL) |
| |
| #define | EBU_BUSRCON3_EBSE_Msk (0x20000UL) |
| |
| #define | EBU_BUSRCON3_DBA_Pos (18UL) |
| |
| #define | EBU_BUSRCON3_DBA_Msk (0x40000UL) |
| |
| #define | EBU_BUSRCON3_WAITINV_Pos (19UL) |
| |
| #define | EBU_BUSRCON3_WAITINV_Msk (0x80000UL) |
| |
| #define | EBU_BUSRCON3_BCGEN_Pos (20UL) |
| |
| #define | EBU_BUSRCON3_BCGEN_Msk (0x300000UL) |
| |
| #define | EBU_BUSRCON3_PORTW_Pos (22UL) |
| |
| #define | EBU_BUSRCON3_PORTW_Msk (0xc00000UL) |
| |
| #define | EBU_BUSRCON3_WAIT_Pos (24UL) |
| |
| #define | EBU_BUSRCON3_WAIT_Msk (0x3000000UL) |
| |
| #define | EBU_BUSRCON3_AAP_Pos (26UL) |
| |
| #define | EBU_BUSRCON3_AAP_Msk (0x4000000UL) |
| |
| #define | EBU_BUSRCON3_AGEN_Pos (28UL) |
| |
| #define | EBU_BUSRCON3_AGEN_Msk (0xf0000000UL) |
| |
| #define | EBU_BUSRAP3_RDDTACS_Pos (0UL) |
| |
| #define | EBU_BUSRAP3_RDDTACS_Msk (0xfUL) |
| |
| #define | EBU_BUSRAP3_RDRECOVC_Pos (4UL) |
| |
| #define | EBU_BUSRAP3_RDRECOVC_Msk (0x70UL) |
| |
| #define | EBU_BUSRAP3_WAITRDC_Pos (7UL) |
| |
| #define | EBU_BUSRAP3_WAITRDC_Msk (0xf80UL) |
| |
| #define | EBU_BUSRAP3_DATAC_Pos (12UL) |
| |
| #define | EBU_BUSRAP3_DATAC_Msk (0xf000UL) |
| |
| #define | EBU_BUSRAP3_EXTCLOCK_Pos (16UL) |
| |
| #define | EBU_BUSRAP3_EXTCLOCK_Msk (0x30000UL) |
| |
| #define | EBU_BUSRAP3_EXTDATA_Pos (18UL) |
| |
| #define | EBU_BUSRAP3_EXTDATA_Msk (0xc0000UL) |
| |
| #define | EBU_BUSRAP3_CMDDELAY_Pos (20UL) |
| |
| #define | EBU_BUSRAP3_CMDDELAY_Msk (0xf00000UL) |
| |
| #define | EBU_BUSRAP3_AHOLDC_Pos (24UL) |
| |
| #define | EBU_BUSRAP3_AHOLDC_Msk (0xf000000UL) |
| |
| #define | EBU_BUSRAP3_ADDRC_Pos (28UL) |
| |
| #define | EBU_BUSRAP3_ADDRC_Msk (0xf0000000UL) |
| |
| #define | EBU_BUSWCON3_FETBLEN_Pos (0UL) |
| |
| #define | EBU_BUSWCON3_FETBLEN_Msk (0x7UL) |
| |
| #define | EBU_BUSWCON3_FBBMSEL_Pos (3UL) |
| |
| #define | EBU_BUSWCON3_FBBMSEL_Msk (0x8UL) |
| |
| #define | EBU_BUSWCON3_NAA_Pos (7UL) |
| |
| #define | EBU_BUSWCON3_NAA_Msk (0x80UL) |
| |
| #define | EBU_BUSWCON3_ECSE_Pos (16UL) |
| |
| #define | EBU_BUSWCON3_ECSE_Msk (0x10000UL) |
| |
| #define | EBU_BUSWCON3_EBSE_Pos (17UL) |
| |
| #define | EBU_BUSWCON3_EBSE_Msk (0x20000UL) |
| |
| #define | EBU_BUSWCON3_WAITINV_Pos (19UL) |
| |
| #define | EBU_BUSWCON3_WAITINV_Msk (0x80000UL) |
| |
| #define | EBU_BUSWCON3_BCGEN_Pos (20UL) |
| |
| #define | EBU_BUSWCON3_BCGEN_Msk (0x300000UL) |
| |
| #define | EBU_BUSWCON3_PORTW_Pos (22UL) |
| |
| #define | EBU_BUSWCON3_PORTW_Msk (0xc00000UL) |
| |
| #define | EBU_BUSWCON3_WAIT_Pos (24UL) |
| |
| #define | EBU_BUSWCON3_WAIT_Msk (0x3000000UL) |
| |
| #define | EBU_BUSWCON3_AAP_Pos (26UL) |
| |
| #define | EBU_BUSWCON3_AAP_Msk (0x4000000UL) |
| |
| #define | EBU_BUSWCON3_LOCKCS_Pos (27UL) |
| |
| #define | EBU_BUSWCON3_LOCKCS_Msk (0x8000000UL) |
| |
| #define | EBU_BUSWCON3_AGEN_Pos (28UL) |
| |
| #define | EBU_BUSWCON3_AGEN_Msk (0xf0000000UL) |
| |
| #define | EBU_BUSWAP3_WRDTACS_Pos (0UL) |
| |
| #define | EBU_BUSWAP3_WRDTACS_Msk (0xfUL) |
| |
| #define | EBU_BUSWAP3_WRRECOVC_Pos (4UL) |
| |
| #define | EBU_BUSWAP3_WRRECOVC_Msk (0x70UL) |
| |
| #define | EBU_BUSWAP3_WAITWRC_Pos (7UL) |
| |
| #define | EBU_BUSWAP3_WAITWRC_Msk (0xf80UL) |
| |
| #define | EBU_BUSWAP3_DATAC_Pos (12UL) |
| |
| #define | EBU_BUSWAP3_DATAC_Msk (0xf000UL) |
| |
| #define | EBU_BUSWAP3_EXTCLOCK_Pos (16UL) |
| |
| #define | EBU_BUSWAP3_EXTCLOCK_Msk (0x30000UL) |
| |
| #define | EBU_BUSWAP3_EXTDATA_Pos (18UL) |
| |
| #define | EBU_BUSWAP3_EXTDATA_Msk (0xc0000UL) |
| |
| #define | EBU_BUSWAP3_CMDDELAY_Pos (20UL) |
| |
| #define | EBU_BUSWAP3_CMDDELAY_Msk (0xf00000UL) |
| |
| #define | EBU_BUSWAP3_AHOLDC_Pos (24UL) |
| |
| #define | EBU_BUSWAP3_AHOLDC_Msk (0xf000000UL) |
| |
| #define | EBU_BUSWAP3_ADDRC_Pos (28UL) |
| |
| #define | EBU_BUSWAP3_ADDRC_Msk (0xf0000000UL) |
| |
| #define | EBU_SDRMCON_CRAS_Pos (0UL) |
| |
| #define | EBU_SDRMCON_CRAS_Msk (0xfUL) |
| |
| #define | EBU_SDRMCON_CRFSH_Pos (4UL) |
| |
| #define | EBU_SDRMCON_CRFSH_Msk (0xf0UL) |
| |
| #define | EBU_SDRMCON_CRSC_Pos (8UL) |
| |
| #define | EBU_SDRMCON_CRSC_Msk (0x300UL) |
| |
| #define | EBU_SDRMCON_CRP_Pos (10UL) |
| |
| #define | EBU_SDRMCON_CRP_Msk (0xc00UL) |
| |
| #define | EBU_SDRMCON_AWIDTH_Pos (12UL) |
| |
| #define | EBU_SDRMCON_AWIDTH_Msk (0x3000UL) |
| |
| #define | EBU_SDRMCON_CRCD_Pos (14UL) |
| |
| #define | EBU_SDRMCON_CRCD_Msk (0xc000UL) |
| |
| #define | EBU_SDRMCON_CRC_Pos (16UL) |
| |
| #define | EBU_SDRMCON_CRC_Msk (0x70000UL) |
| |
| #define | EBU_SDRMCON_ROWM_Pos (19UL) |
| |
| #define | EBU_SDRMCON_ROWM_Msk (0x380000UL) |
| |
| #define | EBU_SDRMCON_BANKM_Pos (22UL) |
| |
| #define | EBU_SDRMCON_BANKM_Msk (0x1c00000UL) |
| |
| #define | EBU_SDRMCON_CRCE_Pos (25UL) |
| |
| #define | EBU_SDRMCON_CRCE_Msk (0xe000000UL) |
| |
| #define | EBU_SDRMCON_CLKDIS_Pos (28UL) |
| |
| #define | EBU_SDRMCON_CLKDIS_Msk (0x10000000UL) |
| |
| #define | EBU_SDRMCON_PWR_MODE_Pos (29UL) |
| |
| #define | EBU_SDRMCON_PWR_MODE_Msk (0x60000000UL) |
| |
| #define | EBU_SDRMCON_SDCMSEL_Pos (31UL) |
| |
| #define | EBU_SDRMCON_SDCMSEL_Msk (0x80000000UL) |
| |
| #define | EBU_SDRMOD_BURSTL_Pos (0UL) |
| |
| #define | EBU_SDRMOD_BURSTL_Msk (0x7UL) |
| |
| #define | EBU_SDRMOD_BTYP_Pos (3UL) |
| |
| #define | EBU_SDRMOD_BTYP_Msk (0x8UL) |
| |
| #define | EBU_SDRMOD_CASLAT_Pos (4UL) |
| |
| #define | EBU_SDRMOD_CASLAT_Msk (0x70UL) |
| |
| #define | EBU_SDRMOD_OPMODE_Pos (7UL) |
| |
| #define | EBU_SDRMOD_OPMODE_Msk (0x3f80UL) |
| |
| #define | EBU_SDRMOD_COLDSTART_Pos (15UL) |
| |
| #define | EBU_SDRMOD_COLDSTART_Msk (0x8000UL) |
| |
| #define | EBU_SDRMOD_XOPM_Pos (16UL) |
| |
| #define | EBU_SDRMOD_XOPM_Msk (0xfff0000UL) |
| |
| #define | EBU_SDRMOD_XBA_Pos (28UL) |
| |
| #define | EBU_SDRMOD_XBA_Msk (0xf0000000UL) |
| |
| #define | EBU_SDRMREF_REFRESHC_Pos (0UL) |
| |
| #define | EBU_SDRMREF_REFRESHC_Msk (0x3fUL) |
| |
| #define | EBU_SDRMREF_REFRESHR_Pos (6UL) |
| |
| #define | EBU_SDRMREF_REFRESHR_Msk (0x1c0UL) |
| |
| #define | EBU_SDRMREF_SELFREXST_Pos (9UL) |
| |
| #define | EBU_SDRMREF_SELFREXST_Msk (0x200UL) |
| |
| #define | EBU_SDRMREF_SELFREX_Pos (10UL) |
| |
| #define | EBU_SDRMREF_SELFREX_Msk (0x400UL) |
| |
| #define | EBU_SDRMREF_SELFRENST_Pos (11UL) |
| |
| #define | EBU_SDRMREF_SELFRENST_Msk (0x800UL) |
| |
| #define | EBU_SDRMREF_SELFREN_Pos (12UL) |
| |
| #define | EBU_SDRMREF_SELFREN_Msk (0x1000UL) |
| |
| #define | EBU_SDRMREF_AUTOSELFR_Pos (13UL) |
| |
| #define | EBU_SDRMREF_AUTOSELFR_Msk (0x2000UL) |
| |
| #define | EBU_SDRMREF_ERFSHC_Pos (14UL) |
| |
| #define | EBU_SDRMREF_ERFSHC_Msk (0xc000UL) |
| |
| #define | EBU_SDRMREF_SELFREX_DLY_Pos (16UL) |
| |
| #define | EBU_SDRMREF_SELFREX_DLY_Msk (0xff0000UL) |
| |
| #define | EBU_SDRMREF_ARFSH_Pos (24UL) |
| |
| #define | EBU_SDRMREF_ARFSH_Msk (0x1000000UL) |
| |
| #define | EBU_SDRMREF_RES_DLY_Pos (25UL) |
| |
| #define | EBU_SDRMREF_RES_DLY_Msk (0xe000000UL) |
| |
| #define | EBU_SDRSTAT_REFERR_Pos (0UL) |
| |
| #define | EBU_SDRSTAT_REFERR_Msk (0x1UL) |
| |
| #define | EBU_SDRSTAT_SDRMBUSY_Pos (1UL) |
| |
| #define | EBU_SDRSTAT_SDRMBUSY_Msk (0x2UL) |
| |
| #define | EBU_SDRSTAT_SDERR_Pos (2UL) |
| |
| #define | EBU_SDRSTAT_SDERR_Msk (0x4UL) |
| |
| #define | ETH_CON_RXD0_Pos (0UL) |
| |
| #define | ETH_CON_RXD0_Msk (0x3UL) |
| |
| #define | ETH_CON_RXD1_Pos (2UL) |
| |
| #define | ETH_CON_RXD1_Msk (0xcUL) |
| |
| #define | ETH_CON_RXD2_Pos (4UL) |
| |
| #define | ETH_CON_RXD2_Msk (0x30UL) |
| |
| #define | ETH_CON_RXD3_Pos (6UL) |
| |
| #define | ETH_CON_RXD3_Msk (0xc0UL) |
| |
| #define | ETH_CON_CLK_RMII_Pos (8UL) |
| |
| #define | ETH_CON_CLK_RMII_Msk (0x300UL) |
| |
| #define | ETH_CON_CRS_DV_Pos (10UL) |
| |
| #define | ETH_CON_CRS_DV_Msk (0xc00UL) |
| |
| #define | ETH_CON_CRS_Pos (12UL) |
| |
| #define | ETH_CON_CRS_Msk (0x3000UL) |
| |
| #define | ETH_CON_RXER_Pos (14UL) |
| |
| #define | ETH_CON_RXER_Msk (0xc000UL) |
| |
| #define | ETH_CON_COL_Pos (16UL) |
| |
| #define | ETH_CON_COL_Msk (0x30000UL) |
| |
| #define | ETH_CON_CLK_TX_Pos (18UL) |
| |
| #define | ETH_CON_CLK_TX_Msk (0xc0000UL) |
| |
| #define | ETH_CON_MDIO_Pos (22UL) |
| |
| #define | ETH_CON_MDIO_Msk (0xc00000UL) |
| |
| #define | ETH_CON_INFSEL_Pos (26UL) |
| |
| #define | ETH_CON_INFSEL_Msk (0x4000000UL) |
| |
| #define | ETH_MAC_CONFIGURATION_PRELEN_Pos (0UL) |
| |
| #define | ETH_MAC_CONFIGURATION_PRELEN_Msk (0x3UL) |
| |
| #define | ETH_MAC_CONFIGURATION_RE_Pos (2UL) |
| |
| #define | ETH_MAC_CONFIGURATION_RE_Msk (0x4UL) |
| |
| #define | ETH_MAC_CONFIGURATION_TE_Pos (3UL) |
| |
| #define | ETH_MAC_CONFIGURATION_TE_Msk (0x8UL) |
| |
| #define | ETH_MAC_CONFIGURATION_DC_Pos (4UL) |
| |
| #define | ETH_MAC_CONFIGURATION_DC_Msk (0x10UL) |
| |
| #define | ETH_MAC_CONFIGURATION_BL_Pos (5UL) |
| |
| #define | ETH_MAC_CONFIGURATION_BL_Msk (0x60UL) |
| |
| #define | ETH_MAC_CONFIGURATION_ACS_Pos (7UL) |
| |
| #define | ETH_MAC_CONFIGURATION_ACS_Msk (0x80UL) |
| |
| #define | ETH_MAC_CONFIGURATION_DR_Pos (9UL) |
| |
| #define | ETH_MAC_CONFIGURATION_DR_Msk (0x200UL) |
| |
| #define | ETH_MAC_CONFIGURATION_IPC_Pos (10UL) |
| |
| #define | ETH_MAC_CONFIGURATION_IPC_Msk (0x400UL) |
| |
| #define | ETH_MAC_CONFIGURATION_DM_Pos (11UL) |
| |
| #define | ETH_MAC_CONFIGURATION_DM_Msk (0x800UL) |
| |
| #define | ETH_MAC_CONFIGURATION_LM_Pos (12UL) |
| |
| #define | ETH_MAC_CONFIGURATION_LM_Msk (0x1000UL) |
| |
| #define | ETH_MAC_CONFIGURATION_DO_Pos (13UL) |
| |
| #define | ETH_MAC_CONFIGURATION_DO_Msk (0x2000UL) |
| |
| #define | ETH_MAC_CONFIGURATION_FES_Pos (14UL) |
| |
| #define | ETH_MAC_CONFIGURATION_FES_Msk (0x4000UL) |
| |
| #define | ETH_MAC_CONFIGURATION_DCRS_Pos (16UL) |
| |
| #define | ETH_MAC_CONFIGURATION_DCRS_Msk (0x10000UL) |
| |
| #define | ETH_MAC_CONFIGURATION_IFG_Pos (17UL) |
| |
| #define | ETH_MAC_CONFIGURATION_IFG_Msk (0xe0000UL) |
| |
| #define | ETH_MAC_CONFIGURATION_JE_Pos (20UL) |
| |
| #define | ETH_MAC_CONFIGURATION_JE_Msk (0x100000UL) |
| |
| #define | ETH_MAC_CONFIGURATION_BE_Pos (21UL) |
| |
| #define | ETH_MAC_CONFIGURATION_BE_Msk (0x200000UL) |
| |
| #define | ETH_MAC_CONFIGURATION_JD_Pos (22UL) |
| |
| #define | ETH_MAC_CONFIGURATION_JD_Msk (0x400000UL) |
| |
| #define | ETH_MAC_CONFIGURATION_WD_Pos (23UL) |
| |
| #define | ETH_MAC_CONFIGURATION_WD_Msk (0x800000UL) |
| |
| #define | ETH_MAC_CONFIGURATION_TC_Pos (24UL) |
| |
| #define | ETH_MAC_CONFIGURATION_TC_Msk (0x1000000UL) |
| |
| #define | ETH_MAC_CONFIGURATION_CST_Pos (25UL) |
| |
| #define | ETH_MAC_CONFIGURATION_CST_Msk (0x2000000UL) |
| |
| #define | ETH_MAC_CONFIGURATION_TWOKPE_Pos (27UL) |
| |
| #define | ETH_MAC_CONFIGURATION_TWOKPE_Msk (0x8000000UL) |
| |
| #define | ETH_MAC_CONFIGURATION_SARC_Pos (28UL) |
| |
| #define | ETH_MAC_CONFIGURATION_SARC_Msk (0x70000000UL) |
| |
| #define | ETH_MAC_FRAME_FILTER_PR_Pos (0UL) |
| |
| #define | ETH_MAC_FRAME_FILTER_PR_Msk (0x1UL) |
| |
| #define | ETH_MAC_FRAME_FILTER_HUC_Pos (1UL) |
| |
| #define | ETH_MAC_FRAME_FILTER_HUC_Msk (0x2UL) |
| |
| #define | ETH_MAC_FRAME_FILTER_HMC_Pos (2UL) |
| |
| #define | ETH_MAC_FRAME_FILTER_HMC_Msk (0x4UL) |
| |
| #define | ETH_MAC_FRAME_FILTER_DAIF_Pos (3UL) |
| |
| #define | ETH_MAC_FRAME_FILTER_DAIF_Msk (0x8UL) |
| |
| #define | ETH_MAC_FRAME_FILTER_PM_Pos (4UL) |
| |
| #define | ETH_MAC_FRAME_FILTER_PM_Msk (0x10UL) |
| |
| #define | ETH_MAC_FRAME_FILTER_DBF_Pos (5UL) |
| |
| #define | ETH_MAC_FRAME_FILTER_DBF_Msk (0x20UL) |
| |
| #define | ETH_MAC_FRAME_FILTER_PCF_Pos (6UL) |
| |
| #define | ETH_MAC_FRAME_FILTER_PCF_Msk (0xc0UL) |
| |
| #define | ETH_MAC_FRAME_FILTER_SAIF_Pos (8UL) |
| |
| #define | ETH_MAC_FRAME_FILTER_SAIF_Msk (0x100UL) |
| |
| #define | ETH_MAC_FRAME_FILTER_SAF_Pos (9UL) |
| |
| #define | ETH_MAC_FRAME_FILTER_SAF_Msk (0x200UL) |
| |
| #define | ETH_MAC_FRAME_FILTER_HPF_Pos (10UL) |
| |
| #define | ETH_MAC_FRAME_FILTER_HPF_Msk (0x400UL) |
| |
| #define | ETH_MAC_FRAME_FILTER_VTFE_Pos (16UL) |
| |
| #define | ETH_MAC_FRAME_FILTER_VTFE_Msk (0x10000UL) |
| |
| #define | ETH_MAC_FRAME_FILTER_IPFE_Pos (20UL) |
| |
| #define | ETH_MAC_FRAME_FILTER_IPFE_Msk (0x100000UL) |
| |
| #define | ETH_MAC_FRAME_FILTER_DNTU_Pos (21UL) |
| |
| #define | ETH_MAC_FRAME_FILTER_DNTU_Msk (0x200000UL) |
| |
| #define | ETH_MAC_FRAME_FILTER_RA_Pos (31UL) |
| |
| #define | ETH_MAC_FRAME_FILTER_RA_Msk (0x80000000UL) |
| |
| #define | ETH_HASH_TABLE_HIGH_HTH_Pos (0UL) |
| |
| #define | ETH_HASH_TABLE_HIGH_HTH_Msk (0xffffffffUL) |
| |
| #define | ETH_HASH_TABLE_LOW_HTL_Pos (0UL) |
| |
| #define | ETH_HASH_TABLE_LOW_HTL_Msk (0xffffffffUL) |
| |
| #define | ETH_GMII_ADDRESS_MB_Pos (0UL) |
| |
| #define | ETH_GMII_ADDRESS_MB_Msk (0x1UL) |
| |
| #define | ETH_GMII_ADDRESS_MW_Pos (1UL) |
| |
| #define | ETH_GMII_ADDRESS_MW_Msk (0x2UL) |
| |
| #define | ETH_GMII_ADDRESS_CR_Pos (2UL) |
| |
| #define | ETH_GMII_ADDRESS_CR_Msk (0x3cUL) |
| |
| #define | ETH_GMII_ADDRESS_MR_Pos (6UL) |
| |
| #define | ETH_GMII_ADDRESS_MR_Msk (0x7c0UL) |
| |
| #define | ETH_GMII_ADDRESS_PA_Pos (11UL) |
| |
| #define | ETH_GMII_ADDRESS_PA_Msk (0xf800UL) |
| |
| #define | ETH_GMII_DATA_MD_Pos (0UL) |
| |
| #define | ETH_GMII_DATA_MD_Msk (0xffffUL) |
| |
| #define | ETH_FLOW_CONTROL_FCA_BPA_Pos (0UL) |
| |
| #define | ETH_FLOW_CONTROL_FCA_BPA_Msk (0x1UL) |
| |
| #define | ETH_FLOW_CONTROL_TFE_Pos (1UL) |
| |
| #define | ETH_FLOW_CONTROL_TFE_Msk (0x2UL) |
| |
| #define | ETH_FLOW_CONTROL_RFE_Pos (2UL) |
| |
| #define | ETH_FLOW_CONTROL_RFE_Msk (0x4UL) |
| |
| #define | ETH_FLOW_CONTROL_UP_Pos (3UL) |
| |
| #define | ETH_FLOW_CONTROL_UP_Msk (0x8UL) |
| |
| #define | ETH_FLOW_CONTROL_PLT_Pos (4UL) |
| |
| #define | ETH_FLOW_CONTROL_PLT_Msk (0x30UL) |
| |
| #define | ETH_FLOW_CONTROL_DZPQ_Pos (7UL) |
| |
| #define | ETH_FLOW_CONTROL_DZPQ_Msk (0x80UL) |
| |
| #define | ETH_FLOW_CONTROL_PT_Pos (16UL) |
| |
| #define | ETH_FLOW_CONTROL_PT_Msk (0xffff0000UL) |
| |
| #define | ETH_VLAN_TAG_VL_Pos (0UL) |
| |
| #define | ETH_VLAN_TAG_VL_Msk (0xffffUL) |
| |
| #define | ETH_VLAN_TAG_ETV_Pos (16UL) |
| |
| #define | ETH_VLAN_TAG_ETV_Msk (0x10000UL) |
| |
| #define | ETH_VLAN_TAG_VTIM_Pos (17UL) |
| |
| #define | ETH_VLAN_TAG_VTIM_Msk (0x20000UL) |
| |
| #define | ETH_VLAN_TAG_ESVL_Pos (18UL) |
| |
| #define | ETH_VLAN_TAG_ESVL_Msk (0x40000UL) |
| |
| #define | ETH_VLAN_TAG_VTHM_Pos (19UL) |
| |
| #define | ETH_VLAN_TAG_VTHM_Msk (0x80000UL) |
| |
| #define | ETH_VERSION_SNPSVER_Pos (0UL) |
| |
| #define | ETH_VERSION_SNPSVER_Msk (0xffUL) |
| |
| #define | ETH_VERSION_USERVER_Pos (8UL) |
| |
| #define | ETH_VERSION_USERVER_Msk (0xff00UL) |
| |
| #define | ETH_DEBUG_RPESTS_Pos (0UL) |
| |
| #define | ETH_DEBUG_RPESTS_Msk (0x1UL) |
| |
| #define | ETH_DEBUG_RFCFCSTS_Pos (1UL) |
| |
| #define | ETH_DEBUG_RFCFCSTS_Msk (0x6UL) |
| |
| #define | ETH_DEBUG_RWCSTS_Pos (4UL) |
| |
| #define | ETH_DEBUG_RWCSTS_Msk (0x10UL) |
| |
| #define | ETH_DEBUG_RRCSTS_Pos (5UL) |
| |
| #define | ETH_DEBUG_RRCSTS_Msk (0x60UL) |
| |
| #define | ETH_DEBUG_RXFSTS_Pos (8UL) |
| |
| #define | ETH_DEBUG_RXFSTS_Msk (0x300UL) |
| |
| #define | ETH_DEBUG_TPESTS_Pos (16UL) |
| |
| #define | ETH_DEBUG_TPESTS_Msk (0x10000UL) |
| |
| #define | ETH_DEBUG_TFCSTS_Pos (17UL) |
| |
| #define | ETH_DEBUG_TFCSTS_Msk (0x60000UL) |
| |
| #define | ETH_DEBUG_TXPAUSED_Pos (19UL) |
| |
| #define | ETH_DEBUG_TXPAUSED_Msk (0x80000UL) |
| |
| #define | ETH_DEBUG_TRCSTS_Pos (20UL) |
| |
| #define | ETH_DEBUG_TRCSTS_Msk (0x300000UL) |
| |
| #define | ETH_DEBUG_TWCSTS_Pos (22UL) |
| |
| #define | ETH_DEBUG_TWCSTS_Msk (0x400000UL) |
| |
| #define | ETH_DEBUG_TXFSTS_Pos (24UL) |
| |
| #define | ETH_DEBUG_TXFSTS_Msk (0x1000000UL) |
| |
| #define | ETH_DEBUG_TXSTSFSTS_Pos (25UL) |
| |
| #define | ETH_DEBUG_TXSTSFSTS_Msk (0x2000000UL) |
| |
| #define | ETH_REMOTE_WAKE_UP_FRAME_FILTER_WKUPFRMFTR_Pos (0UL) |
| |
| #define | ETH_REMOTE_WAKE_UP_FRAME_FILTER_WKUPFRMFTR_Msk (0xffffffffUL) |
| |
| #define | ETH_PMT_CONTROL_STATUS_PWRDWN_Pos (0UL) |
| |
| #define | ETH_PMT_CONTROL_STATUS_PWRDWN_Msk (0x1UL) |
| |
| #define | ETH_PMT_CONTROL_STATUS_MGKPKTEN_Pos (1UL) |
| |
| #define | ETH_PMT_CONTROL_STATUS_MGKPKTEN_Msk (0x2UL) |
| |
| #define | ETH_PMT_CONTROL_STATUS_RWKPKTEN_Pos (2UL) |
| |
| #define | ETH_PMT_CONTROL_STATUS_RWKPKTEN_Msk (0x4UL) |
| |
| #define | ETH_PMT_CONTROL_STATUS_MGKPRCVD_Pos (5UL) |
| |
| #define | ETH_PMT_CONTROL_STATUS_MGKPRCVD_Msk (0x20UL) |
| |
| #define | ETH_PMT_CONTROL_STATUS_RWKPRCVD_Pos (6UL) |
| |
| #define | ETH_PMT_CONTROL_STATUS_RWKPRCVD_Msk (0x40UL) |
| |
| #define | ETH_PMT_CONTROL_STATUS_GLBLUCAST_Pos (9UL) |
| |
| #define | ETH_PMT_CONTROL_STATUS_GLBLUCAST_Msk (0x200UL) |
| |
| #define | ETH_PMT_CONTROL_STATUS_RWKFILTRST_Pos (31UL) |
| |
| #define | ETH_PMT_CONTROL_STATUS_RWKFILTRST_Msk (0x80000000UL) |
| |
| #define | ETH_INTERRUPT_STATUS_PMTIS_Pos (3UL) |
| |
| #define | ETH_INTERRUPT_STATUS_PMTIS_Msk (0x8UL) |
| |
| #define | ETH_INTERRUPT_STATUS_MMCIS_Pos (4UL) |
| |
| #define | ETH_INTERRUPT_STATUS_MMCIS_Msk (0x10UL) |
| |
| #define | ETH_INTERRUPT_STATUS_MMCRXIS_Pos (5UL) |
| |
| #define | ETH_INTERRUPT_STATUS_MMCRXIS_Msk (0x20UL) |
| |
| #define | ETH_INTERRUPT_STATUS_MMCTXIS_Pos (6UL) |
| |
| #define | ETH_INTERRUPT_STATUS_MMCTXIS_Msk (0x40UL) |
| |
| #define | ETH_INTERRUPT_STATUS_MMCRXIPIS_Pos (7UL) |
| |
| #define | ETH_INTERRUPT_STATUS_MMCRXIPIS_Msk (0x80UL) |
| |
| #define | ETH_INTERRUPT_STATUS_TSIS_Pos (9UL) |
| |
| #define | ETH_INTERRUPT_STATUS_TSIS_Msk (0x200UL) |
| |
| #define | ETH_INTERRUPT_MASK_PMTIM_Pos (3UL) |
| |
| #define | ETH_INTERRUPT_MASK_PMTIM_Msk (0x8UL) |
| |
| #define | ETH_INTERRUPT_MASK_TSIM_Pos (9UL) |
| |
| #define | ETH_INTERRUPT_MASK_TSIM_Msk (0x200UL) |
| |
| #define | ETH_MAC_ADDRESS0_HIGH_ADDRHI_Pos (0UL) |
| |
| #define | ETH_MAC_ADDRESS0_HIGH_ADDRHI_Msk (0xffffUL) |
| |
| #define | ETH_MAC_ADDRESS0_HIGH_AE_Pos (31UL) |
| |
| #define | ETH_MAC_ADDRESS0_HIGH_AE_Msk (0x80000000UL) |
| |
| #define | ETH_MAC_ADDRESS0_LOW_ADDRLO_Pos (0UL) |
| |
| #define | ETH_MAC_ADDRESS0_LOW_ADDRLO_Msk (0xffffffffUL) |
| |
| #define | ETH_MAC_ADDRESS1_HIGH_ADDRHI_Pos (0UL) |
| |
| #define | ETH_MAC_ADDRESS1_HIGH_ADDRHI_Msk (0xffffUL) |
| |
| #define | ETH_MAC_ADDRESS1_HIGH_MBC_Pos (24UL) |
| |
| #define | ETH_MAC_ADDRESS1_HIGH_MBC_Msk (0x3f000000UL) |
| |
| #define | ETH_MAC_ADDRESS1_HIGH_SA_Pos (30UL) |
| |
| #define | ETH_MAC_ADDRESS1_HIGH_SA_Msk (0x40000000UL) |
| |
| #define | ETH_MAC_ADDRESS1_HIGH_AE_Pos (31UL) |
| |
| #define | ETH_MAC_ADDRESS1_HIGH_AE_Msk (0x80000000UL) |
| |
| #define | ETH_MAC_ADDRESS1_LOW_ADDRLO_Pos (0UL) |
| |
| #define | ETH_MAC_ADDRESS1_LOW_ADDRLO_Msk (0xffffffffUL) |
| |
| #define | ETH_MAC_ADDRESS2_HIGH_ADDRHI_Pos (0UL) |
| |
| #define | ETH_MAC_ADDRESS2_HIGH_ADDRHI_Msk (0xffffUL) |
| |
| #define | ETH_MAC_ADDRESS2_HIGH_MBC_Pos (24UL) |
| |
| #define | ETH_MAC_ADDRESS2_HIGH_MBC_Msk (0x3f000000UL) |
| |
| #define | ETH_MAC_ADDRESS2_HIGH_SA_Pos (30UL) |
| |
| #define | ETH_MAC_ADDRESS2_HIGH_SA_Msk (0x40000000UL) |
| |
| #define | ETH_MAC_ADDRESS2_HIGH_AE_Pos (31UL) |
| |
| #define | ETH_MAC_ADDRESS2_HIGH_AE_Msk (0x80000000UL) |
| |
| #define | ETH_MAC_ADDRESS2_LOW_ADDRLO_Pos (0UL) |
| |
| #define | ETH_MAC_ADDRESS2_LOW_ADDRLO_Msk (0xffffffffUL) |
| |
| #define | ETH_MAC_ADDRESS3_HIGH_ADDRHI_Pos (0UL) |
| |
| #define | ETH_MAC_ADDRESS3_HIGH_ADDRHI_Msk (0xffffUL) |
| |
| #define | ETH_MAC_ADDRESS3_HIGH_MBC_Pos (24UL) |
| |
| #define | ETH_MAC_ADDRESS3_HIGH_MBC_Msk (0x3f000000UL) |
| |
| #define | ETH_MAC_ADDRESS3_HIGH_SA_Pos (30UL) |
| |
| #define | ETH_MAC_ADDRESS3_HIGH_SA_Msk (0x40000000UL) |
| |
| #define | ETH_MAC_ADDRESS3_HIGH_AE_Pos (31UL) |
| |
| #define | ETH_MAC_ADDRESS3_HIGH_AE_Msk (0x80000000UL) |
| |
| #define | ETH_MAC_ADDRESS3_LOW_ADDRLO_Pos (0UL) |
| |
| #define | ETH_MAC_ADDRESS3_LOW_ADDRLO_Msk (0xffffffffUL) |
| |
| #define | ETH_MMC_CONTROL_CNTRST_Pos (0UL) |
| |
| #define | ETH_MMC_CONTROL_CNTRST_Msk (0x1UL) |
| |
| #define | ETH_MMC_CONTROL_CNTSTOPRO_Pos (1UL) |
| |
| #define | ETH_MMC_CONTROL_CNTSTOPRO_Msk (0x2UL) |
| |
| #define | ETH_MMC_CONTROL_RSTONRD_Pos (2UL) |
| |
| #define | ETH_MMC_CONTROL_RSTONRD_Msk (0x4UL) |
| |
| #define | ETH_MMC_CONTROL_CNTFREEZ_Pos (3UL) |
| |
| #define | ETH_MMC_CONTROL_CNTFREEZ_Msk (0x8UL) |
| |
| #define | ETH_MMC_CONTROL_CNTPRST_Pos (4UL) |
| |
| #define | ETH_MMC_CONTROL_CNTPRST_Msk (0x10UL) |
| |
| #define | ETH_MMC_CONTROL_CNTPRSTLVL_Pos (5UL) |
| |
| #define | ETH_MMC_CONTROL_CNTPRSTLVL_Msk (0x20UL) |
| |
| #define | ETH_MMC_CONTROL_UCDBC_Pos (8UL) |
| |
| #define | ETH_MMC_CONTROL_UCDBC_Msk (0x100UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXGBFRMIS_Pos (0UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXGBFRMIS_Msk (0x1UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXGBOCTIS_Pos (1UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXGBOCTIS_Msk (0x2UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXGOCTIS_Pos (2UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXGOCTIS_Msk (0x4UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXBCGFIS_Pos (3UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXBCGFIS_Msk (0x8UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXMCGFIS_Pos (4UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXMCGFIS_Msk (0x10UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXCRCERFIS_Pos (5UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXCRCERFIS_Msk (0x20UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXALGNERFIS_Pos (6UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXALGNERFIS_Msk (0x40UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXRUNTFIS_Pos (7UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXRUNTFIS_Msk (0x80UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXJABERFIS_Pos (8UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXJABERFIS_Msk (0x100UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS_Pos (9UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS_Msk (0x200UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS_Pos (10UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS_Msk (0x400UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS_Pos (11UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS_Msk (0x800UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS_Pos (12UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS_Msk (0x1000UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS_Pos (13UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS_Msk (0x2000UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS_Pos (14UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS_Msk (0x4000UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS_Pos (15UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS_Msk (0x8000UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS_Pos (16UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS_Msk (0x10000UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXUCGFIS_Pos (17UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXUCGFIS_Msk (0x20000UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXLENERFIS_Pos (18UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXLENERFIS_Msk (0x40000UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXORANGEFIS_Pos (19UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXORANGEFIS_Msk (0x80000UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXPAUSFIS_Pos (20UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXPAUSFIS_Msk (0x100000UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXFOVFIS_Pos (21UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXFOVFIS_Msk (0x200000UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXVLANGBFIS_Pos (22UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXVLANGBFIS_Msk (0x400000UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXWDOGFIS_Pos (23UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXWDOGFIS_Msk (0x800000UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXRCVERRFIS_Pos (24UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXRCVERRFIS_Msk (0x1000000UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXCTRLFIS_Pos (25UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_RXCTRLFIS_Msk (0x2000000UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXGBOCTIS_Pos (0UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXGBOCTIS_Msk (0x1UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXGBFRMIS_Pos (1UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXGBFRMIS_Msk (0x2UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXBCGFIS_Pos (2UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXBCGFIS_Msk (0x4UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXMCGFIS_Pos (3UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXMCGFIS_Msk (0x8UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS_Pos (4UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS_Msk (0x10UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS_Pos (5UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS_Msk (0x20UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS_Pos (6UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS_Msk (0x40UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS_Pos (7UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS_Msk (0x80UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS_Pos (8UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS_Msk (0x100UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS_Pos (9UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS_Msk (0x200UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXUCGBFIS_Pos (10UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXUCGBFIS_Msk (0x400UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXMCGBFIS_Pos (11UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXMCGBFIS_Msk (0x800UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXBCGBFIS_Pos (12UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXBCGBFIS_Msk (0x1000UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS_Pos (13UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS_Msk (0x2000UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS_Pos (14UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS_Msk (0x4000UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS_Pos (15UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS_Msk (0x8000UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXDEFFIS_Pos (16UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXDEFFIS_Msk (0x10000UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXLATCOLFIS_Pos (17UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXLATCOLFIS_Msk (0x20000UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXEXCOLFIS_Pos (18UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXEXCOLFIS_Msk (0x40000UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXCARERFIS_Pos (19UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXCARERFIS_Msk (0x80000UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXGOCTIS_Pos (20UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXGOCTIS_Msk (0x100000UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXGFRMIS_Pos (21UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXGFRMIS_Msk (0x200000UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXEXDEFFIS_Pos (22UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXEXDEFFIS_Msk (0x400000UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXPAUSFIS_Pos (23UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXPAUSFIS_Msk (0x800000UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXVLANGFIS_Pos (24UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXVLANGFIS_Msk (0x1000000UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXOSIZEGFIS_Pos (25UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_TXOSIZEGFIS_Msk (0x2000000UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM_Pos (0UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM_Msk (0x1UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBOCTIM_Pos (1UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBOCTIM_Msk (0x2UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGOCTIM_Pos (2UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGOCTIM_Msk (0x4UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXBCGFIM_Pos (3UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXBCGFIM_Msk (0x8UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXMCGFIM_Pos (4UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXMCGFIM_Msk (0x10UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM_Pos (5UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM_Msk (0x20UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM_Pos (6UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM_Msk (0x40UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRUNTFIM_Pos (7UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRUNTFIM_Msk (0x80UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXJABERFIM_Pos (8UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXJABERFIM_Msk (0x100UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUSIZEGFIM_Pos (9UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUSIZEGFIM_Msk (0x200UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXOSIZEGFIM_Pos (10UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXOSIZEGFIM_Msk (0x400UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RX64OCTGBFIM_Pos (11UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RX64OCTGBFIM_Msk (0x800UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RX65T127OCTGBFIM_Pos (12UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RX65T127OCTGBFIM_Msk (0x1000UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RX128T255OCTGBFIM_Pos (13UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RX128T255OCTGBFIM_Msk (0x2000UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RX256T511OCTGBFIM_Pos (14UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RX256T511OCTGBFIM_Msk (0x4000UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RX512T1023OCTGBFIM_Pos (15UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RX512T1023OCTGBFIM_Msk (0x8000UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RX1024TMAXOCTGBFIM_Pos (16UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RX1024TMAXOCTGBFIM_Msk (0x10000UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM_Pos (17UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM_Msk (0x20000UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXLENERFIM_Pos (18UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXLENERFIM_Msk (0x40000UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXORANGEFIM_Pos (19UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXORANGEFIM_Msk (0x80000UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXPAUSFIM_Pos (20UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXPAUSFIM_Msk (0x100000UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM_Pos (21UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM_Msk (0x200000UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXVLANGBFIM_Pos (22UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXVLANGBFIM_Msk (0x400000UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXWDOGFIM_Pos (23UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXWDOGFIM_Msk (0x800000UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRCVERRFIM_Pos (24UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRCVERRFIM_Msk (0x1000000UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCTRLFIM_Pos (25UL) |
| |
| #define | ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCTRLFIM_Msk (0x2000000UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBOCTIM_Pos (0UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBOCTIM_Msk (0x1UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBFRMIM_Pos (1UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBFRMIM_Msk (0x2UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGFIM_Pos (2UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGFIM_Msk (0x4UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGFIM_Pos (3UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGFIM_Msk (0x8UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX64OCTGBFIM_Pos (4UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX64OCTGBFIM_Msk (0x10UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX65T127OCTGBFIM_Pos (5UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX65T127OCTGBFIM_Msk (0x20UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX128T255OCTGBFIM_Pos (6UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX128T255OCTGBFIM_Msk (0x40UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX256T511OCTGBFIM_Pos (7UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX256T511OCTGBFIM_Msk (0x80UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX512T1023OCTGBFIM_Pos (8UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX512T1023OCTGBFIM_Msk (0x100UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX1024TMAXOCTGBFIM_Pos (9UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX1024TMAXOCTGBFIM_Msk (0x200UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUCGBFIM_Pos (10UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUCGBFIM_Msk (0x400UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGBFIM_Pos (11UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGBFIM_Msk (0x800UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGBFIM_Pos (12UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGBFIM_Msk (0x1000UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM_Pos (13UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM_Msk (0x2000UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM_Pos (14UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM_Msk (0x4000UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM_Pos (15UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM_Msk (0x8000UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXDEFFIM_Pos (16UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXDEFFIM_Msk (0x10000UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXLATCOLFIM_Pos (17UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXLATCOLFIM_Msk (0x20000UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXCOLFIM_Pos (18UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXCOLFIM_Msk (0x40000UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXCARERFIM_Pos (19UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXCARERFIM_Msk (0x80000UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGOCTIM_Pos (20UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGOCTIM_Msk (0x100000UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM_Pos (21UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM_Msk (0x200000UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXDEFFIM_Pos (22UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXDEFFIM_Msk (0x400000UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXPAUSFIM_Pos (23UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXPAUSFIM_Msk (0x800000UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXVLANGFIM_Pos (24UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXVLANGFIM_Msk (0x1000000UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXOSIZEGFIM_Pos (25UL) |
| |
| #define | ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXOSIZEGFIM_Msk (0x2000000UL) |
| |
| #define | ETH_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_Pos (0UL) |
| |
| #define | ETH_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_Msk (0xffffffffUL) |
| |
| #define | ETH_TX_FRAME_COUNT_GOOD_BAD_TXFRMGB_Pos (0UL) |
| |
| #define | ETH_TX_FRAME_COUNT_GOOD_BAD_TXFRMGB_Msk (0xffffffffUL) |
| |
| #define | ETH_TX_BROADCAST_FRAMES_GOOD_TXBCASTG_Pos (0UL) |
| |
| #define | ETH_TX_BROADCAST_FRAMES_GOOD_TXBCASTG_Msk (0xffffffffUL) |
| |
| #define | ETH_TX_MULTICAST_FRAMES_GOOD_TXMCASTG_Pos (0UL) |
| |
| #define | ETH_TX_MULTICAST_FRAMES_GOOD_TXMCASTG_Msk (0xffffffffUL) |
| |
| #define | ETH_TX_64OCTETS_FRAMES_GOOD_BAD_TX64OCTGB_Pos (0UL) |
| |
| #define | ETH_TX_64OCTETS_FRAMES_GOOD_BAD_TX64OCTGB_Msk (0xffffffffUL) |
| |
| #define | ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD_TX65_127OCTGB_Pos (0UL) |
| |
| #define | ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD_TX65_127OCTGB_Msk (0xffffffffUL) |
| |
| #define | ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD_TX128_255OCTGB_Pos (0UL) |
| |
| #define | ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD_TX128_255OCTGB_Msk (0xffffffffUL) |
| |
| #define | ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD_TX256_511OCTGB_Pos (0UL) |
| |
| #define | ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD_TX256_511OCTGB_Msk (0xffffffffUL) |
| |
| #define | ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD_TX512_1023OCTGB_Pos (0UL) |
| |
| #define | ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD_TX512_1023OCTGB_Msk (0xffffffffUL) |
| |
| #define | ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_TX1024_MAXOCTGB_Pos (0UL) |
| |
| #define | ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_TX1024_MAXOCTGB_Msk (0xffffffffUL) |
| |
| #define | ETH_TX_UNICAST_FRAMES_GOOD_BAD_TXUCASTGB_Pos (0UL) |
| |
| #define | ETH_TX_UNICAST_FRAMES_GOOD_BAD_TXUCASTGB_Msk (0xffffffffUL) |
| |
| #define | ETH_TX_MULTICAST_FRAMES_GOOD_BAD_TXMCASTGB_Pos (0UL) |
| |
| #define | ETH_TX_MULTICAST_FRAMES_GOOD_BAD_TXMCASTGB_Msk (0xffffffffUL) |
| |
| #define | ETH_TX_BROADCAST_FRAMES_GOOD_BAD_TXBCASTGB_Pos (0UL) |
| |
| #define | ETH_TX_BROADCAST_FRAMES_GOOD_BAD_TXBCASTGB_Msk (0xffffffffUL) |
| |
| #define | ETH_TX_UNDERFLOW_ERROR_FRAMES_TXUNDRFLW_Pos (0UL) |
| |
| #define | ETH_TX_UNDERFLOW_ERROR_FRAMES_TXUNDRFLW_Msk (0xffffffffUL) |
| |
| #define | ETH_TX_SINGLE_COLLISION_GOOD_FRAMES_TXSNGLCOLG_Pos (0UL) |
| |
| #define | ETH_TX_SINGLE_COLLISION_GOOD_FRAMES_TXSNGLCOLG_Msk (0xffffffffUL) |
| |
| #define | ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES_TXMULTCOLG_Pos (0UL) |
| |
| #define | ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES_TXMULTCOLG_Msk (0xffffffffUL) |
| |
| #define | ETH_TX_DEFERRED_FRAMES_TXDEFRD_Pos (0UL) |
| |
| #define | ETH_TX_DEFERRED_FRAMES_TXDEFRD_Msk (0xffffffffUL) |
| |
| #define | ETH_TX_LATE_COLLISION_FRAMES_TXLATECOL_Pos (0UL) |
| |
| #define | ETH_TX_LATE_COLLISION_FRAMES_TXLATECOL_Msk (0xffffffffUL) |
| |
| #define | ETH_TX_EXCESSIVE_COLLISION_FRAMES_TXEXSCOL_Pos (0UL) |
| |
| #define | ETH_TX_EXCESSIVE_COLLISION_FRAMES_TXEXSCOL_Msk (0xffffffffUL) |
| |
| #define | ETH_TX_CARRIER_ERROR_FRAMES_TXCARR_Pos (0UL) |
| |
| #define | ETH_TX_CARRIER_ERROR_FRAMES_TXCARR_Msk (0xffffffffUL) |
| |
| #define | ETH_TX_OCTET_COUNT_GOOD_TXOCTG_Pos (0UL) |
| |
| #define | ETH_TX_OCTET_COUNT_GOOD_TXOCTG_Msk (0xffffffffUL) |
| |
| #define | ETH_TX_FRAME_COUNT_GOOD_TXFRMG_Pos (0UL) |
| |
| #define | ETH_TX_FRAME_COUNT_GOOD_TXFRMG_Msk (0xffffffffUL) |
| |
| #define | ETH_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_Pos (0UL) |
| |
| #define | ETH_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_Msk (0xffffffffUL) |
| |
| #define | ETH_TX_PAUSE_FRAMES_TXPAUSE_Pos (0UL) |
| |
| #define | ETH_TX_PAUSE_FRAMES_TXPAUSE_Msk (0xffffffffUL) |
| |
| #define | ETH_TX_VLAN_FRAMES_GOOD_TXVLANG_Pos (0UL) |
| |
| #define | ETH_TX_VLAN_FRAMES_GOOD_TXVLANG_Msk (0xffffffffUL) |
| |
| #define | ETH_TX_OSIZE_FRAMES_GOOD_TXOSIZG_Pos (0UL) |
| |
| #define | ETH_TX_OSIZE_FRAMES_GOOD_TXOSIZG_Msk (0xffffffffUL) |
| |
| #define | ETH_RX_FRAMES_COUNT_GOOD_BAD_RXFRMGB_Pos (0UL) |
| |
| #define | ETH_RX_FRAMES_COUNT_GOOD_BAD_RXFRMGB_Msk (0xffffffffUL) |
| |
| #define | ETH_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_Pos (0UL) |
| |
| #define | ETH_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_Msk (0xffffffffUL) |
| |
| #define | ETH_RX_OCTET_COUNT_GOOD_RXOCTG_Pos (0UL) |
| |
| #define | ETH_RX_OCTET_COUNT_GOOD_RXOCTG_Msk (0xffffffffUL) |
| |
| #define | ETH_RX_BROADCAST_FRAMES_GOOD_RXBCASTG_Pos (0UL) |
| |
| #define | ETH_RX_BROADCAST_FRAMES_GOOD_RXBCASTG_Msk (0xffffffffUL) |
| |
| #define | ETH_RX_MULTICAST_FRAMES_GOOD_RXMCASTG_Pos (0UL) |
| |
| #define | ETH_RX_MULTICAST_FRAMES_GOOD_RXMCASTG_Msk (0xffffffffUL) |
| |
| #define | ETH_RX_CRC_ERROR_FRAMES_RXCRCERR_Pos (0UL) |
| |
| #define | ETH_RX_CRC_ERROR_FRAMES_RXCRCERR_Msk (0xffffffffUL) |
| |
| #define | ETH_RX_ALIGNMENT_ERROR_FRAMES_RXALGNERR_Pos (0UL) |
| |
| #define | ETH_RX_ALIGNMENT_ERROR_FRAMES_RXALGNERR_Msk (0xffffffffUL) |
| |
| #define | ETH_RX_RUNT_ERROR_FRAMES_RXRUNTERR_Pos (0UL) |
| |
| #define | ETH_RX_RUNT_ERROR_FRAMES_RXRUNTERR_Msk (0xffffffffUL) |
| |
| #define | ETH_RX_JABBER_ERROR_FRAMES_RXJABERR_Pos (0UL) |
| |
| #define | ETH_RX_JABBER_ERROR_FRAMES_RXJABERR_Msk (0xffffffffUL) |
| |
| #define | ETH_RX_UNDERSIZE_FRAMES_GOOD_RXUNDERSZG_Pos (0UL) |
| |
| #define | ETH_RX_UNDERSIZE_FRAMES_GOOD_RXUNDERSZG_Msk (0xffffffffUL) |
| |
| #define | ETH_RX_OVERSIZE_FRAMES_GOOD_RXOVERSZG_Pos (0UL) |
| |
| #define | ETH_RX_OVERSIZE_FRAMES_GOOD_RXOVERSZG_Msk (0xffffffffUL) |
| |
| #define | ETH_RX_64OCTETS_FRAMES_GOOD_BAD_RX64OCTGB_Pos (0UL) |
| |
| #define | ETH_RX_64OCTETS_FRAMES_GOOD_BAD_RX64OCTGB_Msk (0xffffffffUL) |
| |
| #define | ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD_RX65_127OCTGB_Pos (0UL) |
| |
| #define | ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD_RX65_127OCTGB_Msk (0xffffffffUL) |
| |
| #define | ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD_RX128_255OCTGB_Pos (0UL) |
| |
| #define | ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD_RX128_255OCTGB_Msk (0xffffffffUL) |
| |
| #define | ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD_RX256_511OCTGB_Pos (0UL) |
| |
| #define | ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD_RX256_511OCTGB_Msk (0xffffffffUL) |
| |
| #define | ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD_RX512_1023OCTGB_Pos (0UL) |
| |
| #define | ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD_RX512_1023OCTGB_Msk (0xffffffffUL) |
| |
| #define | ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_RX1024_MAXOCTGB_Pos (0UL) |
| |
| #define | ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_RX1024_MAXOCTGB_Msk (0xffffffffUL) |
| |
| #define | ETH_RX_UNICAST_FRAMES_GOOD_RXUCASTG_Pos (0UL) |
| |
| #define | ETH_RX_UNICAST_FRAMES_GOOD_RXUCASTG_Msk (0xffffffffUL) |
| |
| #define | ETH_RX_LENGTH_ERROR_FRAMES_RXLENERR_Pos (0UL) |
| |
| #define | ETH_RX_LENGTH_ERROR_FRAMES_RXLENERR_Msk (0xffffffffUL) |
| |
| #define | ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_RXOUTOFRNG_Pos (0UL) |
| |
| #define | ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_RXOUTOFRNG_Msk (0xffffffffUL) |
| |
| #define | ETH_RX_PAUSE_FRAMES_RXPAUSEFRM_Pos (0UL) |
| |
| #define | ETH_RX_PAUSE_FRAMES_RXPAUSEFRM_Msk (0xffffffffUL) |
| |
| #define | ETH_RX_FIFO_OVERFLOW_FRAMES_RXFIFOOVFL_Pos (0UL) |
| |
| #define | ETH_RX_FIFO_OVERFLOW_FRAMES_RXFIFOOVFL_Msk (0xffffffffUL) |
| |
| #define | ETH_RX_VLAN_FRAMES_GOOD_BAD_RXVLANFRGB_Pos (0UL) |
| |
| #define | ETH_RX_VLAN_FRAMES_GOOD_BAD_RXVLANFRGB_Msk (0xffffffffUL) |
| |
| #define | ETH_RX_WATCHDOG_ERROR_FRAMES_RXWDGERR_Pos (0UL) |
| |
| #define | ETH_RX_WATCHDOG_ERROR_FRAMES_RXWDGERR_Msk (0xffffffffUL) |
| |
| #define | ETH_RX_RECEIVE_ERROR_FRAMES_RXRCVERR_Pos (0UL) |
| |
| #define | ETH_RX_RECEIVE_ERROR_FRAMES_RXRCVERR_Msk (0xffffffffUL) |
| |
| #define | ETH_RX_CONTROL_FRAMES_GOOD_RXCTRLG_Pos (0UL) |
| |
| #define | ETH_RX_CONTROL_FRAMES_GOOD_RXCTRLG_Msk (0xffffffffUL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GFIM_Pos (0UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GFIM_Msk (0x1UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HERFIM_Pos (1UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HERFIM_Msk (0x2UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYFIM_Pos (2UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYFIM_Msk (0x4UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGFIM_Pos (3UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGFIM_Msk (0x8UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLFIM_Pos (4UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLFIM_Msk (0x10UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GFIM_Pos (5UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GFIM_Msk (0x20UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HERFIM_Pos (6UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HERFIM_Msk (0x40UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYFIM_Pos (7UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYFIM_Msk (0x80UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGFIM_Pos (8UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGFIM_Msk (0x100UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPERFIM_Pos (9UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPERFIM_Msk (0x200UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGFIM_Pos (10UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGFIM_Msk (0x400UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPERFIM_Pos (11UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPERFIM_Msk (0x800UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM_Pos (12UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM_Msk (0x1000UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM_Pos (13UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM_Msk (0x2000UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GOIM_Pos (16UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GOIM_Msk (0x10000UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HEROIM_Pos (17UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HEROIM_Msk (0x20000UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYOIM_Pos (18UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYOIM_Msk (0x40000UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGOIM_Pos (19UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGOIM_Msk (0x80000UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLOIM_Pos (20UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLOIM_Msk (0x100000UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GOIM_Pos (21UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GOIM_Msk (0x200000UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HEROIM_Pos (22UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HEROIM_Msk (0x400000UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYOIM_Pos (23UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYOIM_Msk (0x800000UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGOIM_Pos (24UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGOIM_Msk (0x1000000UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPEROIM_Pos (25UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPEROIM_Msk (0x2000000UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGOIM_Pos (26UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGOIM_Msk (0x4000000UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPEROIM_Pos (27UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPEROIM_Msk (0x8000000UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGOIM_Pos (28UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGOIM_Msk (0x10000000UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPEROIM_Pos (29UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPEROIM_Msk (0x20000000UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GFIS_Pos (0UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GFIS_Msk (0x1UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HERFIS_Pos (1UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HERFIS_Msk (0x2UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYFIS_Pos (2UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYFIS_Msk (0x4UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGFIS_Pos (3UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGFIS_Msk (0x8UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLFIS_Pos (4UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLFIS_Msk (0x10UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GFIS_Pos (5UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GFIS_Msk (0x20UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HERFIS_Pos (6UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HERFIS_Msk (0x40UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYFIS_Pos (7UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYFIS_Msk (0x80UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGFIS_Pos (8UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGFIS_Msk (0x100UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPERFIS_Pos (9UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPERFIS_Msk (0x200UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGFIS_Pos (10UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGFIS_Msk (0x400UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPERFIS_Pos (11UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPERFIS_Msk (0x800UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS_Pos (12UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS_Msk (0x1000UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS_Pos (13UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS_Msk (0x2000UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GOIS_Pos (16UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GOIS_Msk (0x10000UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HEROIS_Pos (17UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HEROIS_Msk (0x20000UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYOIS_Pos (18UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYOIS_Msk (0x40000UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGOIS_Pos (19UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGOIS_Msk (0x80000UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLOIS_Pos (20UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLOIS_Msk (0x100000UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GOIS_Pos (21UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GOIS_Msk (0x200000UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HEROIS_Pos (22UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HEROIS_Msk (0x400000UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYOIS_Pos (23UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYOIS_Msk (0x800000UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGOIS_Pos (24UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGOIS_Msk (0x1000000UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPEROIS_Pos (25UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPEROIS_Msk (0x2000000UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGOIS_Pos (26UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGOIS_Msk (0x4000000UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPEROIS_Pos (27UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPEROIS_Msk (0x8000000UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGOIS_Pos (28UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGOIS_Msk (0x10000000UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPEROIS_Pos (29UL) |
| |
| #define | ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPEROIS_Msk (0x20000000UL) |
| |
| #define | ETH_RXIPV4_GOOD_FRAMES_RXIPV4GDFRM_Pos (0UL) |
| |
| #define | ETH_RXIPV4_GOOD_FRAMES_RXIPV4GDFRM_Msk (0xffffffffUL) |
| |
| #define | ETH_RXIPV4_HEADER_ERROR_FRAMES_RXIPV4HDRERRFRM_Pos (0UL) |
| |
| #define | ETH_RXIPV4_HEADER_ERROR_FRAMES_RXIPV4HDRERRFRM_Msk (0xffffffffUL) |
| |
| #define | ETH_RXIPV4_NO_PAYLOAD_FRAMES_RXIPV4NOPAYFRM_Pos (0UL) |
| |
| #define | ETH_RXIPV4_NO_PAYLOAD_FRAMES_RXIPV4NOPAYFRM_Msk (0xffffffffUL) |
| |
| #define | ETH_RXIPV4_FRAGMENTED_FRAMES_RXIPV4FRAGFRM_Pos (0UL) |
| |
| #define | ETH_RXIPV4_FRAGMENTED_FRAMES_RXIPV4FRAGFRM_Msk (0xffffffffUL) |
| |
| #define | ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_RXIPV4UDSBLFRM_Pos (0UL) |
| |
| #define | ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_RXIPV4UDSBLFRM_Msk (0xffffffffUL) |
| |
| #define | ETH_RXIPV6_GOOD_FRAMES_RXIPV6GDFRM_Pos (0UL) |
| |
| #define | ETH_RXIPV6_GOOD_FRAMES_RXIPV6GDFRM_Msk (0xffffffffUL) |
| |
| #define | ETH_RXIPV6_HEADER_ERROR_FRAMES_RXIPV6HDRERRFRM_Pos (0UL) |
| |
| #define | ETH_RXIPV6_HEADER_ERROR_FRAMES_RXIPV6HDRERRFRM_Msk (0xffffffffUL) |
| |
| #define | ETH_RXIPV6_NO_PAYLOAD_FRAMES_RXIPV6NOPAYFRM_Pos (0UL) |
| |
| #define | ETH_RXIPV6_NO_PAYLOAD_FRAMES_RXIPV6NOPAYFRM_Msk (0xffffffffUL) |
| |
| #define | ETH_RXUDP_GOOD_FRAMES_RXUDPGDFRM_Pos (0UL) |
| |
| #define | ETH_RXUDP_GOOD_FRAMES_RXUDPGDFRM_Msk (0xffffffffUL) |
| |
| #define | ETH_RXUDP_ERROR_FRAMES_RXUDPERRFRM_Pos (0UL) |
| |
| #define | ETH_RXUDP_ERROR_FRAMES_RXUDPERRFRM_Msk (0xffffffffUL) |
| |
| #define | ETH_RXTCP_GOOD_FRAMES_RXTCPGDFRM_Pos (0UL) |
| |
| #define | ETH_RXTCP_GOOD_FRAMES_RXTCPGDFRM_Msk (0xffffffffUL) |
| |
| #define | ETH_RXTCP_ERROR_FRAMES_RXTCPERRFRM_Pos (0UL) |
| |
| #define | ETH_RXTCP_ERROR_FRAMES_RXTCPERRFRM_Msk (0xffffffffUL) |
| |
| #define | ETH_RXICMP_GOOD_FRAMES_RXICMPGDFRM_Pos (0UL) |
| |
| #define | ETH_RXICMP_GOOD_FRAMES_RXICMPGDFRM_Msk (0xffffffffUL) |
| |
| #define | ETH_RXICMP_ERROR_FRAMES_RXICMPERRFRM_Pos (0UL) |
| |
| #define | ETH_RXICMP_ERROR_FRAMES_RXICMPERRFRM_Msk (0xffffffffUL) |
| |
| #define | ETH_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_Pos (0UL) |
| |
| #define | ETH_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_Msk (0xffffffffUL) |
| |
| #define | ETH_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_Pos (0UL) |
| |
| #define | ETH_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_Msk (0xffffffffUL) |
| |
| #define | ETH_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_Pos (0UL) |
| |
| #define | ETH_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_Msk (0xffffffffUL) |
| |
| #define | ETH_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_Pos (0UL) |
| |
| #define | ETH_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_Msk (0xffffffffUL) |
| |
| #define | ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_Pos (0UL) |
| |
| #define | ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_Msk (0xffffffffUL) |
| |
| #define | ETH_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_Pos (0UL) |
| |
| #define | ETH_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_Msk (0xffffffffUL) |
| |
| #define | ETH_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_Pos (0UL) |
| |
| #define | ETH_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_Msk (0xffffffffUL) |
| |
| #define | ETH_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_Pos (0UL) |
| |
| #define | ETH_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_Msk (0xffffffffUL) |
| |
| #define | ETH_RXUDP_GOOD_OCTETS_RXUDPGDOCT_Pos (0UL) |
| |
| #define | ETH_RXUDP_GOOD_OCTETS_RXUDPGDOCT_Msk (0xffffffffUL) |
| |
| #define | ETH_RXUDP_ERROR_OCTETS_RXUDPERROCT_Pos (0UL) |
| |
| #define | ETH_RXUDP_ERROR_OCTETS_RXUDPERROCT_Msk (0xffffffffUL) |
| |
| #define | ETH_RXTCP_GOOD_OCTETS_RXTCPGDOCT_Pos (0UL) |
| |
| #define | ETH_RXTCP_GOOD_OCTETS_RXTCPGDOCT_Msk (0xffffffffUL) |
| |
| #define | ETH_RXTCP_ERROR_OCTETS_RXTCPERROCT_Pos (0UL) |
| |
| #define | ETH_RXTCP_ERROR_OCTETS_RXTCPERROCT_Msk (0xffffffffUL) |
| |
| #define | ETH_RXICMP_GOOD_OCTETS_RXICMPGDOCT_Pos (0UL) |
| |
| #define | ETH_RXICMP_GOOD_OCTETS_RXICMPGDOCT_Msk (0xffffffffUL) |
| |
| #define | ETH_RXICMP_ERROR_OCTETS_RXICMPERROCT_Pos (0UL) |
| |
| #define | ETH_RXICMP_ERROR_OCTETS_RXICMPERROCT_Msk (0xffffffffUL) |
| |
| #define | ETH_TIMESTAMP_CONTROL_TSENA_Pos (0UL) |
| |
| #define | ETH_TIMESTAMP_CONTROL_TSENA_Msk (0x1UL) |
| |
| #define | ETH_TIMESTAMP_CONTROL_TSCFUPDT_Pos (1UL) |
| |
| #define | ETH_TIMESTAMP_CONTROL_TSCFUPDT_Msk (0x2UL) |
| |
| #define | ETH_TIMESTAMP_CONTROL_TSINIT_Pos (2UL) |
| |
| #define | ETH_TIMESTAMP_CONTROL_TSINIT_Msk (0x4UL) |
| |
| #define | ETH_TIMESTAMP_CONTROL_TSUPDT_Pos (3UL) |
| |
| #define | ETH_TIMESTAMP_CONTROL_TSUPDT_Msk (0x8UL) |
| |
| #define | ETH_TIMESTAMP_CONTROL_TSTRIG_Pos (4UL) |
| |
| #define | ETH_TIMESTAMP_CONTROL_TSTRIG_Msk (0x10UL) |
| |
| #define | ETH_TIMESTAMP_CONTROL_TSADDREG_Pos (5UL) |
| |
| #define | ETH_TIMESTAMP_CONTROL_TSADDREG_Msk (0x20UL) |
| |
| #define | ETH_TIMESTAMP_CONTROL_TSENALL_Pos (8UL) |
| |
| #define | ETH_TIMESTAMP_CONTROL_TSENALL_Msk (0x100UL) |
| |
| #define | ETH_TIMESTAMP_CONTROL_TSCTRLSSR_Pos (9UL) |
| |
| #define | ETH_TIMESTAMP_CONTROL_TSCTRLSSR_Msk (0x200UL) |
| |
| #define | ETH_TIMESTAMP_CONTROL_TSVER2ENA_Pos (10UL) |
| |
| #define | ETH_TIMESTAMP_CONTROL_TSVER2ENA_Msk (0x400UL) |
| |
| #define | ETH_TIMESTAMP_CONTROL_TSIPENA_Pos (11UL) |
| |
| #define | ETH_TIMESTAMP_CONTROL_TSIPENA_Msk (0x800UL) |
| |
| #define | ETH_TIMESTAMP_CONTROL_TSIPV6ENA_Pos (12UL) |
| |
| #define | ETH_TIMESTAMP_CONTROL_TSIPV6ENA_Msk (0x1000UL) |
| |
| #define | ETH_TIMESTAMP_CONTROL_TSIPV4ENA_Pos (13UL) |
| |
| #define | ETH_TIMESTAMP_CONTROL_TSIPV4ENA_Msk (0x2000UL) |
| |
| #define | ETH_TIMESTAMP_CONTROL_TSEVNTENA_Pos (14UL) |
| |
| #define | ETH_TIMESTAMP_CONTROL_TSEVNTENA_Msk (0x4000UL) |
| |
| #define | ETH_TIMESTAMP_CONTROL_TSMSTRENA_Pos (15UL) |
| |
| #define | ETH_TIMESTAMP_CONTROL_TSMSTRENA_Msk (0x8000UL) |
| |
| #define | ETH_TIMESTAMP_CONTROL_SNAPTYPSEL_Pos (16UL) |
| |
| #define | ETH_TIMESTAMP_CONTROL_SNAPTYPSEL_Msk (0x30000UL) |
| |
| #define | ETH_TIMESTAMP_CONTROL_TSENMACADDR_Pos (18UL) |
| |
| #define | ETH_TIMESTAMP_CONTROL_TSENMACADDR_Msk (0x40000UL) |
| |
| #define | ETH_SUB_SECOND_INCREMENT_SSINC_Pos (0UL) |
| |
| #define | ETH_SUB_SECOND_INCREMENT_SSINC_Msk (0xffUL) |
| |
| #define | ETH_SYSTEM_TIME_SECONDS_TSS_Pos (0UL) |
| |
| #define | ETH_SYSTEM_TIME_SECONDS_TSS_Msk (0xffffffffUL) |
| |
| #define | ETH_SYSTEM_TIME_NANOSECONDS_TSSS_Pos (0UL) |
| |
| #define | ETH_SYSTEM_TIME_NANOSECONDS_TSSS_Msk (0x7fffffffUL) |
| |
| #define | ETH_SYSTEM_TIME_SECONDS_UPDATE_TSS_Pos (0UL) |
| |
| #define | ETH_SYSTEM_TIME_SECONDS_UPDATE_TSS_Msk (0xffffffffUL) |
| |
| #define | ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_Pos (0UL) |
| |
| #define | ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_Msk (0x7fffffffUL) |
| |
| #define | ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_Pos (31UL) |
| |
| #define | ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_Msk (0x80000000UL) |
| |
| #define | ETH_TIMESTAMP_ADDEND_TSAR_Pos (0UL) |
| |
| #define | ETH_TIMESTAMP_ADDEND_TSAR_Msk (0xffffffffUL) |
| |
| #define | ETH_TARGET_TIME_SECONDS_TSTR_Pos (0UL) |
| |
| #define | ETH_TARGET_TIME_SECONDS_TSTR_Msk (0xffffffffUL) |
| |
| #define | ETH_TARGET_TIME_NANOSECONDS_TTSLO_Pos (0UL) |
| |
| #define | ETH_TARGET_TIME_NANOSECONDS_TTSLO_Msk (0x7fffffffUL) |
| |
| #define | ETH_TARGET_TIME_NANOSECONDS_TRGTBUSY_Pos (31UL) |
| |
| #define | ETH_TARGET_TIME_NANOSECONDS_TRGTBUSY_Msk (0x80000000UL) |
| |
| #define | ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_Pos (0UL) |
| |
| #define | ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_Msk (0xffffUL) |
| |
| #define | ETH_TIMESTAMP_STATUS_TSSOVF_Pos (0UL) |
| |
| #define | ETH_TIMESTAMP_STATUS_TSSOVF_Msk (0x1UL) |
| |
| #define | ETH_TIMESTAMP_STATUS_TSTARGT_Pos (1UL) |
| |
| #define | ETH_TIMESTAMP_STATUS_TSTARGT_Msk (0x2UL) |
| |
| #define | ETH_TIMESTAMP_STATUS_TSTRGTERR_Pos (3UL) |
| |
| #define | ETH_TIMESTAMP_STATUS_TSTRGTERR_Msk (0x8UL) |
| |
| #define | ETH_TIMESTAMP_STATUS_TSTARGT1_Pos (4UL) |
| |
| #define | ETH_TIMESTAMP_STATUS_TSTARGT1_Msk (0x10UL) |
| |
| #define | ETH_TIMESTAMP_STATUS_TSTRGTERR1_Pos (5UL) |
| |
| #define | ETH_TIMESTAMP_STATUS_TSTRGTERR1_Msk (0x20UL) |
| |
| #define | ETH_TIMESTAMP_STATUS_TSTARGT2_Pos (6UL) |
| |
| #define | ETH_TIMESTAMP_STATUS_TSTARGT2_Msk (0x40UL) |
| |
| #define | ETH_TIMESTAMP_STATUS_TSTRGTERR2_Pos (7UL) |
| |
| #define | ETH_TIMESTAMP_STATUS_TSTRGTERR2_Msk (0x80UL) |
| |
| #define | ETH_TIMESTAMP_STATUS_TSTARGT3_Pos (8UL) |
| |
| #define | ETH_TIMESTAMP_STATUS_TSTARGT3_Msk (0x100UL) |
| |
| #define | ETH_TIMESTAMP_STATUS_TSTRGTERR3_Pos (9UL) |
| |
| #define | ETH_TIMESTAMP_STATUS_TSTRGTERR3_Msk (0x200UL) |
| |
| #define | ETH_BUS_MODE_SWR_Pos (0UL) |
| |
| #define | ETH_BUS_MODE_SWR_Msk (0x1UL) |
| |
| #define | ETH_BUS_MODE_DA_Pos (1UL) |
| |
| #define | ETH_BUS_MODE_DA_Msk (0x2UL) |
| |
| #define | ETH_BUS_MODE_DSL_Pos (2UL) |
| |
| #define | ETH_BUS_MODE_DSL_Msk (0x7cUL) |
| |
| #define | ETH_BUS_MODE_ATDS_Pos (7UL) |
| |
| #define | ETH_BUS_MODE_ATDS_Msk (0x80UL) |
| |
| #define | ETH_BUS_MODE_PBL_Pos (8UL) |
| |
| #define | ETH_BUS_MODE_PBL_Msk (0x3f00UL) |
| |
| #define | ETH_BUS_MODE_PR_Pos (14UL) |
| |
| #define | ETH_BUS_MODE_PR_Msk (0xc000UL) |
| |
| #define | ETH_BUS_MODE_FB_Pos (16UL) |
| |
| #define | ETH_BUS_MODE_FB_Msk (0x10000UL) |
| |
| #define | ETH_BUS_MODE_RPBL_Pos (17UL) |
| |
| #define | ETH_BUS_MODE_RPBL_Msk (0x7e0000UL) |
| |
| #define | ETH_BUS_MODE_USP_Pos (23UL) |
| |
| #define | ETH_BUS_MODE_USP_Msk (0x800000UL) |
| |
| #define | ETH_BUS_MODE_PBLX8_Pos (24UL) |
| |
| #define | ETH_BUS_MODE_PBLX8_Msk (0x1000000UL) |
| |
| #define | ETH_BUS_MODE_AAL_Pos (25UL) |
| |
| #define | ETH_BUS_MODE_AAL_Msk (0x2000000UL) |
| |
| #define | ETH_BUS_MODE_MB_Pos (26UL) |
| |
| #define | ETH_BUS_MODE_MB_Msk (0x4000000UL) |
| |
| #define | ETH_BUS_MODE_TXPR_Pos (27UL) |
| |
| #define | ETH_BUS_MODE_TXPR_Msk (0x8000000UL) |
| |
| #define | ETH_BUS_MODE_PRWG_Pos (28UL) |
| |
| #define | ETH_BUS_MODE_PRWG_Msk (0x30000000UL) |
| |
| #define | ETH_TRANSMIT_POLL_DEMAND_TPD_Pos (0UL) |
| |
| #define | ETH_TRANSMIT_POLL_DEMAND_TPD_Msk (0xffffffffUL) |
| |
| #define | ETH_RECEIVE_POLL_DEMAND_RPD_Pos (0UL) |
| |
| #define | ETH_RECEIVE_POLL_DEMAND_RPD_Msk (0xffffffffUL) |
| |
| #define | ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32bit_Pos (2UL) |
| |
| #define | ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32bit_Msk (0xfffffffcUL) |
| |
| #define | ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32bit_Pos (2UL) |
| |
| #define | ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32bit_Msk (0xfffffffcUL) |
| |
| #define | ETH_STATUS_TI_Pos (0UL) |
| |
| #define | ETH_STATUS_TI_Msk (0x1UL) |
| |
| #define | ETH_STATUS_TPS_Pos (1UL) |
| |
| #define | ETH_STATUS_TPS_Msk (0x2UL) |
| |
| #define | ETH_STATUS_TU_Pos (2UL) |
| |
| #define | ETH_STATUS_TU_Msk (0x4UL) |
| |
| #define | ETH_STATUS_TJT_Pos (3UL) |
| |
| #define | ETH_STATUS_TJT_Msk (0x8UL) |
| |
| #define | ETH_STATUS_OVF_Pos (4UL) |
| |
| #define | ETH_STATUS_OVF_Msk (0x10UL) |
| |
| #define | ETH_STATUS_UNF_Pos (5UL) |
| |
| #define | ETH_STATUS_UNF_Msk (0x20UL) |
| |
| #define | ETH_STATUS_RI_Pos (6UL) |
| |
| #define | ETH_STATUS_RI_Msk (0x40UL) |
| |
| #define | ETH_STATUS_RU_Pos (7UL) |
| |
| #define | ETH_STATUS_RU_Msk (0x80UL) |
| |
| #define | ETH_STATUS_RPS_Pos (8UL) |
| |
| #define | ETH_STATUS_RPS_Msk (0x100UL) |
| |
| #define | ETH_STATUS_RWT_Pos (9UL) |
| |
| #define | ETH_STATUS_RWT_Msk (0x200UL) |
| |
| #define | ETH_STATUS_ETI_Pos (10UL) |
| |
| #define | ETH_STATUS_ETI_Msk (0x400UL) |
| |
| #define | ETH_STATUS_FBI_Pos (13UL) |
| |
| #define | ETH_STATUS_FBI_Msk (0x2000UL) |
| |
| #define | ETH_STATUS_ERI_Pos (14UL) |
| |
| #define | ETH_STATUS_ERI_Msk (0x4000UL) |
| |
| #define | ETH_STATUS_AIS_Pos (15UL) |
| |
| #define | ETH_STATUS_AIS_Msk (0x8000UL) |
| |
| #define | ETH_STATUS_NIS_Pos (16UL) |
| |
| #define | ETH_STATUS_NIS_Msk (0x10000UL) |
| |
| #define | ETH_STATUS_RS_Pos (17UL) |
| |
| #define | ETH_STATUS_RS_Msk (0xe0000UL) |
| |
| #define | ETH_STATUS_TS_Pos (20UL) |
| |
| #define | ETH_STATUS_TS_Msk (0x700000UL) |
| |
| #define | ETH_STATUS_EB_Pos (23UL) |
| |
| #define | ETH_STATUS_EB_Msk (0x3800000UL) |
| |
| #define | ETH_STATUS_EMI_Pos (27UL) |
| |
| #define | ETH_STATUS_EMI_Msk (0x8000000UL) |
| |
| #define | ETH_STATUS_EPI_Pos (28UL) |
| |
| #define | ETH_STATUS_EPI_Msk (0x10000000UL) |
| |
| #define | ETH_STATUS_TTI_Pos (29UL) |
| |
| #define | ETH_STATUS_TTI_Msk (0x20000000UL) |
| |
| #define | ETH_OPERATION_MODE_SR_Pos (1UL) |
| |
| #define | ETH_OPERATION_MODE_SR_Msk (0x2UL) |
| |
| #define | ETH_OPERATION_MODE_OSF_Pos (2UL) |
| |
| #define | ETH_OPERATION_MODE_OSF_Msk (0x4UL) |
| |
| #define | ETH_OPERATION_MODE_RTC_Pos (3UL) |
| |
| #define | ETH_OPERATION_MODE_RTC_Msk (0x18UL) |
| |
| #define | ETH_OPERATION_MODE_FUF_Pos (6UL) |
| |
| #define | ETH_OPERATION_MODE_FUF_Msk (0x40UL) |
| |
| #define | ETH_OPERATION_MODE_FEF_Pos (7UL) |
| |
| #define | ETH_OPERATION_MODE_FEF_Msk (0x80UL) |
| |
| #define | ETH_OPERATION_MODE_ST_Pos (13UL) |
| |
| #define | ETH_OPERATION_MODE_ST_Msk (0x2000UL) |
| |
| #define | ETH_OPERATION_MODE_TTC_Pos (14UL) |
| |
| #define | ETH_OPERATION_MODE_TTC_Msk (0x1c000UL) |
| |
| #define | ETH_OPERATION_MODE_FTF_Pos (20UL) |
| |
| #define | ETH_OPERATION_MODE_FTF_Msk (0x100000UL) |
| |
| #define | ETH_OPERATION_MODE_TSF_Pos (21UL) |
| |
| #define | ETH_OPERATION_MODE_TSF_Msk (0x200000UL) |
| |
| #define | ETH_OPERATION_MODE_DFF_Pos (24UL) |
| |
| #define | ETH_OPERATION_MODE_DFF_Msk (0x1000000UL) |
| |
| #define | ETH_OPERATION_MODE_RSF_Pos (25UL) |
| |
| #define | ETH_OPERATION_MODE_RSF_Msk (0x2000000UL) |
| |
| #define | ETH_OPERATION_MODE_DT_Pos (26UL) |
| |
| #define | ETH_OPERATION_MODE_DT_Msk (0x4000000UL) |
| |
| #define | ETH_INTERRUPT_ENABLE_TIE_Pos (0UL) |
| |
| #define | ETH_INTERRUPT_ENABLE_TIE_Msk (0x1UL) |
| |
| #define | ETH_INTERRUPT_ENABLE_TSE_Pos (1UL) |
| |
| #define | ETH_INTERRUPT_ENABLE_TSE_Msk (0x2UL) |
| |
| #define | ETH_INTERRUPT_ENABLE_TUE_Pos (2UL) |
| |
| #define | ETH_INTERRUPT_ENABLE_TUE_Msk (0x4UL) |
| |
| #define | ETH_INTERRUPT_ENABLE_TJE_Pos (3UL) |
| |
| #define | ETH_INTERRUPT_ENABLE_TJE_Msk (0x8UL) |
| |
| #define | ETH_INTERRUPT_ENABLE_OVE_Pos (4UL) |
| |
| #define | ETH_INTERRUPT_ENABLE_OVE_Msk (0x10UL) |
| |
| #define | ETH_INTERRUPT_ENABLE_UNE_Pos (5UL) |
| |
| #define | ETH_INTERRUPT_ENABLE_UNE_Msk (0x20UL) |
| |
| #define | ETH_INTERRUPT_ENABLE_RIE_Pos (6UL) |
| |
| #define | ETH_INTERRUPT_ENABLE_RIE_Msk (0x40UL) |
| |
| #define | ETH_INTERRUPT_ENABLE_RUE_Pos (7UL) |
| |
| #define | ETH_INTERRUPT_ENABLE_RUE_Msk (0x80UL) |
| |
| #define | ETH_INTERRUPT_ENABLE_RSE_Pos (8UL) |
| |
| #define | ETH_INTERRUPT_ENABLE_RSE_Msk (0x100UL) |
| |
| #define | ETH_INTERRUPT_ENABLE_RWE_Pos (9UL) |
| |
| #define | ETH_INTERRUPT_ENABLE_RWE_Msk (0x200UL) |
| |
| #define | ETH_INTERRUPT_ENABLE_ETE_Pos (10UL) |
| |
| #define | ETH_INTERRUPT_ENABLE_ETE_Msk (0x400UL) |
| |
| #define | ETH_INTERRUPT_ENABLE_FBE_Pos (13UL) |
| |
| #define | ETH_INTERRUPT_ENABLE_FBE_Msk (0x2000UL) |
| |
| #define | ETH_INTERRUPT_ENABLE_ERE_Pos (14UL) |
| |
| #define | ETH_INTERRUPT_ENABLE_ERE_Msk (0x4000UL) |
| |
| #define | ETH_INTERRUPT_ENABLE_AIE_Pos (15UL) |
| |
| #define | ETH_INTERRUPT_ENABLE_AIE_Msk (0x8000UL) |
| |
| #define | ETH_INTERRUPT_ENABLE_NIE_Pos (16UL) |
| |
| #define | ETH_INTERRUPT_ENABLE_NIE_Msk (0x10000UL) |
| |
| #define | ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_Pos (0UL) |
| |
| #define | ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_Msk (0xffffUL) |
| |
| #define | ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_Pos (16UL) |
| |
| #define | ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_Msk (0x10000UL) |
| |
| #define | ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_Pos (17UL) |
| |
| #define | ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_Msk (0xffe0000UL) |
| |
| #define | ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_Pos (28UL) |
| |
| #define | ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_Msk (0x10000000UL) |
| |
| #define | ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_Pos (0UL) |
| |
| #define | ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_Msk (0xffUL) |
| |
| #define | ETH_AHB_STATUS_AHBMS_Pos (0UL) |
| |
| #define | ETH_AHB_STATUS_AHBMS_Msk (0x1UL) |
| |
| #define | ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_Pos (0UL) |
| |
| #define | ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_Msk (0xffffffffUL) |
| |
| #define | ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_Pos (0UL) |
| |
| #define | ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_Msk (0xffffffffUL) |
| |
| #define | ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_Pos (0UL) |
| |
| #define | ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_Msk (0xffffffffUL) |
| |
| #define | ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_Pos (0UL) |
| |
| #define | ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_Msk (0xffffffffUL) |
| |
| #define | ETH_HW_FEATURE_MIISEL_Pos (0UL) |
| |
| #define | ETH_HW_FEATURE_MIISEL_Msk (0x1UL) |
| |
| #define | ETH_HW_FEATURE_GMIISEL_Pos (1UL) |
| |
| #define | ETH_HW_FEATURE_GMIISEL_Msk (0x2UL) |
| |
| #define | ETH_HW_FEATURE_HDSEL_Pos (2UL) |
| |
| #define | ETH_HW_FEATURE_HDSEL_Msk (0x4UL) |
| |
| #define | ETH_HW_FEATURE_EXTHASHEN_Pos (3UL) |
| |
| #define | ETH_HW_FEATURE_EXTHASHEN_Msk (0x8UL) |
| |
| #define | ETH_HW_FEATURE_HASHSEL_Pos (4UL) |
| |
| #define | ETH_HW_FEATURE_HASHSEL_Msk (0x10UL) |
| |
| #define | ETH_HW_FEATURE_ADDMACADRSEL_Pos (5UL) |
| |
| #define | ETH_HW_FEATURE_ADDMACADRSEL_Msk (0x20UL) |
| |
| #define | ETH_HW_FEATURE_PCSSEL_Pos (6UL) |
| |
| #define | ETH_HW_FEATURE_PCSSEL_Msk (0x40UL) |
| |
| #define | ETH_HW_FEATURE_L3L4FLTREN_Pos (7UL) |
| |
| #define | ETH_HW_FEATURE_L3L4FLTREN_Msk (0x80UL) |
| |
| #define | ETH_HW_FEATURE_SMASEL_Pos (8UL) |
| |
| #define | ETH_HW_FEATURE_SMASEL_Msk (0x100UL) |
| |
| #define | ETH_HW_FEATURE_RWKSEL_Pos (9UL) |
| |
| #define | ETH_HW_FEATURE_RWKSEL_Msk (0x200UL) |
| |
| #define | ETH_HW_FEATURE_MGKSEL_Pos (10UL) |
| |
| #define | ETH_HW_FEATURE_MGKSEL_Msk (0x400UL) |
| |
| #define | ETH_HW_FEATURE_MMCSEL_Pos (11UL) |
| |
| #define | ETH_HW_FEATURE_MMCSEL_Msk (0x800UL) |
| |
| #define | ETH_HW_FEATURE_TSVER1SEL_Pos (12UL) |
| |
| #define | ETH_HW_FEATURE_TSVER1SEL_Msk (0x1000UL) |
| |
| #define | ETH_HW_FEATURE_TSVER2SEL_Pos (13UL) |
| |
| #define | ETH_HW_FEATURE_TSVER2SEL_Msk (0x2000UL) |
| |
| #define | ETH_HW_FEATURE_EEESEL_Pos (14UL) |
| |
| #define | ETH_HW_FEATURE_EEESEL_Msk (0x4000UL) |
| |
| #define | ETH_HW_FEATURE_AVSEL_Pos (15UL) |
| |
| #define | ETH_HW_FEATURE_AVSEL_Msk (0x8000UL) |
| |
| #define | ETH_HW_FEATURE_TXCOESEL_Pos (16UL) |
| |
| #define | ETH_HW_FEATURE_TXCOESEL_Msk (0x10000UL) |
| |
| #define | ETH_HW_FEATURE_RXTYP1COE_Pos (17UL) |
| |
| #define | ETH_HW_FEATURE_RXTYP1COE_Msk (0x20000UL) |
| |
| #define | ETH_HW_FEATURE_RXTYP2COE_Pos (18UL) |
| |
| #define | ETH_HW_FEATURE_RXTYP2COE_Msk (0x40000UL) |
| |
| #define | ETH_HW_FEATURE_RXFIFOSIZE_Pos (19UL) |
| |
| #define | ETH_HW_FEATURE_RXFIFOSIZE_Msk (0x80000UL) |
| |
| #define | ETH_HW_FEATURE_RXCHCNT_Pos (20UL) |
| |
| #define | ETH_HW_FEATURE_RXCHCNT_Msk (0x300000UL) |
| |
| #define | ETH_HW_FEATURE_TXCHCNT_Pos (22UL) |
| |
| #define | ETH_HW_FEATURE_TXCHCNT_Msk (0xc00000UL) |
| |
| #define | ETH_HW_FEATURE_ENHDESSEL_Pos (24UL) |
| |
| #define | ETH_HW_FEATURE_ENHDESSEL_Msk (0x1000000UL) |
| |
| #define | ETH_HW_FEATURE_INTTSEN_Pos (25UL) |
| |
| #define | ETH_HW_FEATURE_INTTSEN_Msk (0x2000000UL) |
| |
| #define | ETH_HW_FEATURE_FLEXIPPSEN_Pos (26UL) |
| |
| #define | ETH_HW_FEATURE_FLEXIPPSEN_Msk (0x4000000UL) |
| |
| #define | ETH_HW_FEATURE_SAVLANINS_Pos (27UL) |
| |
| #define | ETH_HW_FEATURE_SAVLANINS_Msk (0x8000000UL) |
| |
| #define | ETH_HW_FEATURE_ACTPHYIF_Pos (28UL) |
| |
| #define | ETH_HW_FEATURE_ACTPHYIF_Msk (0x70000000UL) |
| |
| #define | ECAT0_CON_CON_ECATRSTEN_Pos (0UL) |
| |
| #define | ECAT0_CON_CON_ECATRSTEN_Msk (0x1UL) |
| |
| #define | ECAT0_CON_CON_LATCHIN0SEL_Pos (8UL) |
| |
| #define | ECAT0_CON_CON_LATCHIN0SEL_Msk (0x300UL) |
| |
| #define | ECAT0_CON_CON_LATCHIN0_Pos (11UL) |
| |
| #define | ECAT0_CON_CON_LATCHIN0_Msk (0x800UL) |
| |
| #define | ECAT0_CON_CON_LATCHIN1SEL_Pos (12UL) |
| |
| #define | ECAT0_CON_CON_LATCHIN1SEL_Msk (0x3000UL) |
| |
| #define | ECAT0_CON_CON_LATCHIN1_Pos (15UL) |
| |
| #define | ECAT0_CON_CON_LATCHIN1_Msk (0x8000UL) |
| |
| #define | ECAT0_CON_CON_PHYOFFSET_Pos (16UL) |
| |
| #define | ECAT0_CON_CON_PHYOFFSET_Msk (0x1f0000UL) |
| |
| #define | ECAT0_CON_CON_MDIO_Pos (22UL) |
| |
| #define | ECAT0_CON_CON_MDIO_Msk (0xc00000UL) |
| |
| #define | ECAT0_CON_CONP0_RXD0_Pos (0UL) |
| |
| #define | ECAT0_CON_CONP0_RXD0_Msk (0x3UL) |
| |
| #define | ECAT0_CON_CONP0_RXD1_Pos (2UL) |
| |
| #define | ECAT0_CON_CONP0_RXD1_Msk (0xcUL) |
| |
| #define | ECAT0_CON_CONP0_RXD2_Pos (4UL) |
| |
| #define | ECAT0_CON_CONP0_RXD2_Msk (0x30UL) |
| |
| #define | ECAT0_CON_CONP0_RXD3_Pos (6UL) |
| |
| #define | ECAT0_CON_CONP0_RXD3_Msk (0xc0UL) |
| |
| #define | ECAT0_CON_CONP0_RX_ERR_Pos (8UL) |
| |
| #define | ECAT0_CON_CONP0_RX_ERR_Msk (0x300UL) |
| |
| #define | ECAT0_CON_CONP0_RX_DV_Pos (10UL) |
| |
| #define | ECAT0_CON_CONP0_RX_DV_Msk (0xc00UL) |
| |
| #define | ECAT0_CON_CONP0_RX_CLK_Pos (12UL) |
| |
| #define | ECAT0_CON_CONP0_RX_CLK_Msk (0x3000UL) |
| |
| #define | ECAT0_CON_CONP0_LINK_Pos (16UL) |
| |
| #define | ECAT0_CON_CONP0_LINK_Msk (0x30000UL) |
| |
| #define | ECAT0_CON_CONP0_TX_CLK_Pos (28UL) |
| |
| #define | ECAT0_CON_CONP0_TX_CLK_Msk (0x30000000UL) |
| |
| #define | ECAT0_CON_CONP0_TX_SHIFT_Pos (30UL) |
| |
| #define | ECAT0_CON_CONP0_TX_SHIFT_Msk (0xc0000000UL) |
| |
| #define | ECAT0_CON_CONP1_RXD0_Pos (0UL) |
| |
| #define | ECAT0_CON_CONP1_RXD0_Msk (0x3UL) |
| |
| #define | ECAT0_CON_CONP1_RXD1_Pos (2UL) |
| |
| #define | ECAT0_CON_CONP1_RXD1_Msk (0xcUL) |
| |
| #define | ECAT0_CON_CONP1_RXD2_Pos (4UL) |
| |
| #define | ECAT0_CON_CONP1_RXD2_Msk (0x30UL) |
| |
| #define | ECAT0_CON_CONP1_RXD3_Pos (6UL) |
| |
| #define | ECAT0_CON_CONP1_RXD3_Msk (0xc0UL) |
| |
| #define | ECAT0_CON_CONP1_RX_ERR_Pos (8UL) |
| |
| #define | ECAT0_CON_CONP1_RX_ERR_Msk (0x300UL) |
| |
| #define | ECAT0_CON_CONP1_RX_DV_Pos (10UL) |
| |
| #define | ECAT0_CON_CONP1_RX_DV_Msk (0xc00UL) |
| |
| #define | ECAT0_CON_CONP1_RX_CLK_Pos (12UL) |
| |
| #define | ECAT0_CON_CONP1_RX_CLK_Msk (0x3000UL) |
| |
| #define | ECAT0_CON_CONP1_LINK_Pos (16UL) |
| |
| #define | ECAT0_CON_CONP1_LINK_Msk (0x30000UL) |
| |
| #define | ECAT0_CON_CONP1_TX_CLK_Pos (28UL) |
| |
| #define | ECAT0_CON_CONP1_TX_CLK_Msk (0x30000000UL) |
| |
| #define | ECAT0_CON_CONP1_TX_SHIFT_Pos (30UL) |
| |
| #define | ECAT0_CON_CONP1_TX_SHIFT_Msk (0xc0000000UL) |
| |
| #define | ECAT_TYPE_Type_Pos (0UL) |
| |
| #define | ECAT_TYPE_Type_Msk (0xffUL) |
| |
| #define | ECAT_REVISION_Revision_Pos (0UL) |
| |
| #define | ECAT_REVISION_Revision_Msk (0xffUL) |
| |
| #define | ECAT_BUILD_BUILD_Pos (0UL) |
| |
| #define | ECAT_BUILD_BUILD_Msk (0xffffUL) |
| |
| #define | ECAT_FMMU_NUM_NUM_FMMU_Pos (0UL) |
| |
| #define | ECAT_FMMU_NUM_NUM_FMMU_Msk (0xffUL) |
| |
| #define | ECAT_SYNC_MANAGER_NUM_SM_Pos (0UL) |
| |
| #define | ECAT_SYNC_MANAGER_NUM_SM_Msk (0xffUL) |
| |
| #define | ECAT_RAM_SIZE_RAM_Size_Pos (0UL) |
| |
| #define | ECAT_RAM_SIZE_RAM_Size_Msk (0xffUL) |
| |
| #define | ECAT_PORT_DESC_Port0_Pos (0UL) |
| |
| #define | ECAT_PORT_DESC_Port0_Msk (0x3UL) |
| |
| #define | ECAT_PORT_DESC_Port1_Pos (2UL) |
| |
| #define | ECAT_PORT_DESC_Port1_Msk (0xcUL) |
| |
| #define | ECAT_PORT_DESC_Port2_Pos (4UL) |
| |
| #define | ECAT_PORT_DESC_Port2_Msk (0x30UL) |
| |
| #define | ECAT_PORT_DESC_Port3_Pos (6UL) |
| |
| #define | ECAT_PORT_DESC_Port3_Msk (0xc0UL) |
| |
| #define | ECAT_FEATURE_FMMU_Pos (0UL) |
| |
| #define | ECAT_FEATURE_FMMU_Msk (0x1UL) |
| |
| #define | ECAT_FEATURE_CLKS_Pos (2UL) |
| |
| #define | ECAT_FEATURE_CLKS_Msk (0x4UL) |
| |
| #define | ECAT_FEATURE_CLKS_W_Pos (3UL) |
| |
| #define | ECAT_FEATURE_CLKS_W_Msk (0x8UL) |
| |
| #define | ECAT_FEATURE_LJ_EBUS_Pos (4UL) |
| |
| #define | ECAT_FEATURE_LJ_EBUS_Msk (0x10UL) |
| |
| #define | ECAT_FEATURE_ELD_EBUS_Pos (5UL) |
| |
| #define | ECAT_FEATURE_ELD_EBUS_Msk (0x20UL) |
| |
| #define | ECAT_FEATURE_ELD_MII_Pos (6UL) |
| |
| #define | ECAT_FEATURE_ELD_MII_Msk (0x40UL) |
| |
| #define | ECAT_FEATURE_SH_FCSE_Pos (7UL) |
| |
| #define | ECAT_FEATURE_SH_FCSE_Msk (0x80UL) |
| |
| #define | ECAT_FEATURE_EDC_SYNCA_Pos (8UL) |
| |
| #define | ECAT_FEATURE_EDC_SYNCA_Msk (0x100UL) |
| |
| #define | ECAT_FEATURE_LRW_CS_Pos (9UL) |
| |
| #define | ECAT_FEATURE_LRW_CS_Msk (0x200UL) |
| |
| #define | ECAT_FEATURE_RW_CS_Pos (10UL) |
| |
| #define | ECAT_FEATURE_RW_CS_Msk (0x400UL) |
| |
| #define | ECAT_FEATURE_FX_CONF_Pos (11UL) |
| |
| #define | ECAT_FEATURE_FX_CONF_Msk (0x800UL) |
| |
| #define | ECAT_STATION_ADR_NODE_ADDR_Pos (0UL) |
| |
| #define | ECAT_STATION_ADR_NODE_ADDR_Msk (0xffffUL) |
| |
| #define | ECAT_STATION_ALIAS_ALIAS_ADDR_Pos (0UL) |
| |
| #define | ECAT_STATION_ALIAS_ALIAS_ADDR_Msk (0xffffUL) |
| |
| #define | ECAT_WR_REG_ENABLE_WR_REG_EN_Pos (0UL) |
| |
| #define | ECAT_WR_REG_ENABLE_WR_REG_EN_Msk (0x1UL) |
| |
| #define | ECAT_WR_REG_PROTECT_WR_REG_P_Pos (0UL) |
| |
| #define | ECAT_WR_REG_PROTECT_WR_REG_P_Msk (0x1UL) |
| |
| #define | ECAT_ESC_WR_ENABLE_ESC_WR_PROT_Pos (0UL) |
| |
| #define | ECAT_ESC_WR_ENABLE_ESC_WR_PROT_Msk (0x1UL) |
| |
| #define | ECAT_ESC_WR_PROTECT_ESC_WR_PROT_Pos (0UL) |
| |
| #define | ECAT_ESC_WR_PROTECT_ESC_WR_PROT_Msk (0x1UL) |
| |
| #define | ECAT_ESC_RESET_ECAT_RESET_CMD_WRITEMode_Pos (0UL) |
| |
| #define | ECAT_ESC_RESET_ECAT_RESET_CMD_WRITEMode_Msk (0xffUL) |
| |
| #define | ECAT_ESC_RESET_ECAT_RESET_CMD_STATE_READMode_Pos (0UL) |
| |
| #define | ECAT_ESC_RESET_ECAT_RESET_CMD_STATE_READMode_Msk (0x3UL) |
| |
| #define | ECAT_ESC_RESET_PDI_RESET_CMD_WRITEMode_Pos (0UL) |
| |
| #define | ECAT_ESC_RESET_PDI_RESET_CMD_WRITEMode_Msk (0xffUL) |
| |
| #define | ECAT_ESC_RESET_PDI_RESET_CMD_STATE_READMode_Pos (0UL) |
| |
| #define | ECAT_ESC_RESET_PDI_RESET_CMD_STATE_READMode_Msk (0x3UL) |
| |
| #define | ECAT_ESC_DL_CONTROL_FR_Pos (0UL) |
| |
| #define | ECAT_ESC_DL_CONTROL_FR_Msk (0x1UL) |
| |
| #define | ECAT_ESC_DL_CONTROL_TEMP_Pos (1UL) |
| |
| #define | ECAT_ESC_DL_CONTROL_TEMP_Msk (0x2UL) |
| |
| #define | ECAT_ESC_DL_CONTROL_LP0_Pos (8UL) |
| |
| #define | ECAT_ESC_DL_CONTROL_LP0_Msk (0x300UL) |
| |
| #define | ECAT_ESC_DL_CONTROL_LP1_Pos (10UL) |
| |
| #define | ECAT_ESC_DL_CONTROL_LP1_Msk (0xc00UL) |
| |
| #define | ECAT_ESC_DL_CONTROL_LP2_Pos (12UL) |
| |
| #define | ECAT_ESC_DL_CONTROL_LP2_Msk (0x3000UL) |
| |
| #define | ECAT_ESC_DL_CONTROL_LP3_Pos (14UL) |
| |
| #define | ECAT_ESC_DL_CONTROL_LP3_Msk (0xc000UL) |
| |
| #define | ECAT_ESC_DL_CONTROL_RX_FIFO_SIZE_Pos (16UL) |
| |
| #define | ECAT_ESC_DL_CONTROL_RX_FIFO_SIZE_Msk (0x70000UL) |
| |
| #define | ECAT_ESC_DL_CONTROL_LJ_Pos (19UL) |
| |
| #define | ECAT_ESC_DL_CONTROL_LJ_Msk (0x80000UL) |
| |
| #define | ECAT_ESC_DL_CONTROL_RLD_ST_Pos (22UL) |
| |
| #define | ECAT_ESC_DL_CONTROL_RLD_ST_Msk (0x400000UL) |
| |
| #define | ECAT_ESC_DL_CONTROL_S_ALIAS_Pos (24UL) |
| |
| #define | ECAT_ESC_DL_CONTROL_S_ALIAS_Msk (0x1000000UL) |
| |
| #define | ECAT_PHYSICAL_RW_OFFSET_OFFSET_Pos (0UL) |
| |
| #define | ECAT_PHYSICAL_RW_OFFSET_OFFSET_Msk (0xffffUL) |
| |
| #define | ECAT_ESC_DL_STATUS_PDI_EEPROM_Pos (0UL) |
| |
| #define | ECAT_ESC_DL_STATUS_PDI_EEPROM_Msk (0x1UL) |
| |
| #define | ECAT_ESC_DL_STATUS_PDI_WDT_S_Pos (1UL) |
| |
| #define | ECAT_ESC_DL_STATUS_PDI_WDT_S_Msk (0x2UL) |
| |
| #define | ECAT_ESC_DL_STATUS_ELD_Pos (2UL) |
| |
| #define | ECAT_ESC_DL_STATUS_ELD_Msk (0x4UL) |
| |
| #define | ECAT_ESC_DL_STATUS_LINK_P0_Pos (4UL) |
| |
| #define | ECAT_ESC_DL_STATUS_LINK_P0_Msk (0x10UL) |
| |
| #define | ECAT_ESC_DL_STATUS_LINK_P1_Pos (5UL) |
| |
| #define | ECAT_ESC_DL_STATUS_LINK_P1_Msk (0x20UL) |
| |
| #define | ECAT_ESC_DL_STATUS_LINK_P2_Pos (6UL) |
| |
| #define | ECAT_ESC_DL_STATUS_LINK_P2_Msk (0x40UL) |
| |
| #define | ECAT_ESC_DL_STATUS_LINK_P3_Pos (7UL) |
| |
| #define | ECAT_ESC_DL_STATUS_LINK_P3_Msk (0x80UL) |
| |
| #define | ECAT_ESC_DL_STATUS_LP0_Pos (8UL) |
| |
| #define | ECAT_ESC_DL_STATUS_LP0_Msk (0x100UL) |
| |
| #define | ECAT_ESC_DL_STATUS_COM_P0_Pos (9UL) |
| |
| #define | ECAT_ESC_DL_STATUS_COM_P0_Msk (0x200UL) |
| |
| #define | ECAT_ESC_DL_STATUS_LP1_Pos (10UL) |
| |
| #define | ECAT_ESC_DL_STATUS_LP1_Msk (0x400UL) |
| |
| #define | ECAT_ESC_DL_STATUS_COM_P1_Pos (11UL) |
| |
| #define | ECAT_ESC_DL_STATUS_COM_P1_Msk (0x800UL) |
| |
| #define | ECAT_ESC_DL_STATUS_LP2_Pos (12UL) |
| |
| #define | ECAT_ESC_DL_STATUS_LP2_Msk (0x1000UL) |
| |
| #define | ECAT_ESC_DL_STATUS_COM_P2_Pos (13UL) |
| |
| #define | ECAT_ESC_DL_STATUS_COM_P2_Msk (0x2000UL) |
| |
| #define | ECAT_ESC_DL_STATUS_LP3_Pos (14UL) |
| |
| #define | ECAT_ESC_DL_STATUS_LP3_Msk (0x4000UL) |
| |
| #define | ECAT_ESC_DL_STATUS_COM_P3_Pos (15UL) |
| |
| #define | ECAT_ESC_DL_STATUS_COM_P3_Msk (0x8000UL) |
| |
| #define | ECAT_AL_CONTROL_IST_Pos (0UL) |
| |
| #define | ECAT_AL_CONTROL_IST_Msk (0xfUL) |
| |
| #define | ECAT_AL_CONTROL_EIA_Pos (4UL) |
| |
| #define | ECAT_AL_CONTROL_EIA_Msk (0x10UL) |
| |
| #define | ECAT_AL_CONTROL_DID_Pos (5UL) |
| |
| #define | ECAT_AL_CONTROL_DID_Msk (0x20UL) |
| |
| #define | ECAT_AL_STATUS_STATE_Pos (0UL) |
| |
| #define | ECAT_AL_STATUS_STATE_Msk (0xfUL) |
| |
| #define | ECAT_AL_STATUS_ERRI_Pos (4UL) |
| |
| #define | ECAT_AL_STATUS_ERRI_Msk (0x10UL) |
| |
| #define | ECAT_AL_STATUS_DID_Pos (5UL) |
| |
| #define | ECAT_AL_STATUS_DID_Msk (0x20UL) |
| |
| #define | ECAT_AL_STATUS_CODE_AL_S_CODE_Pos (0UL) |
| |
| #define | ECAT_AL_STATUS_CODE_AL_S_CODE_Msk (0xffffUL) |
| |
| #define | ECAT_RUN_LED_LED_CODE_Pos (0UL) |
| |
| #define | ECAT_RUN_LED_LED_CODE_Msk (0xfUL) |
| |
| #define | ECAT_RUN_LED_EN_OVERR_Pos (4UL) |
| |
| #define | ECAT_RUN_LED_EN_OVERR_Msk (0x10UL) |
| |
| #define | ECAT_ERR_LED_LED_CODE_Pos (0UL) |
| |
| #define | ECAT_ERR_LED_LED_CODE_Msk (0xfUL) |
| |
| #define | ECAT_ERR_LED_EN_OVERR_Pos (4UL) |
| |
| #define | ECAT_ERR_LED_EN_OVERR_Msk (0x10UL) |
| |
| #define | ECAT_PDI_CONTROL_PDI_Pos (0UL) |
| |
| #define | ECAT_PDI_CONTROL_PDI_Msk (0xffUL) |
| |
| #define | ECAT_ESC_CONFIG_EMUL_Pos (0UL) |
| |
| #define | ECAT_ESC_CONFIG_EMUL_Msk (0x1UL) |
| |
| #define | ECAT_ESC_CONFIG_EHLD_Pos (1UL) |
| |
| #define | ECAT_ESC_CONFIG_EHLD_Msk (0x2UL) |
| |
| #define | ECAT_ESC_CONFIG_CLKS_OUT_Pos (2UL) |
| |
| #define | ECAT_ESC_CONFIG_CLKS_OUT_Msk (0x4UL) |
| |
| #define | ECAT_ESC_CONFIG_CLKS_IN_Pos (3UL) |
| |
| #define | ECAT_ESC_CONFIG_CLKS_IN_Msk (0x8UL) |
| |
| #define | ECAT_ESC_CONFIG_EHLD_P0_Pos (4UL) |
| |
| #define | ECAT_ESC_CONFIG_EHLD_P0_Msk (0x10UL) |
| |
| #define | ECAT_ESC_CONFIG_EHLD_P1_Pos (5UL) |
| |
| #define | ECAT_ESC_CONFIG_EHLD_P1_Msk (0x20UL) |
| |
| #define | ECAT_ESC_CONFIG_EHLD_P2_Pos (6UL) |
| |
| #define | ECAT_ESC_CONFIG_EHLD_P2_Msk (0x40UL) |
| |
| #define | ECAT_ESC_CONFIG_EHLD_P3_Pos (7UL) |
| |
| #define | ECAT_ESC_CONFIG_EHLD_P3_Msk (0x80UL) |
| |
| #define | ECAT_PDI_CONFIG_BUS_CLK_Pos (0UL) |
| |
| #define | ECAT_PDI_CONFIG_BUS_CLK_Msk (0x1fUL) |
| |
| #define | ECAT_PDI_CONFIG_OC_BUS_Pos (5UL) |
| |
| #define | ECAT_PDI_CONFIG_OC_BUS_Msk (0xe0UL) |
| |
| #define | ECAT_SYNC_LATCH_CONFIG_SYNC0_POL_Pos (0UL) |
| |
| #define | ECAT_SYNC_LATCH_CONFIG_SYNC0_POL_Msk (0x3UL) |
| |
| #define | ECAT_SYNC_LATCH_CONFIG_SL0_CNF_Pos (2UL) |
| |
| #define | ECAT_SYNC_LATCH_CONFIG_SL0_CNF_Msk (0x4UL) |
| |
| #define | ECAT_SYNC_LATCH_CONFIG_S0_MAP_Pos (3UL) |
| |
| #define | ECAT_SYNC_LATCH_CONFIG_S0_MAP_Msk (0x8UL) |
| |
| #define | ECAT_SYNC_LATCH_CONFIG_SYNC1_POL_Pos (4UL) |
| |
| #define | ECAT_SYNC_LATCH_CONFIG_SYNC1_POL_Msk (0x30UL) |
| |
| #define | ECAT_SYNC_LATCH_CONFIG_SL1_CNF_Pos (6UL) |
| |
| #define | ECAT_SYNC_LATCH_CONFIG_SL1_CNF_Msk (0x40UL) |
| |
| #define | ECAT_SYNC_LATCH_CONFIG_S1_MAP_Pos (7UL) |
| |
| #define | ECAT_SYNC_LATCH_CONFIG_S1_MAP_Msk (0x80UL) |
| |
| #define | ECAT_PDI_EXT_CONFIG_R_Pref_Pos (0UL) |
| |
| #define | ECAT_PDI_EXT_CONFIG_R_Pref_Msk (0x3UL) |
| |
| #define | ECAT_PDI_EXT_CONFIG_SUB_TYPE_Pos (8UL) |
| |
| #define | ECAT_PDI_EXT_CONFIG_SUB_TYPE_Msk (0x700UL) |
| |
| #define | ECAT_EVENT_MASK_DC_LE_MASK_Pos (0UL) |
| |
| #define | ECAT_EVENT_MASK_DC_LE_MASK_Msk (0x1UL) |
| |
| #define | ECAT_EVENT_MASK_DL_SE_MASK_Pos (2UL) |
| |
| #define | ECAT_EVENT_MASK_DL_SE_MASK_Msk (0x4UL) |
| |
| #define | ECAT_EVENT_MASK_AL_SE_MASK_Pos (3UL) |
| |
| #define | ECAT_EVENT_MASK_AL_SE_MASK_Msk (0x8UL) |
| |
| #define | ECAT_EVENT_MASK_MIR_0_MASK_Pos (4UL) |
| |
| #define | ECAT_EVENT_MASK_MIR_0_MASK_Msk (0x10UL) |
| |
| #define | ECAT_EVENT_MASK_MIR_1_MASK_Pos (5UL) |
| |
| #define | ECAT_EVENT_MASK_MIR_1_MASK_Msk (0x20UL) |
| |
| #define | ECAT_EVENT_MASK_MIR_2_MASK_Pos (6UL) |
| |
| #define | ECAT_EVENT_MASK_MIR_2_MASK_Msk (0x40UL) |
| |
| #define | ECAT_EVENT_MASK_MIR_3_MASK_Pos (7UL) |
| |
| #define | ECAT_EVENT_MASK_MIR_3_MASK_Msk (0x80UL) |
| |
| #define | ECAT_EVENT_MASK_MIR_4_MASK_Pos (8UL) |
| |
| #define | ECAT_EVENT_MASK_MIR_4_MASK_Msk (0x100UL) |
| |
| #define | ECAT_EVENT_MASK_MIR_5_MASK_Pos (9UL) |
| |
| #define | ECAT_EVENT_MASK_MIR_5_MASK_Msk (0x200UL) |
| |
| #define | ECAT_EVENT_MASK_MIR_6_MASK_Pos (10UL) |
| |
| #define | ECAT_EVENT_MASK_MIR_6_MASK_Msk (0x400UL) |
| |
| #define | ECAT_EVENT_MASK_MIR_7_MASK_Pos (11UL) |
| |
| #define | ECAT_EVENT_MASK_MIR_7_MASK_Msk (0x800UL) |
| |
| #define | ECAT_AL_EVENT_MASK_AL_CE_MASK_Pos (0UL) |
| |
| #define | ECAT_AL_EVENT_MASK_AL_CE_MASK_Msk (0x1UL) |
| |
| #define | ECAT_AL_EVENT_MASK_DC_LE_MASK_Pos (1UL) |
| |
| #define | ECAT_AL_EVENT_MASK_DC_LE_MASK_Msk (0x2UL) |
| |
| #define | ECAT_AL_EVENT_MASK_ST_S0_MASK_Pos (2UL) |
| |
| #define | ECAT_AL_EVENT_MASK_ST_S0_MASK_Msk (0x4UL) |
| |
| #define | ECAT_AL_EVENT_MASK_ST_S1_MASK_Pos (3UL) |
| |
| #define | ECAT_AL_EVENT_MASK_ST_S1_MASK_Msk (0x8UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SM_A_MASK_Pos (4UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SM_A_MASK_Msk (0x10UL) |
| |
| #define | ECAT_AL_EVENT_MASK_EEP_E_MASK_Pos (5UL) |
| |
| #define | ECAT_AL_EVENT_MASK_EEP_E_MASK_Msk (0x20UL) |
| |
| #define | ECAT_AL_EVENT_MASK_WP_D_MASK_Pos (6UL) |
| |
| #define | ECAT_AL_EVENT_MASK_WP_D_MASK_Msk (0x40UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SMI_0_MASK_Pos (8UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SMI_0_MASK_Msk (0x100UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SMI_1_MASK_Pos (9UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SMI_1_MASK_Msk (0x200UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SMI_2_MASK_Pos (10UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SMI_2_MASK_Msk (0x400UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SMI_3_MASK_Pos (11UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SMI_3_MASK_Msk (0x800UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SMI_4_MASK_Pos (12UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SMI_4_MASK_Msk (0x1000UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SMI_5_MASK_Pos (13UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SMI_5_MASK_Msk (0x2000UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SMI_6_MASK_Pos (14UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SMI_6_MASK_Msk (0x4000UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SMI_7_MASK_Pos (15UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SMI_7_MASK_Msk (0x8000UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SMI_8_MASK_Pos (16UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SMI_8_MASK_Msk (0x10000UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SMI_9_MASK_Pos (17UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SMI_9_MASK_Msk (0x20000UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SMI_10_MASK_Pos (18UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SMI_10_MASK_Msk (0x40000UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SMI_11_MASK_Pos (19UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SMI_11_MASK_Msk (0x80000UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SMI_12_MASK_Pos (20UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SMI_12_MASK_Msk (0x100000UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SMI_13_MASK_Pos (21UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SMI_13_MASK_Msk (0x200000UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SMI_14_MASK_Pos (22UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SMI_14_MASK_Msk (0x400000UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SMI_15_MASK_Pos (23UL) |
| |
| #define | ECAT_AL_EVENT_MASK_SMI_15_MASK_Msk (0x800000UL) |
| |
| #define | ECAT_EVENT_REQ_DC_LE_Pos (0UL) |
| |
| #define | ECAT_EVENT_REQ_DC_LE_Msk (0x1UL) |
| |
| #define | ECAT_EVENT_REQ_DL_SE_Pos (2UL) |
| |
| #define | ECAT_EVENT_REQ_DL_SE_Msk (0x4UL) |
| |
| #define | ECAT_EVENT_REQ_AL_SE_Pos (3UL) |
| |
| #define | ECAT_EVENT_REQ_AL_SE_Msk (0x8UL) |
| |
| #define | ECAT_EVENT_REQ_MIR_0_Pos (4UL) |
| |
| #define | ECAT_EVENT_REQ_MIR_0_Msk (0x10UL) |
| |
| #define | ECAT_EVENT_REQ_MIR_1_Pos (5UL) |
| |
| #define | ECAT_EVENT_REQ_MIR_1_Msk (0x20UL) |
| |
| #define | ECAT_EVENT_REQ_MIR_2_Pos (6UL) |
| |
| #define | ECAT_EVENT_REQ_MIR_2_Msk (0x40UL) |
| |
| #define | ECAT_EVENT_REQ_MIR_3_Pos (7UL) |
| |
| #define | ECAT_EVENT_REQ_MIR_3_Msk (0x80UL) |
| |
| #define | ECAT_EVENT_REQ_MIR_4_Pos (8UL) |
| |
| #define | ECAT_EVENT_REQ_MIR_4_Msk (0x100UL) |
| |
| #define | ECAT_EVENT_REQ_MIR_5_Pos (9UL) |
| |
| #define | ECAT_EVENT_REQ_MIR_5_Msk (0x200UL) |
| |
| #define | ECAT_EVENT_REQ_MIR_6_Pos (10UL) |
| |
| #define | ECAT_EVENT_REQ_MIR_6_Msk (0x400UL) |
| |
| #define | ECAT_EVENT_REQ_MIR_7_Pos (11UL) |
| |
| #define | ECAT_EVENT_REQ_MIR_7_Msk (0x800UL) |
| |
| #define | ECAT_AL_EVENT_REQ_AL_CE_Pos (0UL) |
| |
| #define | ECAT_AL_EVENT_REQ_AL_CE_Msk (0x1UL) |
| |
| #define | ECAT_AL_EVENT_REQ_DC_LE_Pos (1UL) |
| |
| #define | ECAT_AL_EVENT_REQ_DC_LE_Msk (0x2UL) |
| |
| #define | ECAT_AL_EVENT_REQ_ST_S0_Pos (2UL) |
| |
| #define | ECAT_AL_EVENT_REQ_ST_S0_Msk (0x4UL) |
| |
| #define | ECAT_AL_EVENT_REQ_ST_S1_Pos (3UL) |
| |
| #define | ECAT_AL_EVENT_REQ_ST_S1_Msk (0x8UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SM_A_Pos (4UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SM_A_Msk (0x10UL) |
| |
| #define | ECAT_AL_EVENT_REQ_EEP_E_Pos (5UL) |
| |
| #define | ECAT_AL_EVENT_REQ_EEP_E_Msk (0x20UL) |
| |
| #define | ECAT_AL_EVENT_REQ_WP_D_Pos (6UL) |
| |
| #define | ECAT_AL_EVENT_REQ_WP_D_Msk (0x40UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SMI_0_Pos (8UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SMI_0_Msk (0x100UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SMI_1_Pos (9UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SMI_1_Msk (0x200UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SMI_2_Pos (10UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SMI_2_Msk (0x400UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SMI_3_Pos (11UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SMI_3_Msk (0x800UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SMI_4_Pos (12UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SMI_4_Msk (0x1000UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SMI_5_Pos (13UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SMI_5_Msk (0x2000UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SMI_6_Pos (14UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SMI_6_Msk (0x4000UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SMI_7_Pos (15UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SMI_7_Msk (0x8000UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SMI_8_Pos (16UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SMI_8_Msk (0x10000UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SMI_9_Pos (17UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SMI_9_Msk (0x20000UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SMI_10_Pos (18UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SMI_10_Msk (0x40000UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SMI_11_Pos (19UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SMI_11_Msk (0x80000UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SMI_12_Pos (20UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SMI_12_Msk (0x100000UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SMI_13_Pos (21UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SMI_13_Msk (0x200000UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SMI_14_Pos (22UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SMI_14_Msk (0x400000UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SMI_15_Pos (23UL) |
| |
| #define | ECAT_AL_EVENT_REQ_SMI_15_Msk (0x800000UL) |
| |
| #define | ECAT_RX_ERR_COUNT0_INVALID_FRAME_Pos (0UL) |
| |
| #define | ECAT_RX_ERR_COUNT0_INVALID_FRAME_Msk (0xffUL) |
| |
| #define | ECAT_RX_ERR_COUNT0_RX_ERROR_Pos (8UL) |
| |
| #define | ECAT_RX_ERR_COUNT0_RX_ERROR_Msk (0xff00UL) |
| |
| #define | ECAT_RX_ERR_COUNT1_INVALID_FRAME_Pos (0UL) |
| |
| #define | ECAT_RX_ERR_COUNT1_INVALID_FRAME_Msk (0xffUL) |
| |
| #define | ECAT_RX_ERR_COUNT1_RX_ERROR_Pos (8UL) |
| |
| #define | ECAT_RX_ERR_COUNT1_RX_ERROR_Msk (0xff00UL) |
| |
| #define | ECAT_FWD_RX_ERR_COUNT0_FORW_ERROR_Pos (0UL) |
| |
| #define | ECAT_FWD_RX_ERR_COUNT0_FORW_ERROR_Msk (0xffUL) |
| |
| #define | ECAT_FWD_RX_ERR_COUNT1_FORW_ERROR_Pos (0UL) |
| |
| #define | ECAT_FWD_RX_ERR_COUNT1_FORW_ERROR_Msk (0xffUL) |
| |
| #define | ECAT_PROC_ERR_COUNT_UNIT_ERROR_Pos (0UL) |
| |
| #define | ECAT_PROC_ERR_COUNT_UNIT_ERROR_Msk (0xffUL) |
| |
| #define | ECAT_PDI_ERR_COUNT_PDI_ERROR_COUNTER_Pos (0UL) |
| |
| #define | ECAT_PDI_ERR_COUNT_PDI_ERROR_COUNTER_Msk (0xffUL) |
| |
| #define | ECAT_LOST_LINK_COUNT0_LL_COUNTER_Pos (0UL) |
| |
| #define | ECAT_LOST_LINK_COUNT0_LL_COUNTER_Msk (0xffUL) |
| |
| #define | ECAT_LOST_LINK_COUNT1_LL_COUNTER_Pos (0UL) |
| |
| #define | ECAT_LOST_LINK_COUNT1_LL_COUNTER_Msk (0xffUL) |
| |
| #define | ECAT_WD_DIVIDE_WD_DIV_Pos (0UL) |
| |
| #define | ECAT_WD_DIVIDE_WD_DIV_Msk (0xffffUL) |
| |
| #define | ECAT_WD_TIME_PDI_WD_TIME_PDI_Pos (0UL) |
| |
| #define | ECAT_WD_TIME_PDI_WD_TIME_PDI_Msk (0xffffUL) |
| |
| #define | ECAT_WD_TIME_PDATA_WD_TIME_PD_Pos (0UL) |
| |
| #define | ECAT_WD_TIME_PDATA_WD_TIME_PD_Msk (0xffffUL) |
| |
| #define | ECAT_WD_STAT_PDATA_WD_STAT_PD_Pos (0UL) |
| |
| #define | ECAT_WD_STAT_PDATA_WD_STAT_PD_Msk (0x1UL) |
| |
| #define | ECAT_WD_COUNT_PDATA_WD_COUNTER_PD_Pos (0UL) |
| |
| #define | ECAT_WD_COUNT_PDATA_WD_COUNTER_PD_Msk (0xffUL) |
| |
| #define | ECAT_WD_COUNT_PDI_WD_COUNTER_PDI_Pos (0UL) |
| |
| #define | ECAT_WD_COUNT_PDI_WD_COUNTER_PDI_Msk (0xffUL) |
| |
| #define | ECAT_EEP_CONF_TO_PDI_Pos (0UL) |
| |
| #define | ECAT_EEP_CONF_TO_PDI_Msk (0x1UL) |
| |
| #define | ECAT_EEP_CONF_FORCE_Pos (1UL) |
| |
| #define | ECAT_EEP_CONF_FORCE_Msk (0x2UL) |
| |
| #define | ECAT_EEP_STATE_ACCESS_Pos (0UL) |
| |
| #define | ECAT_EEP_STATE_ACCESS_Msk (0x1UL) |
| |
| #define | ECAT_EEP_CONT_STAT_W_EN_Pos (0UL) |
| |
| #define | ECAT_EEP_CONT_STAT_W_EN_Msk (0x1UL) |
| |
| #define | ECAT_EEP_CONT_STAT_EMUL_Pos (5UL) |
| |
| #define | ECAT_EEP_CONT_STAT_EMUL_Msk (0x20UL) |
| |
| #define | ECAT_EEP_CONT_STAT_BYTES_Pos (6UL) |
| |
| #define | ECAT_EEP_CONT_STAT_BYTES_Msk (0x40UL) |
| |
| #define | ECAT_EEP_CONT_STAT_ALG_Pos (7UL) |
| |
| #define | ECAT_EEP_CONT_STAT_ALG_Msk (0x80UL) |
| |
| #define | ECAT_EEP_CONT_STAT_CMD_REG_Pos (8UL) |
| |
| #define | ECAT_EEP_CONT_STAT_CMD_REG_Msk (0x700UL) |
| |
| #define | ECAT_EEP_CONT_STAT_ERROR_Pos (11UL) |
| |
| #define | ECAT_EEP_CONT_STAT_ERROR_Msk (0x800UL) |
| |
| #define | ECAT_EEP_CONT_STAT_L_STAT_Pos (12UL) |
| |
| #define | ECAT_EEP_CONT_STAT_L_STAT_Msk (0x1000UL) |
| |
| #define | ECAT_EEP_CONT_STAT_ERROR_AC_Pos (13UL) |
| |
| #define | ECAT_EEP_CONT_STAT_ERROR_AC_Msk (0x2000UL) |
| |
| #define | ECAT_EEP_CONT_STAT_ERROR_WE_Pos (14UL) |
| |
| #define | ECAT_EEP_CONT_STAT_ERROR_WE_Msk (0x4000UL) |
| |
| #define | ECAT_EEP_CONT_STAT_BUSY_Pos (15UL) |
| |
| #define | ECAT_EEP_CONT_STAT_BUSY_Msk (0x8000UL) |
| |
| #define | ECAT_EEP_ADR_EEPROM_ADDR_Pos (0UL) |
| |
| #define | ECAT_EEP_ADR_EEPROM_ADDR_Msk (0xffffffffUL) |
| |
| #define | ECAT_EEP_DATA_EEP_DATA_Pos (0UL) |
| |
| #define | ECAT_EEP_DATA_EEP_DATA_Msk (0xffffffffUL) |
| |
| #define | ECAT_MII_CONT_STAT_W_EN_Pos (0UL) |
| |
| #define | ECAT_MII_CONT_STAT_W_EN_Msk (0x1UL) |
| |
| #define | ECAT_MII_CONT_STAT_MIC_PDI_Pos (1UL) |
| |
| #define | ECAT_MII_CONT_STAT_MIC_PDI_Msk (0x2UL) |
| |
| #define | ECAT_MII_CONT_STAT_MI_LD_Pos (2UL) |
| |
| #define | ECAT_MII_CONT_STAT_MI_LD_Msk (0x4UL) |
| |
| #define | ECAT_MII_CONT_STAT_PHY_ADDR_Pos (3UL) |
| |
| #define | ECAT_MII_CONT_STAT_PHY_ADDR_Msk (0xf8UL) |
| |
| #define | ECAT_MII_CONT_STAT_CMD_REG_Pos (8UL) |
| |
| #define | ECAT_MII_CONT_STAT_CMD_REG_Msk (0x300UL) |
| |
| #define | ECAT_MII_CONT_STAT_ERROR_Pos (14UL) |
| |
| #define | ECAT_MII_CONT_STAT_ERROR_Msk (0x4000UL) |
| |
| #define | ECAT_MII_CONT_STAT_BUSY_Pos (15UL) |
| |
| #define | ECAT_MII_CONT_STAT_BUSY_Msk (0x8000UL) |
| |
| #define | ECAT_MII_PHY_ADR_PHY_ADDR_Pos (0UL) |
| |
| #define | ECAT_MII_PHY_ADR_PHY_ADDR_Msk (0x1fUL) |
| |
| #define | ECAT_MII_PHY_ADR_PHY_CADDR_Pos (7UL) |
| |
| #define | ECAT_MII_PHY_ADR_PHY_CADDR_Msk (0x80UL) |
| |
| #define | ECAT_MII_PHY_REG_ADR_PHY_REG_ADDR_Pos (0UL) |
| |
| #define | ECAT_MII_PHY_REG_ADR_PHY_REG_ADDR_Msk (0x1fUL) |
| |
| #define | ECAT_MII_PHY_DATA_PHY_RW_DATA_Pos (0UL) |
| |
| #define | ECAT_MII_PHY_DATA_PHY_RW_DATA_Msk (0xffffUL) |
| |
| #define | ECAT_MII_ECAT_ACS_STATE_EN_ACS_MII_BY_PDI_Pos (0UL) |
| |
| #define | ECAT_MII_ECAT_ACS_STATE_EN_ACS_MII_BY_PDI_Msk (0x1UL) |
| |
| #define | ECAT_MII_PDI_ACS_STATE_ACS_MII_BY_PDI_Pos (0UL) |
| |
| #define | ECAT_MII_PDI_ACS_STATE_ACS_MII_BY_PDI_Msk (0x1UL) |
| |
| #define | ECAT_MII_PDI_ACS_STATE_FORCE_PDI_ACS_S_Pos (1UL) |
| |
| #define | ECAT_MII_PDI_ACS_STATE_FORCE_PDI_ACS_S_Msk (0x2UL) |
| |
| #define | ECAT_DC_RCV_TIME_PORT0_LOCAL_TIME_P0_Pos (0UL) |
| |
| #define | ECAT_DC_RCV_TIME_PORT0_LOCAL_TIME_P0_Msk (0xffffffffUL) |
| |
| #define | ECAT_DC_RCV_TIME_PORT1_LOCAL_TIME_P1_Pos (0UL) |
| |
| #define | ECAT_DC_RCV_TIME_PORT1_LOCAL_TIME_P1_Msk (0xffffffffUL) |
| |
| #define | ECAT_DC_SYS_TIME_WRITE_ACCESS_WRITEMode_Pos (0UL) |
| |
| #define | ECAT_DC_SYS_TIME_WRITE_ACCESS_WRITEMode_Msk (0xffffffffUL) |
| |
| #define | ECAT_DC_SYS_TIME_READ_ACCESS_READMode_Pos (0UL) |
| |
| #define | ECAT_DC_SYS_TIME_READ_ACCESS_READMode_Msk (0xffffffffUL) |
| |
| #define | ECAT_RECEIVE_TIME_PU_RECEIVE_TIME_PU_Pos (0UL) |
| |
| #define | ECAT_RECEIVE_TIME_PU_RECEIVE_TIME_PU_Msk (0xffffffffUL) |
| |
| #define | ECAT_DC_SYS_TIME_OFFSET_DC_SYS_TIME_OFFSET_Pos (0UL) |
| |
| #define | ECAT_DC_SYS_TIME_OFFSET_DC_SYS_TIME_OFFSET_Msk (0xffffffffUL) |
| |
| #define | ECAT_DC_SYS_TIME_DELAY_CLK_DELAY_Pos (0UL) |
| |
| #define | ECAT_DC_SYS_TIME_DELAY_CLK_DELAY_Msk (0xffffffffUL) |
| |
| #define | ECAT_DC_SYS_TIME_DIFF_TIME_DIF_Pos (0UL) |
| |
| #define | ECAT_DC_SYS_TIME_DIFF_TIME_DIF_Msk (0x7fffffffUL) |
| |
| #define | ECAT_DC_SYS_TIME_DIFF_CPY_Pos (31UL) |
| |
| #define | ECAT_DC_SYS_TIME_DIFF_CPY_Msk (0x80000000UL) |
| |
| #define | ECAT_DC_SPEED_COUNT_START_COUNT_START_Pos (0UL) |
| |
| #define | ECAT_DC_SPEED_COUNT_START_COUNT_START_Msk (0x7fffUL) |
| |
| #define | ECAT_DC_SPEED_COUNT_DIFF_DEVIATION_Pos (0UL) |
| |
| #define | ECAT_DC_SPEED_COUNT_DIFF_DEVIATION_Msk (0xffffUL) |
| |
| #define | ECAT_DC_SYS_TIME_FIL_DEPTH_FILTER_DEPTH_Pos (0UL) |
| |
| #define | ECAT_DC_SYS_TIME_FIL_DEPTH_FILTER_DEPTH_Msk (0xfUL) |
| |
| #define | ECAT_DC_SPEED_COUNT_FIL_DEPTH_FILTER_DEPTH_Pos (0UL) |
| |
| #define | ECAT_DC_SPEED_COUNT_FIL_DEPTH_FILTER_DEPTH_Msk (0xfUL) |
| |
| #define | ECAT_DC_CYC_CONT_SYNC_Pos (0UL) |
| |
| #define | ECAT_DC_CYC_CONT_SYNC_Msk (0x1UL) |
| |
| #define | ECAT_DC_CYC_CONT_LATCH_U0_Pos (4UL) |
| |
| #define | ECAT_DC_CYC_CONT_LATCH_U0_Msk (0x10UL) |
| |
| #define | ECAT_DC_CYC_CONT_LATCH_U1_Pos (5UL) |
| |
| #define | ECAT_DC_CYC_CONT_LATCH_U1_Msk (0x20UL) |
| |
| #define | ECAT_DC_ACT_SYNC_OUT_Pos (0UL) |
| |
| #define | ECAT_DC_ACT_SYNC_OUT_Msk (0x1UL) |
| |
| #define | ECAT_DC_ACT_SYNC_0_Pos (1UL) |
| |
| #define | ECAT_DC_ACT_SYNC_0_Msk (0x2UL) |
| |
| #define | ECAT_DC_ACT_SYNC_1_Pos (2UL) |
| |
| #define | ECAT_DC_ACT_SYNC_1_Msk (0x4UL) |
| |
| #define | ECAT_DC_PULSE_LEN_PULS_LENGTH_Pos (0UL) |
| |
| #define | ECAT_DC_PULSE_LEN_PULS_LENGTH_Msk (0xffffUL) |
| |
| #define | ECAT_DC_ACT_STAT_S0_ACK_STATE_Pos (0UL) |
| |
| #define | ECAT_DC_ACT_STAT_S0_ACK_STATE_Msk (0x1UL) |
| |
| #define | ECAT_DC_ACT_STAT_S1_ACK_STATE_Pos (1UL) |
| |
| #define | ECAT_DC_ACT_STAT_S1_ACK_STATE_Msk (0x2UL) |
| |
| #define | ECAT_DC_ACT_STAT_S_TIME_Pos (2UL) |
| |
| #define | ECAT_DC_ACT_STAT_S_TIME_Msk (0x4UL) |
| |
| #define | ECAT_DC_SYNC0_STAT_S0_STATE_Pos (0UL) |
| |
| #define | ECAT_DC_SYNC0_STAT_S0_STATE_Msk (0x1UL) |
| |
| #define | ECAT_DC_SYNC1_STAT_S1_STATE_Pos (0UL) |
| |
| #define | ECAT_DC_SYNC1_STAT_S1_STATE_Msk (0x1UL) |
| |
| #define | ECAT_DC_CYC_START_TIME_DC_CYC_START_TIME_Pos (0UL) |
| |
| #define | ECAT_DC_CYC_START_TIME_DC_CYC_START_TIME_Msk (0xffffffffUL) |
| |
| #define | ECAT_DC_NEXT_SYNC1_PULSE_DC_NEXT_SYNC1_PULSE_Pos (0UL) |
| |
| #define | ECAT_DC_NEXT_SYNC1_PULSE_DC_NEXT_SYNC1_PULSE_Msk (0xffffffffUL) |
| |
| #define | ECAT_DC_SYNC0_CYC_TIME_TIME_BETWEEN_SYNC0_Pos (0UL) |
| |
| #define | ECAT_DC_SYNC0_CYC_TIME_TIME_BETWEEN_SYNC0_Msk (0xffffffffUL) |
| |
| #define | ECAT_DC_SYNC1_CYC_TIME_TIME_SYNC1_SYNC0_Pos (0UL) |
| |
| #define | ECAT_DC_SYNC1_CYC_TIME_TIME_SYNC1_SYNC0_Msk (0xffffffffUL) |
| |
| #define | ECAT_DC_LATCH0_CONT_L0_POS_Pos (0UL) |
| |
| #define | ECAT_DC_LATCH0_CONT_L0_POS_Msk (0x1UL) |
| |
| #define | ECAT_DC_LATCH0_CONT_L0_NEG_Pos (1UL) |
| |
| #define | ECAT_DC_LATCH0_CONT_L0_NEG_Msk (0x2UL) |
| |
| #define | ECAT_DC_LATCH1_CONT_L1_POS_Pos (0UL) |
| |
| #define | ECAT_DC_LATCH1_CONT_L1_POS_Msk (0x1UL) |
| |
| #define | ECAT_DC_LATCH1_CONT_L1_NEG_Pos (1UL) |
| |
| #define | ECAT_DC_LATCH1_CONT_L1_NEG_Msk (0x2UL) |
| |
| #define | ECAT_DC_LATCH0_STAT_EV_L0_POS_Pos (0UL) |
| |
| #define | ECAT_DC_LATCH0_STAT_EV_L0_POS_Msk (0x1UL) |
| |
| #define | ECAT_DC_LATCH0_STAT_EV_L0_NEG_Pos (1UL) |
| |
| #define | ECAT_DC_LATCH0_STAT_EV_L0_NEG_Msk (0x2UL) |
| |
| #define | ECAT_DC_LATCH0_STAT_L0_PIN_Pos (2UL) |
| |
| #define | ECAT_DC_LATCH0_STAT_L0_PIN_Msk (0x4UL) |
| |
| #define | ECAT_DC_LATCH1_STAT_EV_L1_POS_Pos (0UL) |
| |
| #define | ECAT_DC_LATCH1_STAT_EV_L1_POS_Msk (0x1UL) |
| |
| #define | ECAT_DC_LATCH1_STAT_EV_L1_NEG_Pos (1UL) |
| |
| #define | ECAT_DC_LATCH1_STAT_EV_L1_NEG_Msk (0x2UL) |
| |
| #define | ECAT_DC_LATCH1_STAT_L1_PIN_Pos (2UL) |
| |
| #define | ECAT_DC_LATCH1_STAT_L1_PIN_Msk (0x4UL) |
| |
| #define | ECAT_DC_LATCH0_TIME_POS_DC_LATCH0_TIME_POS_Pos (0UL) |
| |
| #define | ECAT_DC_LATCH0_TIME_POS_DC_LATCH0_TIME_POS_Msk (0xffffffffUL) |
| |
| #define | ECAT_DC_LATCH0_TIME_NEG_DC_LATCH0_TIME_NEG_Pos (0UL) |
| |
| #define | ECAT_DC_LATCH0_TIME_NEG_DC_LATCH0_TIME_NEG_Msk (0xffffffffUL) |
| |
| #define | ECAT_DC_LATCH1_TIME_POS_DC_LATCH1_TIME_POS_Pos (0UL) |
| |
| #define | ECAT_DC_LATCH1_TIME_POS_DC_LATCH1_TIME_POS_Msk (0xffffffffUL) |
| |
| #define | ECAT_DC_LATCH1_TIME_NEG_DC_LATCH1_TIME_NEG_Pos (0UL) |
| |
| #define | ECAT_DC_LATCH1_TIME_NEG_DC_LATCH1_TIME_NEG_Msk (0xffffffffUL) |
| |
| #define | ECAT_DC_ECAT_CNG_EV_TIME_ECAT_CNG_EV_TIME_Pos (0UL) |
| |
| #define | ECAT_DC_ECAT_CNG_EV_TIME_ECAT_CNG_EV_TIME_Msk (0xffffffffUL) |
| |
| #define | ECAT_DC_PDI_START_EV_TIME_PDI_START_EV_TIME_Pos (0UL) |
| |
| #define | ECAT_DC_PDI_START_EV_TIME_PDI_START_EV_TIME_Msk (0xffffffffUL) |
| |
| #define | ECAT_DC_PDI_CNG_EV_TIME_PDI_CNG_EV_TIME_Pos (0UL) |
| |
| #define | ECAT_DC_PDI_CNG_EV_TIME_PDI_CNG_EV_TIME_Msk (0xffffffffUL) |
| |
| #define | ECAT_ID_MOD_REV_Pos (0UL) |
| |
| #define | ECAT_ID_MOD_REV_Msk (0xffUL) |
| |
| #define | ECAT_ID_MOD_TYPE_Pos (8UL) |
| |
| #define | ECAT_ID_MOD_TYPE_Msk (0xff00UL) |
| |
| #define | ECAT_ID_MOD_NUMBER_Pos (16UL) |
| |
| #define | ECAT_ID_MOD_NUMBER_Msk (0xffff0000UL) |
| |
| #define | ECAT_STATUS_PARERR_Pos (0UL) |
| |
| #define | ECAT_STATUS_PARERR_Msk (0x1UL) |
| |
| #define | USB_GOTGCTL_SesReqScs_Pos (0UL) |
| |
| #define | USB_GOTGCTL_SesReqScs_Msk (0x1UL) |
| |
| #define | USB_GOTGCTL_SesReq_Pos (1UL) |
| |
| #define | USB_GOTGCTL_SesReq_Msk (0x2UL) |
| |
| #define | USB_GOTGCTL_VbvalidOvEn_Pos (2UL) |
| |
| #define | USB_GOTGCTL_VbvalidOvEn_Msk (0x4UL) |
| |
| #define | USB_GOTGCTL_VbvalidOvVal_Pos (3UL) |
| |
| #define | USB_GOTGCTL_VbvalidOvVal_Msk (0x8UL) |
| |
| #define | USB_GOTGCTL_AvalidOvEn_Pos (4UL) |
| |
| #define | USB_GOTGCTL_AvalidOvEn_Msk (0x10UL) |
| |
| #define | USB_GOTGCTL_AvalidOvVal_Pos (5UL) |
| |
| #define | USB_GOTGCTL_AvalidOvVal_Msk (0x20UL) |
| |
| #define | USB_GOTGCTL_BvalidOvEn_Pos (6UL) |
| |
| #define | USB_GOTGCTL_BvalidOvEn_Msk (0x40UL) |
| |
| #define | USB_GOTGCTL_BvalidOvVal_Pos (7UL) |
| |
| #define | USB_GOTGCTL_BvalidOvVal_Msk (0x80UL) |
| |
| #define | USB_GOTGCTL_HstNegScs_Pos (8UL) |
| |
| #define | USB_GOTGCTL_HstNegScs_Msk (0x100UL) |
| |
| #define | USB_GOTGCTL_HNPReq_Pos (9UL) |
| |
| #define | USB_GOTGCTL_HNPReq_Msk (0x200UL) |
| |
| #define | USB_GOTGCTL_HstSetHNPEn_Pos (10UL) |
| |
| #define | USB_GOTGCTL_HstSetHNPEn_Msk (0x400UL) |
| |
| #define | USB_GOTGCTL_DevHNPEn_Pos (11UL) |
| |
| #define | USB_GOTGCTL_DevHNPEn_Msk (0x800UL) |
| |
| #define | USB_GOTGCTL_ConlDSts_Pos (16UL) |
| |
| #define | USB_GOTGCTL_ConlDSts_Msk (0x10000UL) |
| |
| #define | USB_GOTGCTL_DbncTime_Pos (17UL) |
| |
| #define | USB_GOTGCTL_DbncTime_Msk (0x20000UL) |
| |
| #define | USB_GOTGCTL_ASesVId_Pos (18UL) |
| |
| #define | USB_GOTGCTL_ASesVId_Msk (0x40000UL) |
| |
| #define | USB_GOTGCTL_BSesVld_Pos (19UL) |
| |
| #define | USB_GOTGCTL_BSesVld_Msk (0x80000UL) |
| |
| #define | USB_GOTGCTL_OTGVer_Pos (20UL) |
| |
| #define | USB_GOTGCTL_OTGVer_Msk (0x100000UL) |
| |
| #define | USB_GOTGINT_SesEndDet_Pos (2UL) |
| |
| #define | USB_GOTGINT_SesEndDet_Msk (0x4UL) |
| |
| #define | USB_GOTGINT_SesReqSucStsChng_Pos (8UL) |
| |
| #define | USB_GOTGINT_SesReqSucStsChng_Msk (0x100UL) |
| |
| #define | USB_GOTGINT_HstNegSucStsChng_Pos (9UL) |
| |
| #define | USB_GOTGINT_HstNegSucStsChng_Msk (0x200UL) |
| |
| #define | USB_GOTGINT_HstNegDet_Pos (17UL) |
| |
| #define | USB_GOTGINT_HstNegDet_Msk (0x20000UL) |
| |
| #define | USB_GOTGINT_ADevTOUTChg_Pos (18UL) |
| |
| #define | USB_GOTGINT_ADevTOUTChg_Msk (0x40000UL) |
| |
| #define | USB_GOTGINT_DbnceDone_Pos (19UL) |
| |
| #define | USB_GOTGINT_DbnceDone_Msk (0x80000UL) |
| |
| #define | USB_GAHBCFG_GlblIntrMsk_Pos (0UL) |
| |
| #define | USB_GAHBCFG_GlblIntrMsk_Msk (0x1UL) |
| |
| #define | USB_GAHBCFG_HBstLen_Pos (1UL) |
| |
| #define | USB_GAHBCFG_HBstLen_Msk (0x1eUL) |
| |
| #define | USB_GAHBCFG_DMAEn_Pos (5UL) |
| |
| #define | USB_GAHBCFG_DMAEn_Msk (0x20UL) |
| |
| #define | USB_GAHBCFG_NPTxFEmpLvl_Pos (7UL) |
| |
| #define | USB_GAHBCFG_NPTxFEmpLvl_Msk (0x80UL) |
| |
| #define | USB_GAHBCFG_PTxFEmpLvl_Pos (8UL) |
| |
| #define | USB_GAHBCFG_PTxFEmpLvl_Msk (0x100UL) |
| |
| #define | USB_GAHBCFG_AHBSingle_Pos (23UL) |
| |
| #define | USB_GAHBCFG_AHBSingle_Msk (0x800000UL) |
| |
| #define | USB_GUSBCFG_TOutCal_Pos (0UL) |
| |
| #define | USB_GUSBCFG_TOutCal_Msk (0x7UL) |
| |
| #define | USB_GUSBCFG_PHYSel_Pos (6UL) |
| |
| #define | USB_GUSBCFG_PHYSel_Msk (0x40UL) |
| |
| #define | USB_GUSBCFG_SRPCap_Pos (8UL) |
| |
| #define | USB_GUSBCFG_SRPCap_Msk (0x100UL) |
| |
| #define | USB_GUSBCFG_HNPCap_Pos (9UL) |
| |
| #define | USB_GUSBCFG_HNPCap_Msk (0x200UL) |
| |
| #define | USB_GUSBCFG_USBTrdTim_Pos (10UL) |
| |
| #define | USB_GUSBCFG_USBTrdTim_Msk (0x3c00UL) |
| |
| #define | USB_GUSBCFG_OtgI2CSel_Pos (16UL) |
| |
| #define | USB_GUSBCFG_OtgI2CSel_Msk (0x10000UL) |
| |
| #define | USB_GUSBCFG_TxEndDelay_Pos (28UL) |
| |
| #define | USB_GUSBCFG_TxEndDelay_Msk (0x10000000UL) |
| |
| #define | USB_GUSBCFG_ForceHstMode_Pos (29UL) |
| |
| #define | USB_GUSBCFG_ForceHstMode_Msk (0x20000000UL) |
| |
| #define | USB_GUSBCFG_ForceDevMode_Pos (30UL) |
| |
| #define | USB_GUSBCFG_ForceDevMode_Msk (0x40000000UL) |
| |
| #define | USB_GUSBCFG_CTP_Pos (31UL) |
| |
| #define | USB_GUSBCFG_CTP_Msk (0x80000000UL) |
| |
| #define | USB_GRSTCTL_CSftRst_Pos (0UL) |
| |
| #define | USB_GRSTCTL_CSftRst_Msk (0x1UL) |
| |
| #define | USB_GRSTCTL_FrmCntrRst_Pos (2UL) |
| |
| #define | USB_GRSTCTL_FrmCntrRst_Msk (0x4UL) |
| |
| #define | USB_GRSTCTL_RxFFlsh_Pos (4UL) |
| |
| #define | USB_GRSTCTL_RxFFlsh_Msk (0x10UL) |
| |
| #define | USB_GRSTCTL_TxFFlsh_Pos (5UL) |
| |
| #define | USB_GRSTCTL_TxFFlsh_Msk (0x20UL) |
| |
| #define | USB_GRSTCTL_TxFNum_Pos (6UL) |
| |
| #define | USB_GRSTCTL_TxFNum_Msk (0x7c0UL) |
| |
| #define | USB_GRSTCTL_DMAReq_Pos (30UL) |
| |
| #define | USB_GRSTCTL_DMAReq_Msk (0x40000000UL) |
| |
| #define | USB_GRSTCTL_AHBIdle_Pos (31UL) |
| |
| #define | USB_GRSTCTL_AHBIdle_Msk (0x80000000UL) |
| |
| #define | USB_GINTSTS_HOSTMODE_CurMod_Pos (0UL) |
| |
| #define | USB_GINTSTS_HOSTMODE_CurMod_Msk (0x1UL) |
| |
| #define | USB_GINTSTS_HOSTMODE_ModeMis_Pos (1UL) |
| |
| #define | USB_GINTSTS_HOSTMODE_ModeMis_Msk (0x2UL) |
| |
| #define | USB_GINTSTS_HOSTMODE_OTGInt_Pos (2UL) |
| |
| #define | USB_GINTSTS_HOSTMODE_OTGInt_Msk (0x4UL) |
| |
| #define | USB_GINTSTS_HOSTMODE_Sof_Pos (3UL) |
| |
| #define | USB_GINTSTS_HOSTMODE_Sof_Msk (0x8UL) |
| |
| #define | USB_GINTSTS_HOSTMODE_RxFLvl_Pos (4UL) |
| |
| #define | USB_GINTSTS_HOSTMODE_RxFLvl_Msk (0x10UL) |
| |
| #define | USB_GINTSTS_HOSTMODE_incomplP_Pos (21UL) |
| |
| #define | USB_GINTSTS_HOSTMODE_incomplP_Msk (0x200000UL) |
| |
| #define | USB_GINTSTS_HOSTMODE_PrtInt_Pos (24UL) |
| |
| #define | USB_GINTSTS_HOSTMODE_PrtInt_Msk (0x1000000UL) |
| |
| #define | USB_GINTSTS_HOSTMODE_HChInt_Pos (25UL) |
| |
| #define | USB_GINTSTS_HOSTMODE_HChInt_Msk (0x2000000UL) |
| |
| #define | USB_GINTSTS_HOSTMODE_PTxFEmp_Pos (26UL) |
| |
| #define | USB_GINTSTS_HOSTMODE_PTxFEmp_Msk (0x4000000UL) |
| |
| #define | USB_GINTSTS_HOSTMODE_ConIDStsChng_Pos (28UL) |
| |
| #define | USB_GINTSTS_HOSTMODE_ConIDStsChng_Msk (0x10000000UL) |
| |
| #define | USB_GINTSTS_HOSTMODE_DisconnInt_Pos (29UL) |
| |
| #define | USB_GINTSTS_HOSTMODE_DisconnInt_Msk (0x20000000UL) |
| |
| #define | USB_GINTSTS_HOSTMODE_SessReqInt_Pos (30UL) |
| |
| #define | USB_GINTSTS_HOSTMODE_SessReqInt_Msk (0x40000000UL) |
| |
| #define | USB_GINTSTS_HOSTMODE_WkUpInt_Pos (31UL) |
| |
| #define | USB_GINTSTS_HOSTMODE_WkUpInt_Msk (0x80000000UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_CurMod_Pos (0UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_CurMod_Msk (0x1UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_ModeMis_Pos (1UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_ModeMis_Msk (0x2UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_OTGInt_Pos (2UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_OTGInt_Msk (0x4UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_Sof_Pos (3UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_Sof_Msk (0x8UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_RxFLvl_Pos (4UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_RxFLvl_Msk (0x10UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_GINNakEff_Pos (6UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_GINNakEff_Msk (0x40UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_GOUTNakEff_Pos (7UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_GOUTNakEff_Msk (0x80UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_ErlySusp_Pos (10UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_ErlySusp_Msk (0x400UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_USBSusp_Pos (11UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_USBSusp_Msk (0x800UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_USBRst_Pos (12UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_USBRst_Msk (0x1000UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_EnumDone_Pos (13UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_EnumDone_Msk (0x2000UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_ISOOutDrop_Pos (14UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_ISOOutDrop_Msk (0x4000UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_EOPF_Pos (15UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_EOPF_Msk (0x8000UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_IEPInt_Pos (18UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_IEPInt_Msk (0x40000UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_OEPInt_Pos (19UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_OEPInt_Msk (0x80000UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_incompISOIN_Pos (20UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_incompISOIN_Msk (0x100000UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_incomplSOOUT_Pos (21UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_incomplSOOUT_Msk (0x200000UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_ConIDStsChng_Pos (28UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_ConIDStsChng_Msk (0x10000000UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_SessReqInt_Pos (30UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_SessReqInt_Msk (0x40000000UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_WkUpInt_Pos (31UL) |
| |
| #define | USB_GINTSTS_DEVICEMODE_WkUpInt_Msk (0x80000000UL) |
| |
| #define | USB_GINTMSK_HOSTMODE_ModeMisMsk_Pos (1UL) |
| |
| #define | USB_GINTMSK_HOSTMODE_ModeMisMsk_Msk (0x2UL) |
| |
| #define | USB_GINTMSK_HOSTMODE_OTGIntMsk_Pos (2UL) |
| |
| #define | USB_GINTMSK_HOSTMODE_OTGIntMsk_Msk (0x4UL) |
| |
| #define | USB_GINTMSK_HOSTMODE_SofMsk_Pos (3UL) |
| |
| #define | USB_GINTMSK_HOSTMODE_SofMsk_Msk (0x8UL) |
| |
| #define | USB_GINTMSK_HOSTMODE_RxFLvlMsk_Pos (4UL) |
| |
| #define | USB_GINTMSK_HOSTMODE_RxFLvlMsk_Msk (0x10UL) |
| |
| #define | USB_GINTMSK_HOSTMODE_incomplPMsk_Pos (21UL) |
| |
| #define | USB_GINTMSK_HOSTMODE_incomplPMsk_Msk (0x200000UL) |
| |
| #define | USB_GINTMSK_HOSTMODE_PrtIntMsk_Pos (24UL) |
| |
| #define | USB_GINTMSK_HOSTMODE_PrtIntMsk_Msk (0x1000000UL) |
| |
| #define | USB_GINTMSK_HOSTMODE_HChIntMsk_Pos (25UL) |
| |
| #define | USB_GINTMSK_HOSTMODE_HChIntMsk_Msk (0x2000000UL) |
| |
| #define | USB_GINTMSK_HOSTMODE_PTxFEmpMsk_Pos (26UL) |
| |
| #define | USB_GINTMSK_HOSTMODE_PTxFEmpMsk_Msk (0x4000000UL) |
| |
| #define | USB_GINTMSK_HOSTMODE_ConIDStsChngMsk_Pos (28UL) |
| |
| #define | USB_GINTMSK_HOSTMODE_ConIDStsChngMsk_Msk (0x10000000UL) |
| |
| #define | USB_GINTMSK_HOSTMODE_DisconnIntMsk_Pos (29UL) |
| |
| #define | USB_GINTMSK_HOSTMODE_DisconnIntMsk_Msk (0x20000000UL) |
| |
| #define | USB_GINTMSK_HOSTMODE_SessReqIntMsk_Pos (30UL) |
| |
| #define | USB_GINTMSK_HOSTMODE_SessReqIntMsk_Msk (0x40000000UL) |
| |
| #define | USB_GINTMSK_HOSTMODE_WkUpIntMsk_Pos (31UL) |
| |
| #define | USB_GINTMSK_HOSTMODE_WkUpIntMsk_Msk (0x80000000UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_ModeMisMsk_Pos (1UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_ModeMisMsk_Msk (0x2UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_OTGIntMsk_Pos (2UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_OTGIntMsk_Msk (0x4UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_SofMsk_Pos (3UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_SofMsk_Msk (0x8UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_RxFLvlMsk_Pos (4UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_RxFLvlMsk_Msk (0x10UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_GINNakEffMsk_Pos (6UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_GINNakEffMsk_Msk (0x40UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_GOUTNakEffMsk_Pos (7UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_GOUTNakEffMsk_Msk (0x80UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_ErlySuspMsk_Pos (10UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_ErlySuspMsk_Msk (0x400UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_USBSuspMsk_Pos (11UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_USBSuspMsk_Msk (0x800UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_USBRstMsk_Pos (12UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_USBRstMsk_Msk (0x1000UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_EnumDoneMsk_Pos (13UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_EnumDoneMsk_Msk (0x2000UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_ISOOutDropMsk_Pos (14UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_ISOOutDropMsk_Msk (0x4000UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_EOPFMsk_Pos (15UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_EOPFMsk_Msk (0x8000UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_IEPIntMsk_Pos (18UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_IEPIntMsk_Msk (0x40000UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_OEPIntMsk_Pos (19UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_OEPIntMsk_Msk (0x80000UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_incompISOINMsk_Pos (20UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_incompISOINMsk_Msk (0x100000UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_incomplSOOUTMsk_Pos (21UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_incomplSOOUTMsk_Msk (0x200000UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_ConIDStsChngMsk_Pos (28UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_ConIDStsChngMsk_Msk (0x10000000UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_DisconnIntMsk_Pos (29UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_DisconnIntMsk_Msk (0x20000000UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_SessReqIntMsk_Pos (30UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_SessReqIntMsk_Msk (0x40000000UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_WkUpIntMsk_Pos (31UL) |
| |
| #define | USB_GINTMSK_DEVICEMODE_WkUpIntMsk_Msk (0x80000000UL) |
| |
| #define | USB_GRXSTSR_HOSTMODE_ChNum_Pos (0UL) |
| |
| #define | USB_GRXSTSR_HOSTMODE_ChNum_Msk (0xfUL) |
| |
| #define | USB_GRXSTSR_HOSTMODE_BCnt_Pos (4UL) |
| |
| #define | USB_GRXSTSR_HOSTMODE_BCnt_Msk (0x7ff0UL) |
| |
| #define | USB_GRXSTSR_HOSTMODE_DPID_Pos (15UL) |
| |
| #define | USB_GRXSTSR_HOSTMODE_DPID_Msk (0x18000UL) |
| |
| #define | USB_GRXSTSR_HOSTMODE_PktSts_Pos (17UL) |
| |
| #define | USB_GRXSTSR_HOSTMODE_PktSts_Msk (0x1e0000UL) |
| |
| #define | USB_GRXSTSR_DEVICEMODE_EPNum_Pos (0UL) |
| |
| #define | USB_GRXSTSR_DEVICEMODE_EPNum_Msk (0xfUL) |
| |
| #define | USB_GRXSTSR_DEVICEMODE_BCnt_Pos (4UL) |
| |
| #define | USB_GRXSTSR_DEVICEMODE_BCnt_Msk (0x7ff0UL) |
| |
| #define | USB_GRXSTSR_DEVICEMODE_DPID_Pos (15UL) |
| |
| #define | USB_GRXSTSR_DEVICEMODE_DPID_Msk (0x18000UL) |
| |
| #define | USB_GRXSTSR_DEVICEMODE_PktSts_Pos (17UL) |
| |
| #define | USB_GRXSTSR_DEVICEMODE_PktSts_Msk (0x1e0000UL) |
| |
| #define | USB_GRXSTSR_DEVICEMODE_FN_Pos (21UL) |
| |
| #define | USB_GRXSTSR_DEVICEMODE_FN_Msk (0x1e00000UL) |
| |
| #define | USB_GRXSTSP_DEVICEMODE_EPNum_Pos (0UL) |
| |
| #define | USB_GRXSTSP_DEVICEMODE_EPNum_Msk (0xfUL) |
| |
| #define | USB_GRXSTSP_DEVICEMODE_BCnt_Pos (4UL) |
| |
| #define | USB_GRXSTSP_DEVICEMODE_BCnt_Msk (0x7ff0UL) |
| |
| #define | USB_GRXSTSP_DEVICEMODE_DPID_Pos (15UL) |
| |
| #define | USB_GRXSTSP_DEVICEMODE_DPID_Msk (0x18000UL) |
| |
| #define | USB_GRXSTSP_DEVICEMODE_PktSts_Pos (17UL) |
| |
| #define | USB_GRXSTSP_DEVICEMODE_PktSts_Msk (0x1e0000UL) |
| |
| #define | USB_GRXSTSP_DEVICEMODE_FN_Pos (21UL) |
| |
| #define | USB_GRXSTSP_DEVICEMODE_FN_Msk (0x1e00000UL) |
| |
| #define | USB_GRXSTSP_HOSTMODE_ChNum_Pos (0UL) |
| |
| #define | USB_GRXSTSP_HOSTMODE_ChNum_Msk (0xfUL) |
| |
| #define | USB_GRXSTSP_HOSTMODE_BCnt_Pos (4UL) |
| |
| #define | USB_GRXSTSP_HOSTMODE_BCnt_Msk (0x7ff0UL) |
| |
| #define | USB_GRXSTSP_HOSTMODE_DPID_Pos (15UL) |
| |
| #define | USB_GRXSTSP_HOSTMODE_DPID_Msk (0x18000UL) |
| |
| #define | USB_GRXSTSP_HOSTMODE_PktSts_Pos (17UL) |
| |
| #define | USB_GRXSTSP_HOSTMODE_PktSts_Msk (0x1e0000UL) |
| |
| #define | USB_GRXFSIZ_RxFDep_Pos (0UL) |
| |
| #define | USB_GRXFSIZ_RxFDep_Msk (0xffffUL) |
| |
| #define | USB_GNPTXFSIZ_HOSTMODE_NPTxFStAddr_Pos (0UL) |
| |
| #define | USB_GNPTXFSIZ_HOSTMODE_NPTxFStAddr_Msk (0xffffUL) |
| |
| #define | USB_GNPTXFSIZ_HOSTMODE_NPTxFDep_Pos (16UL) |
| |
| #define | USB_GNPTXFSIZ_HOSTMODE_NPTxFDep_Msk (0xffff0000UL) |
| |
| #define | USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0StAddr_Pos (0UL) |
| |
| #define | USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0StAddr_Msk (0xffffUL) |
| |
| #define | USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0Dep_Pos (16UL) |
| |
| #define | USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0Dep_Msk (0xffff0000UL) |
| |
| #define | USB_GNPTXSTS_NPTxFSpcAvail_Pos (0UL) |
| |
| #define | USB_GNPTXSTS_NPTxFSpcAvail_Msk (0xffffUL) |
| |
| #define | USB_GNPTXSTS_NPTxQSpcAvail_Pos (16UL) |
| |
| #define | USB_GNPTXSTS_NPTxQSpcAvail_Msk (0xff0000UL) |
| |
| #define | USB_GNPTXSTS_NPTxQTop_Pos (24UL) |
| |
| #define | USB_GNPTXSTS_NPTxQTop_Msk (0x7f000000UL) |
| |
| #define | USB_GUID_MOD_REV_Pos (0UL) |
| |
| #define | USB_GUID_MOD_REV_Msk (0xffUL) |
| |
| #define | USB_GUID_MOD_TYPE_Pos (8UL) |
| |
| #define | USB_GUID_MOD_TYPE_Msk (0xff00UL) |
| |
| #define | USB_GUID_MOD_NUMBER_Pos (16UL) |
| |
| #define | USB_GUID_MOD_NUMBER_Msk (0xffff0000UL) |
| |
| #define | USB_GDFIFOCFG_GDFIFOCfg_Pos (0UL) |
| |
| #define | USB_GDFIFOCFG_GDFIFOCfg_Msk (0xffffUL) |
| |
| #define | USB_GDFIFOCFG_EPInfoBaseAddr_Pos (16UL) |
| |
| #define | USB_GDFIFOCFG_EPInfoBaseAddr_Msk (0xffff0000UL) |
| |
| #define | USB_HPTXFSIZ_PTxFStAddr_Pos (0UL) |
| |
| #define | USB_HPTXFSIZ_PTxFStAddr_Msk (0xffffUL) |
| |
| #define | USB_HPTXFSIZ_PTxFSize_Pos (16UL) |
| |
| #define | USB_HPTXFSIZ_PTxFSize_Msk (0xffff0000UL) |
| |
| #define | USB_DIEPTXF1_INEPnTxFStAddr_Pos (0UL) |
| |
| #define | USB_DIEPTXF1_INEPnTxFStAddr_Msk (0xffffUL) |
| |
| #define | USB_DIEPTXF1_INEPnTxFDep_Pos (16UL) |
| |
| #define | USB_DIEPTXF1_INEPnTxFDep_Msk (0xffff0000UL) |
| |
| #define | USB_DIEPTXF2_INEPnTxFStAddr_Pos (0UL) |
| |
| #define | USB_DIEPTXF2_INEPnTxFStAddr_Msk (0xffffUL) |
| |
| #define | USB_DIEPTXF2_INEPnTxFDep_Pos (16UL) |
| |
| #define | USB_DIEPTXF2_INEPnTxFDep_Msk (0xffff0000UL) |
| |
| #define | USB_DIEPTXF3_INEPnTxFStAddr_Pos (0UL) |
| |
| #define | USB_DIEPTXF3_INEPnTxFStAddr_Msk (0xffffUL) |
| |
| #define | USB_DIEPTXF3_INEPnTxFDep_Pos (16UL) |
| |
| #define | USB_DIEPTXF3_INEPnTxFDep_Msk (0xffff0000UL) |
| |
| #define | USB_DIEPTXF4_INEPnTxFStAddr_Pos (0UL) |
| |
| #define | USB_DIEPTXF4_INEPnTxFStAddr_Msk (0xffffUL) |
| |
| #define | USB_DIEPTXF4_INEPnTxFDep_Pos (16UL) |
| |
| #define | USB_DIEPTXF4_INEPnTxFDep_Msk (0xffff0000UL) |
| |
| #define | USB_DIEPTXF5_INEPnTxFStAddr_Pos (0UL) |
| |
| #define | USB_DIEPTXF5_INEPnTxFStAddr_Msk (0xffffUL) |
| |
| #define | USB_DIEPTXF5_INEPnTxFDep_Pos (16UL) |
| |
| #define | USB_DIEPTXF5_INEPnTxFDep_Msk (0xffff0000UL) |
| |
| #define | USB_DIEPTXF6_INEPnTxFStAddr_Pos (0UL) |
| |
| #define | USB_DIEPTXF6_INEPnTxFStAddr_Msk (0xffffUL) |
| |
| #define | USB_DIEPTXF6_INEPnTxFDep_Pos (16UL) |
| |
| #define | USB_DIEPTXF6_INEPnTxFDep_Msk (0xffff0000UL) |
| |
| #define | USB_HCFG_FSLSPclkSel_Pos (0UL) |
| |
| #define | USB_HCFG_FSLSPclkSel_Msk (0x3UL) |
| |
| #define | USB_HCFG_FSLSSupp_Pos (2UL) |
| |
| #define | USB_HCFG_FSLSSupp_Msk (0x4UL) |
| |
| #define | USB_HCFG_DescDMA_Pos (23UL) |
| |
| #define | USB_HCFG_DescDMA_Msk (0x800000UL) |
| |
| #define | USB_HCFG_FrListEn_Pos (24UL) |
| |
| #define | USB_HCFG_FrListEn_Msk (0x3000000UL) |
| |
| #define | USB_HCFG_PerSchedEna_Pos (26UL) |
| |
| #define | USB_HCFG_PerSchedEna_Msk (0x4000000UL) |
| |
| #define | USB_HFIR_FrInt_Pos (0UL) |
| |
| #define | USB_HFIR_FrInt_Msk (0xffffUL) |
| |
| #define | USB_HFIR_HFIRRldCtrl_Pos (16UL) |
| |
| #define | USB_HFIR_HFIRRldCtrl_Msk (0x10000UL) |
| |
| #define | USB_HFNUM_FrNum_Pos (0UL) |
| |
| #define | USB_HFNUM_FrNum_Msk (0xffffUL) |
| |
| #define | USB_HFNUM_FrRem_Pos (16UL) |
| |
| #define | USB_HFNUM_FrRem_Msk (0xffff0000UL) |
| |
| #define | USB_HPTXSTS_PTxFSpcAvail_Pos (0UL) |
| |
| #define | USB_HPTXSTS_PTxFSpcAvail_Msk (0xffffUL) |
| |
| #define | USB_HPTXSTS_PTxQSpcAvail_Pos (16UL) |
| |
| #define | USB_HPTXSTS_PTxQSpcAvail_Msk (0xff0000UL) |
| |
| #define | USB_HPTXSTS_PTxQTop_Pos (24UL) |
| |
| #define | USB_HPTXSTS_PTxQTop_Msk (0xff000000UL) |
| |
| #define | USB_HAINT_HAINT_Pos (0UL) |
| |
| #define | USB_HAINT_HAINT_Msk (0x3fffUL) |
| |
| #define | USB_HAINTMSK_HAINTMsk_Pos (0UL) |
| |
| #define | USB_HAINTMSK_HAINTMsk_Msk (0x3fffUL) |
| |
| #define | USB_HFLBADDR_Starting_Address_Pos (0UL) |
| |
| #define | USB_HFLBADDR_Starting_Address_Msk (0xffffffffUL) |
| |
| #define | USB_HPRT_PrtConnSts_Pos (0UL) |
| |
| #define | USB_HPRT_PrtConnSts_Msk (0x1UL) |
| |
| #define | USB_HPRT_PrtConnDet_Pos (1UL) |
| |
| #define | USB_HPRT_PrtConnDet_Msk (0x2UL) |
| |
| #define | USB_HPRT_PrtEna_Pos (2UL) |
| |
| #define | USB_HPRT_PrtEna_Msk (0x4UL) |
| |
| #define | USB_HPRT_PrtEnChng_Pos (3UL) |
| |
| #define | USB_HPRT_PrtEnChng_Msk (0x8UL) |
| |
| #define | USB_HPRT_PrtOvrCurrAct_Pos (4UL) |
| |
| #define | USB_HPRT_PrtOvrCurrAct_Msk (0x10UL) |
| |
| #define | USB_HPRT_PrtOvrCurrChng_Pos (5UL) |
| |
| #define | USB_HPRT_PrtOvrCurrChng_Msk (0x20UL) |
| |
| #define | USB_HPRT_PrtRes_Pos (6UL) |
| |
| #define | USB_HPRT_PrtRes_Msk (0x40UL) |
| |
| #define | USB_HPRT_PrtSusp_Pos (7UL) |
| |
| #define | USB_HPRT_PrtSusp_Msk (0x80UL) |
| |
| #define | USB_HPRT_PrtRst_Pos (8UL) |
| |
| #define | USB_HPRT_PrtRst_Msk (0x100UL) |
| |
| #define | USB_HPRT_PrtLnSts_Pos (10UL) |
| |
| #define | USB_HPRT_PrtLnSts_Msk (0xc00UL) |
| |
| #define | USB_HPRT_PrtPwr_Pos (12UL) |
| |
| #define | USB_HPRT_PrtPwr_Msk (0x1000UL) |
| |
| #define | USB_HPRT_PrtSpd_Pos (17UL) |
| |
| #define | USB_HPRT_PrtSpd_Msk (0x60000UL) |
| |
| #define | USB_DCFG_DevSpd_Pos (0UL) |
| |
| #define | USB_DCFG_DevSpd_Msk (0x3UL) |
| |
| #define | USB_DCFG_NZStsOUTHShk_Pos (2UL) |
| |
| #define | USB_DCFG_NZStsOUTHShk_Msk (0x4UL) |
| |
| #define | USB_DCFG_DevAddr_Pos (4UL) |
| |
| #define | USB_DCFG_DevAddr_Msk (0x7f0UL) |
| |
| #define | USB_DCFG_PerFrInt_Pos (11UL) |
| |
| #define | USB_DCFG_PerFrInt_Msk (0x1800UL) |
| |
| #define | USB_DCFG_DescDMA_Pos (23UL) |
| |
| #define | USB_DCFG_DescDMA_Msk (0x800000UL) |
| |
| #define | USB_DCFG_PerSchIntvl_Pos (24UL) |
| |
| #define | USB_DCFG_PerSchIntvl_Msk (0x3000000UL) |
| |
| #define | USB_DCTL_RmtWkUpSig_Pos (0UL) |
| |
| #define | USB_DCTL_RmtWkUpSig_Msk (0x1UL) |
| |
| #define | USB_DCTL_SftDiscon_Pos (1UL) |
| |
| #define | USB_DCTL_SftDiscon_Msk (0x2UL) |
| |
| #define | USB_DCTL_GNPINNakSts_Pos (2UL) |
| |
| #define | USB_DCTL_GNPINNakSts_Msk (0x4UL) |
| |
| #define | USB_DCTL_GOUTNakSts_Pos (3UL) |
| |
| #define | USB_DCTL_GOUTNakSts_Msk (0x8UL) |
| |
| #define | USB_DCTL_SGNPInNak_Pos (7UL) |
| |
| #define | USB_DCTL_SGNPInNak_Msk (0x80UL) |
| |
| #define | USB_DCTL_CGNPInNak_Pos (8UL) |
| |
| #define | USB_DCTL_CGNPInNak_Msk (0x100UL) |
| |
| #define | USB_DCTL_SGOUTNak_Pos (9UL) |
| |
| #define | USB_DCTL_SGOUTNak_Msk (0x200UL) |
| |
| #define | USB_DCTL_CGOUTNak_Pos (10UL) |
| |
| #define | USB_DCTL_CGOUTNak_Msk (0x400UL) |
| |
| #define | USB_DCTL_GMC_Pos (13UL) |
| |
| #define | USB_DCTL_GMC_Msk (0x6000UL) |
| |
| #define | USB_DCTL_IgnrFrmNum_Pos (15UL) |
| |
| #define | USB_DCTL_IgnrFrmNum_Msk (0x8000UL) |
| |
| #define | USB_DCTL_NakOnBble_Pos (16UL) |
| |
| #define | USB_DCTL_NakOnBble_Msk (0x10000UL) |
| |
| #define | USB_DCTL_EnContOnBNA_Pos (17UL) |
| |
| #define | USB_DCTL_EnContOnBNA_Msk (0x20000UL) |
| |
| #define | USB_DSTS_SuspSts_Pos (0UL) |
| |
| #define | USB_DSTS_SuspSts_Msk (0x1UL) |
| |
| #define | USB_DSTS_EnumSpd_Pos (1UL) |
| |
| #define | USB_DSTS_EnumSpd_Msk (0x6UL) |
| |
| #define | USB_DSTS_ErrticErr_Pos (3UL) |
| |
| #define | USB_DSTS_ErrticErr_Msk (0x8UL) |
| |
| #define | USB_DSTS_SOFFN_Pos (8UL) |
| |
| #define | USB_DSTS_SOFFN_Msk (0x3fff00UL) |
| |
| #define | USB_DIEPMSK_XferComplMsk_Pos (0UL) |
| |
| #define | USB_DIEPMSK_XferComplMsk_Msk (0x1UL) |
| |
| #define | USB_DIEPMSK_EPDisbldMsk_Pos (1UL) |
| |
| #define | USB_DIEPMSK_EPDisbldMsk_Msk (0x2UL) |
| |
| #define | USB_DIEPMSK_AHBErrMsk_Pos (2UL) |
| |
| #define | USB_DIEPMSK_AHBErrMsk_Msk (0x4UL) |
| |
| #define | USB_DIEPMSK_TimeOUTMsk_Pos (3UL) |
| |
| #define | USB_DIEPMSK_TimeOUTMsk_Msk (0x8UL) |
| |
| #define | USB_DIEPMSK_INTknTXFEmpMsk_Pos (4UL) |
| |
| #define | USB_DIEPMSK_INTknTXFEmpMsk_Msk (0x10UL) |
| |
| #define | USB_DIEPMSK_INEPNakEffMsk_Pos (6UL) |
| |
| #define | USB_DIEPMSK_INEPNakEffMsk_Msk (0x40UL) |
| |
| #define | USB_DIEPMSK_TxfifoUndrnMsk_Pos (8UL) |
| |
| #define | USB_DIEPMSK_TxfifoUndrnMsk_Msk (0x100UL) |
| |
| #define | USB_DIEPMSK_BNAInIntrMsk_Pos (9UL) |
| |
| #define | USB_DIEPMSK_BNAInIntrMsk_Msk (0x200UL) |
| |
| #define | USB_DIEPMSK_NAKMsk_Pos (13UL) |
| |
| #define | USB_DIEPMSK_NAKMsk_Msk (0x2000UL) |
| |
| #define | USB_DOEPMSK_XferComplMsk_Pos (0UL) |
| |
| #define | USB_DOEPMSK_XferComplMsk_Msk (0x1UL) |
| |
| #define | USB_DOEPMSK_EPDisbldMsk_Pos (1UL) |
| |
| #define | USB_DOEPMSK_EPDisbldMsk_Msk (0x2UL) |
| |
| #define | USB_DOEPMSK_AHBErrMsk_Pos (2UL) |
| |
| #define | USB_DOEPMSK_AHBErrMsk_Msk (0x4UL) |
| |
| #define | USB_DOEPMSK_SetUPMsk_Pos (3UL) |
| |
| #define | USB_DOEPMSK_SetUPMsk_Msk (0x8UL) |
| |
| #define | USB_DOEPMSK_OUTTknEPdisMsk_Pos (4UL) |
| |
| #define | USB_DOEPMSK_OUTTknEPdisMsk_Msk (0x10UL) |
| |
| #define | USB_DOEPMSK_Back2BackSETup_Pos (6UL) |
| |
| #define | USB_DOEPMSK_Back2BackSETup_Msk (0x40UL) |
| |
| #define | USB_DOEPMSK_OutPktErrMsk_Pos (8UL) |
| |
| #define | USB_DOEPMSK_OutPktErrMsk_Msk (0x100UL) |
| |
| #define | USB_DOEPMSK_BnaOutIntrMsk_Pos (9UL) |
| |
| #define | USB_DOEPMSK_BnaOutIntrMsk_Msk (0x200UL) |
| |
| #define | USB_DOEPMSK_BbleErrMsk_Pos (12UL) |
| |
| #define | USB_DOEPMSK_BbleErrMsk_Msk (0x1000UL) |
| |
| #define | USB_DOEPMSK_NAKMsk_Pos (13UL) |
| |
| #define | USB_DOEPMSK_NAKMsk_Msk (0x2000UL) |
| |
| #define | USB_DOEPMSK_NYETMsk_Pos (14UL) |
| |
| #define | USB_DOEPMSK_NYETMsk_Msk (0x4000UL) |
| |
| #define | USB_DAINT_InEpInt_Pos (0UL) |
| |
| #define | USB_DAINT_InEpInt_Msk (0xffffUL) |
| |
| #define | USB_DAINT_OutEPInt_Pos (16UL) |
| |
| #define | USB_DAINT_OutEPInt_Msk (0xffff0000UL) |
| |
| #define | USB_DAINTMSK_InEpMsk_Pos (0UL) |
| |
| #define | USB_DAINTMSK_InEpMsk_Msk (0xffffUL) |
| |
| #define | USB_DAINTMSK_OutEpMsk_Pos (16UL) |
| |
| #define | USB_DAINTMSK_OutEpMsk_Msk (0xffff0000UL) |
| |
| #define | USB_DVBUSDIS_DVBUSDis_Pos (0UL) |
| |
| #define | USB_DVBUSDIS_DVBUSDis_Msk (0xffffUL) |
| |
| #define | USB_DVBUSPULSE_DVBUSPulse_Pos (0UL) |
| |
| #define | USB_DVBUSPULSE_DVBUSPulse_Msk (0xfffUL) |
| |
| #define | USB_DIEPEMPMSK_InEpTxfEmpMsk_Pos (0UL) |
| |
| #define | USB_DIEPEMPMSK_InEpTxfEmpMsk_Msk (0xffffUL) |
| |
| #define | USB_PCGCCTL_StopPclk_Pos (0UL) |
| |
| #define | USB_PCGCCTL_StopPclk_Msk (0x1UL) |
| |
| #define | USB_PCGCCTL_GateHclk_Pos (1UL) |
| |
| #define | USB_PCGCCTL_GateHclk_Msk (0x2UL) |
| |
| #define | USB_EP_DIEPCTL0_MPS_Pos (0UL) |
| |
| #define | USB_EP_DIEPCTL0_MPS_Msk (0x3UL) |
| |
| #define | USB_EP_DIEPCTL0_USBActEP_Pos (15UL) |
| |
| #define | USB_EP_DIEPCTL0_USBActEP_Msk (0x8000UL) |
| |
| #define | USB_EP_DIEPCTL0_NAKSts_Pos (17UL) |
| |
| #define | USB_EP_DIEPCTL0_NAKSts_Msk (0x20000UL) |
| |
| #define | USB_EP_DIEPCTL0_EPType_Pos (18UL) |
| |
| #define | USB_EP_DIEPCTL0_EPType_Msk (0xc0000UL) |
| |
| #define | USB_EP_DIEPCTL0_Stall_Pos (21UL) |
| |
| #define | USB_EP_DIEPCTL0_Stall_Msk (0x200000UL) |
| |
| #define | USB_EP_DIEPCTL0_TxFNum_Pos (22UL) |
| |
| #define | USB_EP_DIEPCTL0_TxFNum_Msk (0x3c00000UL) |
| |
| #define | USB_EP_DIEPCTL0_CNAK_Pos (26UL) |
| |
| #define | USB_EP_DIEPCTL0_CNAK_Msk (0x4000000UL) |
| |
| #define | USB_EP_DIEPCTL0_SNAK_Pos (27UL) |
| |
| #define | USB_EP_DIEPCTL0_SNAK_Msk (0x8000000UL) |
| |
| #define | USB_EP_DIEPCTL0_EPDis_Pos (30UL) |
| |
| #define | USB_EP_DIEPCTL0_EPDis_Msk (0x40000000UL) |
| |
| #define | USB_EP_DIEPCTL0_EPEna_Pos (31UL) |
| |
| #define | USB_EP_DIEPCTL0_EPEna_Msk (0x80000000UL) |
| |
| #define | USB_EP_DIEPINT0_XferCompl_Pos (0UL) |
| |
| #define | USB_EP_DIEPINT0_XferCompl_Msk (0x1UL) |
| |
| #define | USB_EP_DIEPINT0_EPDisbld_Pos (1UL) |
| |
| #define | USB_EP_DIEPINT0_EPDisbld_Msk (0x2UL) |
| |
| #define | USB_EP_DIEPINT0_AHBErr_Pos (2UL) |
| |
| #define | USB_EP_DIEPINT0_AHBErr_Msk (0x4UL) |
| |
| #define | USB_EP_DIEPINT0_TimeOUT_Pos (3UL) |
| |
| #define | USB_EP_DIEPINT0_TimeOUT_Msk (0x8UL) |
| |
| #define | USB_EP_DIEPINT0_INTknTXFEmp_Pos (4UL) |
| |
| #define | USB_EP_DIEPINT0_INTknTXFEmp_Msk (0x10UL) |
| |
| #define | USB_EP_DIEPINT0_INEPNakEff_Pos (6UL) |
| |
| #define | USB_EP_DIEPINT0_INEPNakEff_Msk (0x40UL) |
| |
| #define | USB_EP_DIEPINT0_TxFEmp_Pos (7UL) |
| |
| #define | USB_EP_DIEPINT0_TxFEmp_Msk (0x80UL) |
| |
| #define | USB_EP_DIEPINT0_BNAIntr_Pos (9UL) |
| |
| #define | USB_EP_DIEPINT0_BNAIntr_Msk (0x200UL) |
| |
| #define | USB_EP_DIEPTSIZ0_XferSize_Pos (0UL) |
| |
| #define | USB_EP_DIEPTSIZ0_XferSize_Msk (0x7fUL) |
| |
| #define | USB_EP_DIEPTSIZ0_PktCnt_Pos (19UL) |
| |
| #define | USB_EP_DIEPTSIZ0_PktCnt_Msk (0x180000UL) |
| |
| #define | USB_EP_DIEPDMA0_DMAAddr_Pos (0UL) |
| |
| #define | USB_EP_DIEPDMA0_DMAAddr_Msk (0xffffffffUL) |
| |
| #define | USB_EP_DTXFSTS0_INEPTxFSpcAvail_Pos (0UL) |
| |
| #define | USB_EP_DTXFSTS0_INEPTxFSpcAvail_Msk (0xffffUL) |
| |
| #define | USB_EP_DIEPDMAB0_DMABufferAddr_Pos (0UL) |
| |
| #define | USB_EP_DIEPDMAB0_DMABufferAddr_Msk (0xffffffffUL) |
| |
| #define | USB_EP_DOEPCTL0_MPS_Pos (0UL) |
| |
| #define | USB_EP_DOEPCTL0_MPS_Msk (0x3UL) |
| |
| #define | USB_EP_DOEPCTL0_USBActEP_Pos (15UL) |
| |
| #define | USB_EP_DOEPCTL0_USBActEP_Msk (0x8000UL) |
| |
| #define | USB_EP_DOEPCTL0_NAKSts_Pos (17UL) |
| |
| #define | USB_EP_DOEPCTL0_NAKSts_Msk (0x20000UL) |
| |
| #define | USB_EP_DOEPCTL0_EPType_Pos (18UL) |
| |
| #define | USB_EP_DOEPCTL0_EPType_Msk (0xc0000UL) |
| |
| #define | USB_EP_DOEPCTL0_Snp_Pos (20UL) |
| |
| #define | USB_EP_DOEPCTL0_Snp_Msk (0x100000UL) |
| |
| #define | USB_EP_DOEPCTL0_Stall_Pos (21UL) |
| |
| #define | USB_EP_DOEPCTL0_Stall_Msk (0x200000UL) |
| |
| #define | USB_EP_DOEPCTL0_CNAK_Pos (26UL) |
| |
| #define | USB_EP_DOEPCTL0_CNAK_Msk (0x4000000UL) |
| |
| #define | USB_EP_DOEPCTL0_SNAK_Pos (27UL) |
| |
| #define | USB_EP_DOEPCTL0_SNAK_Msk (0x8000000UL) |
| |
| #define | USB_EP_DOEPCTL0_EPDis_Pos (30UL) |
| |
| #define | USB_EP_DOEPCTL0_EPDis_Msk (0x40000000UL) |
| |
| #define | USB_EP_DOEPCTL0_EPEna_Pos (31UL) |
| |
| #define | USB_EP_DOEPCTL0_EPEna_Msk (0x80000000UL) |
| |
| #define | USB_EP_DOEPINT0_XferCompl_Pos (0UL) |
| |
| #define | USB_EP_DOEPINT0_XferCompl_Msk (0x1UL) |
| |
| #define | USB_EP_DOEPINT0_EPDisbld_Pos (1UL) |
| |
| #define | USB_EP_DOEPINT0_EPDisbld_Msk (0x2UL) |
| |
| #define | USB_EP_DOEPINT0_AHBErr_Pos (2UL) |
| |
| #define | USB_EP_DOEPINT0_AHBErr_Msk (0x4UL) |
| |
| #define | USB_EP_DOEPINT0_SetUp_Pos (3UL) |
| |
| #define | USB_EP_DOEPINT0_SetUp_Msk (0x8UL) |
| |
| #define | USB_EP_DOEPINT0_OUTTknEPdis_Pos (4UL) |
| |
| #define | USB_EP_DOEPINT0_OUTTknEPdis_Msk (0x10UL) |
| |
| #define | USB_EP_DOEPINT0_StsPhseRcvd_Pos (5UL) |
| |
| #define | USB_EP_DOEPINT0_StsPhseRcvd_Msk (0x20UL) |
| |
| #define | USB_EP_DOEPINT0_Back2BackSETup_Pos (6UL) |
| |
| #define | USB_EP_DOEPINT0_Back2BackSETup_Msk (0x40UL) |
| |
| #define | USB_EP_DOEPINT0_BNAIntr_Pos (9UL) |
| |
| #define | USB_EP_DOEPINT0_BNAIntr_Msk (0x200UL) |
| |
| #define | USB_EP_DOEPINT0_PktDrpSts_Pos (11UL) |
| |
| #define | USB_EP_DOEPINT0_PktDrpSts_Msk (0x800UL) |
| |
| #define | USB_EP_DOEPINT0_BbleErrIntrpt_Pos (12UL) |
| |
| #define | USB_EP_DOEPINT0_BbleErrIntrpt_Msk (0x1000UL) |
| |
| #define | USB_EP_DOEPINT0_NAKIntrpt_Pos (13UL) |
| |
| #define | USB_EP_DOEPINT0_NAKIntrpt_Msk (0x2000UL) |
| |
| #define | USB_EP_DOEPINT0_NYETIntrpt_Pos (14UL) |
| |
| #define | USB_EP_DOEPINT0_NYETIntrpt_Msk (0x4000UL) |
| |
| #define | USB_EP_DOEPTSIZ0_XferSize_Pos (0UL) |
| |
| #define | USB_EP_DOEPTSIZ0_XferSize_Msk (0x7fUL) |
| |
| #define | USB_EP_DOEPTSIZ0_PktCnt_Pos (19UL) |
| |
| #define | USB_EP_DOEPTSIZ0_PktCnt_Msk (0x180000UL) |
| |
| #define | USB_EP_DOEPTSIZ0_SUPCnt_Pos (29UL) |
| |
| #define | USB_EP_DOEPTSIZ0_SUPCnt_Msk (0x60000000UL) |
| |
| #define | USB_EP_DOEPDMA0_DMAAddr_Pos (0UL) |
| |
| #define | USB_EP_DOEPDMA0_DMAAddr_Msk (0xffffffffUL) |
| |
| #define | USB_EP_DOEPDMAB0_DMABufferAddr_Pos (0UL) |
| |
| #define | USB_EP_DOEPDMAB0_DMABufferAddr_Msk (0xffffffffUL) |
| |
| #define | USB_EP_DIEPCTL_ISOCONT_MPS_Pos (0UL) |
| |
| #define | USB_EP_DIEPCTL_ISOCONT_MPS_Msk (0x7ffUL) |
| |
| #define | USB_EP_DIEPCTL_ISOCONT_USBActEP_Pos (15UL) |
| |
| #define | USB_EP_DIEPCTL_ISOCONT_USBActEP_Msk (0x8000UL) |
| |
| #define | USB_EP_DIEPCTL_ISOCONT_EO_FrNum_Pos (16UL) |
| |
| #define | USB_EP_DIEPCTL_ISOCONT_EO_FrNum_Msk (0x10000UL) |
| |
| #define | USB_EP_DIEPCTL_ISOCONT_NAKSts_Pos (17UL) |
| |
| #define | USB_EP_DIEPCTL_ISOCONT_NAKSts_Msk (0x20000UL) |
| |
| #define | USB_EP_DIEPCTL_ISOCONT_EPType_Pos (18UL) |
| |
| #define | USB_EP_DIEPCTL_ISOCONT_EPType_Msk (0xc0000UL) |
| |
| #define | USB_EP_DIEPCTL_ISOCONT_Snp_Pos (20UL) |
| |
| #define | USB_EP_DIEPCTL_ISOCONT_Snp_Msk (0x100000UL) |
| |
| #define | USB_EP_DIEPCTL_ISOCONT_Stall_Pos (21UL) |
| |
| #define | USB_EP_DIEPCTL_ISOCONT_Stall_Msk (0x200000UL) |
| |
| #define | USB_EP_DIEPCTL_ISOCONT_TxFNum_Pos (22UL) |
| |
| #define | USB_EP_DIEPCTL_ISOCONT_TxFNum_Msk (0x3c00000UL) |
| |
| #define | USB_EP_DIEPCTL_ISOCONT_CNAK_Pos (26UL) |
| |
| #define | USB_EP_DIEPCTL_ISOCONT_CNAK_Msk (0x4000000UL) |
| |
| #define | USB_EP_DIEPCTL_ISOCONT_SNAK_Pos (27UL) |
| |
| #define | USB_EP_DIEPCTL_ISOCONT_SNAK_Msk (0x8000000UL) |
| |
| #define | USB_EP_DIEPCTL_ISOCONT_SetEvenFr_Pos (28UL) |
| |
| #define | USB_EP_DIEPCTL_ISOCONT_SetEvenFr_Msk (0x10000000UL) |
| |
| #define | USB_EP_DIEPCTL_ISOCONT_SetOddFr_Pos (29UL) |
| |
| #define | USB_EP_DIEPCTL_ISOCONT_SetOddFr_Msk (0x20000000UL) |
| |
| #define | USB_EP_DIEPCTL_ISOCONT_EPDis_Pos (30UL) |
| |
| #define | USB_EP_DIEPCTL_ISOCONT_EPDis_Msk (0x40000000UL) |
| |
| #define | USB_EP_DIEPCTL_ISOCONT_EPEna_Pos (31UL) |
| |
| #define | USB_EP_DIEPCTL_ISOCONT_EPEna_Msk (0x80000000UL) |
| |
| #define | USB_EP_DIEPCTL_INTBULK_MPS_Pos (0UL) |
| |
| #define | USB_EP_DIEPCTL_INTBULK_MPS_Msk (0x7ffUL) |
| |
| #define | USB_EP_DIEPCTL_INTBULK_USBActEP_Pos (15UL) |
| |
| #define | USB_EP_DIEPCTL_INTBULK_USBActEP_Msk (0x8000UL) |
| |
| #define | USB_EP_DIEPCTL_INTBULK_DPID_Pos (16UL) |
| |
| #define | USB_EP_DIEPCTL_INTBULK_DPID_Msk (0x10000UL) |
| |
| #define | USB_EP_DIEPCTL_INTBULK_NAKSts_Pos (17UL) |
| |
| #define | USB_EP_DIEPCTL_INTBULK_NAKSts_Msk (0x20000UL) |
| |
| #define | USB_EP_DIEPCTL_INTBULK_EPType_Pos (18UL) |
| |
| #define | USB_EP_DIEPCTL_INTBULK_EPType_Msk (0xc0000UL) |
| |
| #define | USB_EP_DIEPCTL_INTBULK_Snp_Pos (20UL) |
| |
| #define | USB_EP_DIEPCTL_INTBULK_Snp_Msk (0x100000UL) |
| |
| #define | USB_EP_DIEPCTL_INTBULK_Stall_Pos (21UL) |
| |
| #define | USB_EP_DIEPCTL_INTBULK_Stall_Msk (0x200000UL) |
| |
| #define | USB_EP_DIEPCTL_INTBULK_TxFNum_Pos (22UL) |
| |
| #define | USB_EP_DIEPCTL_INTBULK_TxFNum_Msk (0x3c00000UL) |
| |
| #define | USB_EP_DIEPCTL_INTBULK_CNAK_Pos (26UL) |
| |
| #define | USB_EP_DIEPCTL_INTBULK_CNAK_Msk (0x4000000UL) |
| |
| #define | USB_EP_DIEPCTL_INTBULK_SNAK_Pos (27UL) |
| |
| #define | USB_EP_DIEPCTL_INTBULK_SNAK_Msk (0x8000000UL) |
| |
| #define | USB_EP_DIEPCTL_INTBULK_SetD0PID_Pos (28UL) |
| |
| #define | USB_EP_DIEPCTL_INTBULK_SetD0PID_Msk (0x10000000UL) |
| |
| #define | USB_EP_DIEPCTL_INTBULK_SetD1PID_Pos (29UL) |
| |
| #define | USB_EP_DIEPCTL_INTBULK_SetD1PID_Msk (0x20000000UL) |
| |
| #define | USB_EP_DIEPCTL_INTBULK_EPDis_Pos (30UL) |
| |
| #define | USB_EP_DIEPCTL_INTBULK_EPDis_Msk (0x40000000UL) |
| |
| #define | USB_EP_DIEPCTL_INTBULK_EPEna_Pos (31UL) |
| |
| #define | USB_EP_DIEPCTL_INTBULK_EPEna_Msk (0x80000000UL) |
| |
| #define | USB_EP_DIEPINT_XferCompl_Pos (0UL) |
| |
| #define | USB_EP_DIEPINT_XferCompl_Msk (0x1UL) |
| |
| #define | USB_EP_DIEPINT_EPDisbld_Pos (1UL) |
| |
| #define | USB_EP_DIEPINT_EPDisbld_Msk (0x2UL) |
| |
| #define | USB_EP_DIEPINT_AHBErr_Pos (2UL) |
| |
| #define | USB_EP_DIEPINT_AHBErr_Msk (0x4UL) |
| |
| #define | USB_EP_DIEPINT_TimeOUT_Pos (3UL) |
| |
| #define | USB_EP_DIEPINT_TimeOUT_Msk (0x8UL) |
| |
| #define | USB_EP_DIEPINT_INTknTXFEmp_Pos (4UL) |
| |
| #define | USB_EP_DIEPINT_INTknTXFEmp_Msk (0x10UL) |
| |
| #define | USB_EP_DIEPINT_INEPNakEff_Pos (6UL) |
| |
| #define | USB_EP_DIEPINT_INEPNakEff_Msk (0x40UL) |
| |
| #define | USB_EP_DIEPINT_TxFEmp_Pos (7UL) |
| |
| #define | USB_EP_DIEPINT_TxFEmp_Msk (0x80UL) |
| |
| #define | USB_EP_DIEPINT_BNAIntr_Pos (9UL) |
| |
| #define | USB_EP_DIEPINT_BNAIntr_Msk (0x200UL) |
| |
| #define | USB_EP_DIEPTSIZ_XferSize_Pos (0UL) |
| |
| #define | USB_EP_DIEPTSIZ_XferSize_Msk (0x7ffffUL) |
| |
| #define | USB_EP_DIEPTSIZ_PktCnt_Pos (19UL) |
| |
| #define | USB_EP_DIEPTSIZ_PktCnt_Msk (0x1ff80000UL) |
| |
| #define | USB_EP_DIEPDMA_DMAAddr_Pos (0UL) |
| |
| #define | USB_EP_DIEPDMA_DMAAddr_Msk (0xffffffffUL) |
| |
| #define | USB_EP_DTXFSTS_INEPTxFSpcAvail_Pos (0UL) |
| |
| #define | USB_EP_DTXFSTS_INEPTxFSpcAvail_Msk (0xffffUL) |
| |
| #define | USB_EP_DIEPDMAB_DMABufferAddr_Pos (0UL) |
| |
| #define | USB_EP_DIEPDMAB_DMABufferAddr_Msk (0xffffffffUL) |
| |
| #define | USB_EP_DOEPCTL_ISOCONT_MPS_Pos (0UL) |
| |
| #define | USB_EP_DOEPCTL_ISOCONT_MPS_Msk (0x7ffUL) |
| |
| #define | USB_EP_DOEPCTL_ISOCONT_USBActEP_Pos (15UL) |
| |
| #define | USB_EP_DOEPCTL_ISOCONT_USBActEP_Msk (0x8000UL) |
| |
| #define | USB_EP_DOEPCTL_ISOCONT_EO_FrNum_Pos (16UL) |
| |
| #define | USB_EP_DOEPCTL_ISOCONT_EO_FrNum_Msk (0x10000UL) |
| |
| #define | USB_EP_DOEPCTL_ISOCONT_NAKSts_Pos (17UL) |
| |
| #define | USB_EP_DOEPCTL_ISOCONT_NAKSts_Msk (0x20000UL) |
| |
| #define | USB_EP_DOEPCTL_ISOCONT_EPType_Pos (18UL) |
| |
| #define | USB_EP_DOEPCTL_ISOCONT_EPType_Msk (0xc0000UL) |
| |
| #define | USB_EP_DOEPCTL_ISOCONT_Snp_Pos (20UL) |
| |
| #define | USB_EP_DOEPCTL_ISOCONT_Snp_Msk (0x100000UL) |
| |
| #define | USB_EP_DOEPCTL_ISOCONT_Stall_Pos (21UL) |
| |
| #define | USB_EP_DOEPCTL_ISOCONT_Stall_Msk (0x200000UL) |
| |
| #define | USB_EP_DOEPCTL_ISOCONT_TxFNum_Pos (22UL) |
| |
| #define | USB_EP_DOEPCTL_ISOCONT_TxFNum_Msk (0x3c00000UL) |
| |
| #define | USB_EP_DOEPCTL_ISOCONT_CNAK_Pos (26UL) |
| |
| #define | USB_EP_DOEPCTL_ISOCONT_CNAK_Msk (0x4000000UL) |
| |
| #define | USB_EP_DOEPCTL_ISOCONT_SNAK_Pos (27UL) |
| |
| #define | USB_EP_DOEPCTL_ISOCONT_SNAK_Msk (0x8000000UL) |
| |
| #define | USB_EP_DOEPCTL_ISOCONT_SetEvenFr_Pos (28UL) |
| |
| #define | USB_EP_DOEPCTL_ISOCONT_SetEvenFr_Msk (0x10000000UL) |
| |
| #define | USB_EP_DOEPCTL_ISOCONT_SetOddFr_Pos (29UL) |
| |
| #define | USB_EP_DOEPCTL_ISOCONT_SetOddFr_Msk (0x20000000UL) |
| |
| #define | USB_EP_DOEPCTL_ISOCONT_EPDis_Pos (30UL) |
| |
| #define | USB_EP_DOEPCTL_ISOCONT_EPDis_Msk (0x40000000UL) |
| |
| #define | USB_EP_DOEPCTL_ISOCONT_EPEna_Pos (31UL) |
| |
| #define | USB_EP_DOEPCTL_ISOCONT_EPEna_Msk (0x80000000UL) |
| |
| #define | USB_EP_DOEPCTL_INTBULK_MPS_Pos (0UL) |
| |
| #define | USB_EP_DOEPCTL_INTBULK_MPS_Msk (0x7ffUL) |
| |
| #define | USB_EP_DOEPCTL_INTBULK_USBActEP_Pos (15UL) |
| |
| #define | USB_EP_DOEPCTL_INTBULK_USBActEP_Msk (0x8000UL) |
| |
| #define | USB_EP_DOEPCTL_INTBULK_DPID_Pos (16UL) |
| |
| #define | USB_EP_DOEPCTL_INTBULK_DPID_Msk (0x10000UL) |
| |
| #define | USB_EP_DOEPCTL_INTBULK_NAKSts_Pos (17UL) |
| |
| #define | USB_EP_DOEPCTL_INTBULK_NAKSts_Msk (0x20000UL) |
| |
| #define | USB_EP_DOEPCTL_INTBULK_EPType_Pos (18UL) |
| |
| #define | USB_EP_DOEPCTL_INTBULK_EPType_Msk (0xc0000UL) |
| |
| #define | USB_EP_DOEPCTL_INTBULK_Snp_Pos (20UL) |
| |
| #define | USB_EP_DOEPCTL_INTBULK_Snp_Msk (0x100000UL) |
| |
| #define | USB_EP_DOEPCTL_INTBULK_Stall_Pos (21UL) |
| |
| #define | USB_EP_DOEPCTL_INTBULK_Stall_Msk (0x200000UL) |
| |
| #define | USB_EP_DOEPCTL_INTBULK_TxFNum_Pos (22UL) |
| |
| #define | USB_EP_DOEPCTL_INTBULK_TxFNum_Msk (0x3c00000UL) |
| |
| #define | USB_EP_DOEPCTL_INTBULK_CNAK_Pos (26UL) |
| |
| #define | USB_EP_DOEPCTL_INTBULK_CNAK_Msk (0x4000000UL) |
| |
| #define | USB_EP_DOEPCTL_INTBULK_SNAK_Pos (27UL) |
| |
| #define | USB_EP_DOEPCTL_INTBULK_SNAK_Msk (0x8000000UL) |
| |
| #define | USB_EP_DOEPCTL_INTBULK_SetD0PID_Pos (28UL) |
| |
| #define | USB_EP_DOEPCTL_INTBULK_SetD0PID_Msk (0x10000000UL) |
| |
| #define | USB_EP_DOEPCTL_INTBULK_SetD1PID_Pos (29UL) |
| |
| #define | USB_EP_DOEPCTL_INTBULK_SetD1PID_Msk (0x20000000UL) |
| |
| #define | USB_EP_DOEPCTL_INTBULK_EPDis_Pos (30UL) |
| |
| #define | USB_EP_DOEPCTL_INTBULK_EPDis_Msk (0x40000000UL) |
| |
| #define | USB_EP_DOEPCTL_INTBULK_EPEna_Pos (31UL) |
| |
| #define | USB_EP_DOEPCTL_INTBULK_EPEna_Msk (0x80000000UL) |
| |
| #define | USB_EP_DOEPINT_XferCompl_Pos (0UL) |
| |
| #define | USB_EP_DOEPINT_XferCompl_Msk (0x1UL) |
| |
| #define | USB_EP_DOEPINT_EPDisbld_Pos (1UL) |
| |
| #define | USB_EP_DOEPINT_EPDisbld_Msk (0x2UL) |
| |
| #define | USB_EP_DOEPINT_AHBErr_Pos (2UL) |
| |
| #define | USB_EP_DOEPINT_AHBErr_Msk (0x4UL) |
| |
| #define | USB_EP_DOEPINT_SetUp_Pos (3UL) |
| |
| #define | USB_EP_DOEPINT_SetUp_Msk (0x8UL) |
| |
| #define | USB_EP_DOEPINT_OUTTknEPdis_Pos (4UL) |
| |
| #define | USB_EP_DOEPINT_OUTTknEPdis_Msk (0x10UL) |
| |
| #define | USB_EP_DOEPINT_StsPhseRcvd_Pos (5UL) |
| |
| #define | USB_EP_DOEPINT_StsPhseRcvd_Msk (0x20UL) |
| |
| #define | USB_EP_DOEPINT_Back2BackSETup_Pos (6UL) |
| |
| #define | USB_EP_DOEPINT_Back2BackSETup_Msk (0x40UL) |
| |
| #define | USB_EP_DOEPINT_BNAIntr_Pos (9UL) |
| |
| #define | USB_EP_DOEPINT_BNAIntr_Msk (0x200UL) |
| |
| #define | USB_EP_DOEPINT_PktDrpSts_Pos (11UL) |
| |
| #define | USB_EP_DOEPINT_PktDrpSts_Msk (0x800UL) |
| |
| #define | USB_EP_DOEPINT_BbleErrIntrpt_Pos (12UL) |
| |
| #define | USB_EP_DOEPINT_BbleErrIntrpt_Msk (0x1000UL) |
| |
| #define | USB_EP_DOEPINT_NAKIntrpt_Pos (13UL) |
| |
| #define | USB_EP_DOEPINT_NAKIntrpt_Msk (0x2000UL) |
| |
| #define | USB_EP_DOEPINT_NYETIntrpt_Pos (14UL) |
| |
| #define | USB_EP_DOEPINT_NYETIntrpt_Msk (0x4000UL) |
| |
| #define | USB_EP_DOEPTSIZ_ISO_XferSize_Pos (0UL) |
| |
| #define | USB_EP_DOEPTSIZ_ISO_XferSize_Msk (0x7ffffUL) |
| |
| #define | USB_EP_DOEPTSIZ_ISO_PktCnt_Pos (19UL) |
| |
| #define | USB_EP_DOEPTSIZ_ISO_PktCnt_Msk (0x1ff80000UL) |
| |
| #define | USB_EP_DOEPTSIZ_ISO_RxDPID_Pos (29UL) |
| |
| #define | USB_EP_DOEPTSIZ_ISO_RxDPID_Msk (0x60000000UL) |
| |
| #define | USB_EP_DOEPTSIZ_CONTROL_XferSize_Pos (0UL) |
| |
| #define | USB_EP_DOEPTSIZ_CONTROL_XferSize_Msk (0x7ffffUL) |
| |
| #define | USB_EP_DOEPTSIZ_CONTROL_PktCnt_Pos (19UL) |
| |
| #define | USB_EP_DOEPTSIZ_CONTROL_PktCnt_Msk (0x1ff80000UL) |
| |
| #define | USB_EP_DOEPTSIZ_CONTROL_SUPCnt_Pos (29UL) |
| |
| #define | USB_EP_DOEPTSIZ_CONTROL_SUPCnt_Msk (0x60000000UL) |
| |
| #define | USB_EP_DOEPDMA_DMAAddr_Pos (0UL) |
| |
| #define | USB_EP_DOEPDMA_DMAAddr_Msk (0xffffffffUL) |
| |
| #define | USB_EP_DOEPDMAB_DMABufferAddr_Pos (0UL) |
| |
| #define | USB_EP_DOEPDMAB_DMABufferAddr_Msk (0xffffffffUL) |
| |
| #define | USB_CH_HCCHAR_MPS_Pos (0UL) |
| |
| #define | USB_CH_HCCHAR_MPS_Msk (0x7ffUL) |
| |
| #define | USB_CH_HCCHAR_EPNum_Pos (11UL) |
| |
| #define | USB_CH_HCCHAR_EPNum_Msk (0x7800UL) |
| |
| #define | USB_CH_HCCHAR_EPDir_Pos (15UL) |
| |
| #define | USB_CH_HCCHAR_EPDir_Msk (0x8000UL) |
| |
| #define | USB_CH_HCCHAR_EPType_Pos (18UL) |
| |
| #define | USB_CH_HCCHAR_EPType_Msk (0xc0000UL) |
| |
| #define | USB_CH_HCCHAR_MC_EC_Pos (20UL) |
| |
| #define | USB_CH_HCCHAR_MC_EC_Msk (0x300000UL) |
| |
| #define | USB_CH_HCCHAR_DevAddr_Pos (22UL) |
| |
| #define | USB_CH_HCCHAR_DevAddr_Msk (0x1fc00000UL) |
| |
| #define | USB_CH_HCCHAR_OddFrm_Pos (29UL) |
| |
| #define | USB_CH_HCCHAR_OddFrm_Msk (0x20000000UL) |
| |
| #define | USB_CH_HCCHAR_ChDis_Pos (30UL) |
| |
| #define | USB_CH_HCCHAR_ChDis_Msk (0x40000000UL) |
| |
| #define | USB_CH_HCCHAR_ChEna_Pos (31UL) |
| |
| #define | USB_CH_HCCHAR_ChEna_Msk (0x80000000UL) |
| |
| #define | USB_CH_HCINT_XferCompl_Pos (0UL) |
| |
| #define | USB_CH_HCINT_XferCompl_Msk (0x1UL) |
| |
| #define | USB_CH_HCINT_ChHltd_Pos (1UL) |
| |
| #define | USB_CH_HCINT_ChHltd_Msk (0x2UL) |
| |
| #define | USB_CH_HCINT_AHBErr_Pos (2UL) |
| |
| #define | USB_CH_HCINT_AHBErr_Msk (0x4UL) |
| |
| #define | USB_CH_HCINT_STALL_Pos (3UL) |
| |
| #define | USB_CH_HCINT_STALL_Msk (0x8UL) |
| |
| #define | USB_CH_HCINT_NAK_Pos (4UL) |
| |
| #define | USB_CH_HCINT_NAK_Msk (0x10UL) |
| |
| #define | USB_CH_HCINT_ACK_Pos (5UL) |
| |
| #define | USB_CH_HCINT_ACK_Msk (0x20UL) |
| |
| #define | USB_CH_HCINT_NYET_Pos (6UL) |
| |
| #define | USB_CH_HCINT_NYET_Msk (0x40UL) |
| |
| #define | USB_CH_HCINT_XactErr_Pos (7UL) |
| |
| #define | USB_CH_HCINT_XactErr_Msk (0x80UL) |
| |
| #define | USB_CH_HCINT_BblErr_Pos (8UL) |
| |
| #define | USB_CH_HCINT_BblErr_Msk (0x100UL) |
| |
| #define | USB_CH_HCINT_FrmOvrun_Pos (9UL) |
| |
| #define | USB_CH_HCINT_FrmOvrun_Msk (0x200UL) |
| |
| #define | USB_CH_HCINT_DataTglErr_Pos (10UL) |
| |
| #define | USB_CH_HCINT_DataTglErr_Msk (0x400UL) |
| |
| #define | USB_CH_HCINT_BNAIntr_Pos (11UL) |
| |
| #define | USB_CH_HCINT_BNAIntr_Msk (0x800UL) |
| |
| #define | USB_CH_HCINT_XCS_XACT_ERR_Pos (12UL) |
| |
| #define | USB_CH_HCINT_XCS_XACT_ERR_Msk (0x1000UL) |
| |
| #define | USB_CH_HCINT_DESC_LST_ROLLIntr_Pos (13UL) |
| |
| #define | USB_CH_HCINT_DESC_LST_ROLLIntr_Msk (0x2000UL) |
| |
| #define | USB_CH_HCINTMSK_XferComplMsk_Pos (0UL) |
| |
| #define | USB_CH_HCINTMSK_XferComplMsk_Msk (0x1UL) |
| |
| #define | USB_CH_HCINTMSK_ChHltdMsk_Pos (1UL) |
| |
| #define | USB_CH_HCINTMSK_ChHltdMsk_Msk (0x2UL) |
| |
| #define | USB_CH_HCINTMSK_AHBErrMsk_Pos (2UL) |
| |
| #define | USB_CH_HCINTMSK_AHBErrMsk_Msk (0x4UL) |
| |
| #define | USB_CH_HCINTMSK_StallMsk_Pos (3UL) |
| |
| #define | USB_CH_HCINTMSK_StallMsk_Msk (0x8UL) |
| |
| #define | USB_CH_HCINTMSK_NakMsk_Pos (4UL) |
| |
| #define | USB_CH_HCINTMSK_NakMsk_Msk (0x10UL) |
| |
| #define | USB_CH_HCINTMSK_AckMsk_Pos (5UL) |
| |
| #define | USB_CH_HCINTMSK_AckMsk_Msk (0x20UL) |
| |
| #define | USB_CH_HCINTMSK_NyetMsk_Pos (6UL) |
| |
| #define | USB_CH_HCINTMSK_NyetMsk_Msk (0x40UL) |
| |
| #define | USB_CH_HCINTMSK_XactErrMsk_Pos (7UL) |
| |
| #define | USB_CH_HCINTMSK_XactErrMsk_Msk (0x80UL) |
| |
| #define | USB_CH_HCINTMSK_BblErrMsk_Pos (8UL) |
| |
| #define | USB_CH_HCINTMSK_BblErrMsk_Msk (0x100UL) |
| |
| #define | USB_CH_HCINTMSK_FrmOvrunMsk_Pos (9UL) |
| |
| #define | USB_CH_HCINTMSK_FrmOvrunMsk_Msk (0x200UL) |
| |
| #define | USB_CH_HCINTMSK_DataTglErrMsk_Pos (10UL) |
| |
| #define | USB_CH_HCINTMSK_DataTglErrMsk_Msk (0x400UL) |
| |
| #define | USB_CH_HCINTMSK_BNAIntrMsk_Pos (11UL) |
| |
| #define | USB_CH_HCINTMSK_BNAIntrMsk_Msk (0x800UL) |
| |
| #define | USB_CH_HCINTMSK_DESC_LST_ROLLIntrMsk_Pos (13UL) |
| |
| #define | USB_CH_HCINTMSK_DESC_LST_ROLLIntrMsk_Msk (0x2000UL) |
| |
| #define | USB_CH_HCTSIZ_BUFFERMODE_XferSize_Pos (0UL) |
| |
| #define | USB_CH_HCTSIZ_BUFFERMODE_XferSize_Msk (0x7ffffUL) |
| |
| #define | USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Pos (19UL) |
| |
| #define | USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Msk (0x1ff80000UL) |
| |
| #define | USB_CH_HCTSIZ_BUFFERMODE_Pid_Pos (29UL) |
| |
| #define | USB_CH_HCTSIZ_BUFFERMODE_Pid_Msk (0x60000000UL) |
| |
| #define | USB_CH_HCTSIZ_SCATGATHER_SCHED_INFO_Pos (0UL) |
| |
| #define | USB_CH_HCTSIZ_SCATGATHER_SCHED_INFO_Msk (0xffUL) |
| |
| #define | USB_CH_HCTSIZ_SCATGATHER_NTD_Pos (8UL) |
| |
| #define | USB_CH_HCTSIZ_SCATGATHER_NTD_Msk (0xff00UL) |
| |
| #define | USB_CH_HCTSIZ_SCATGATHER_Pid_Pos (29UL) |
| |
| #define | USB_CH_HCTSIZ_SCATGATHER_Pid_Msk (0x60000000UL) |
| |
| #define | USB_CH_HCDMA_BUFFERMODE_DMAAddr_Pos (0UL) |
| |
| #define | USB_CH_HCDMA_BUFFERMODE_DMAAddr_Msk (0xffffffffUL) |
| |
| #define | USB_CH_HCDMA_SCATGATHER_CTD_Pos (3UL) |
| |
| #define | USB_CH_HCDMA_SCATGATHER_CTD_Msk (0x1f8UL) |
| |
| #define | USB_CH_HCDMA_SCATGATHER_DMAAddr_Pos (9UL) |
| |
| #define | USB_CH_HCDMA_SCATGATHER_DMAAddr_Msk (0xfffffe00UL) |
| |
| #define | USB_CH_HCDMAB_Buffer_Address_Pos (0UL) |
| |
| #define | USB_CH_HCDMAB_Buffer_Address_Msk (0xffffffffUL) |
| |
| #define | USIC_ID_MOD_REV_Pos (0UL) |
| |
| #define | USIC_ID_MOD_REV_Msk (0xffUL) |
| |
| #define | USIC_ID_MOD_TYPE_Pos (8UL) |
| |
| #define | USIC_ID_MOD_TYPE_Msk (0xff00UL) |
| |
| #define | USIC_ID_MOD_NUMBER_Pos (16UL) |
| |
| #define | USIC_ID_MOD_NUMBER_Msk (0xffff0000UL) |
| |
| #define | USIC_CH_CCFG_SSC_Pos (0UL) |
| |
| #define | USIC_CH_CCFG_SSC_Msk (0x1UL) |
| |
| #define | USIC_CH_CCFG_ASC_Pos (1UL) |
| |
| #define | USIC_CH_CCFG_ASC_Msk (0x2UL) |
| |
| #define | USIC_CH_CCFG_IIC_Pos (2UL) |
| |
| #define | USIC_CH_CCFG_IIC_Msk (0x4UL) |
| |
| #define | USIC_CH_CCFG_IIS_Pos (3UL) |
| |
| #define | USIC_CH_CCFG_IIS_Msk (0x8UL) |
| |
| #define | USIC_CH_CCFG_RB_Pos (6UL) |
| |
| #define | USIC_CH_CCFG_RB_Msk (0x40UL) |
| |
| #define | USIC_CH_CCFG_TB_Pos (7UL) |
| |
| #define | USIC_CH_CCFG_TB_Msk (0x80UL) |
| |
| #define | USIC_CH_KSCFG_MODEN_Pos (0UL) |
| |
| #define | USIC_CH_KSCFG_MODEN_Msk (0x1UL) |
| |
| #define | USIC_CH_KSCFG_BPMODEN_Pos (1UL) |
| |
| #define | USIC_CH_KSCFG_BPMODEN_Msk (0x2UL) |
| |
| #define | USIC_CH_KSCFG_NOMCFG_Pos (4UL) |
| |
| #define | USIC_CH_KSCFG_NOMCFG_Msk (0x30UL) |
| |
| #define | USIC_CH_KSCFG_BPNOM_Pos (7UL) |
| |
| #define | USIC_CH_KSCFG_BPNOM_Msk (0x80UL) |
| |
| #define | USIC_CH_KSCFG_SUMCFG_Pos (8UL) |
| |
| #define | USIC_CH_KSCFG_SUMCFG_Msk (0x300UL) |
| |
| #define | USIC_CH_KSCFG_BPSUM_Pos (11UL) |
| |
| #define | USIC_CH_KSCFG_BPSUM_Msk (0x800UL) |
| |
| #define | USIC_CH_FDR_STEP_Pos (0UL) |
| |
| #define | USIC_CH_FDR_STEP_Msk (0x3ffUL) |
| |
| #define | USIC_CH_FDR_DM_Pos (14UL) |
| |
| #define | USIC_CH_FDR_DM_Msk (0xc000UL) |
| |
| #define | USIC_CH_FDR_RESULT_Pos (16UL) |
| |
| #define | USIC_CH_FDR_RESULT_Msk (0x3ff0000UL) |
| |
| #define | USIC_CH_BRG_CLKSEL_Pos (0UL) |
| |
| #define | USIC_CH_BRG_CLKSEL_Msk (0x3UL) |
| |
| #define | USIC_CH_BRG_TMEN_Pos (3UL) |
| |
| #define | USIC_CH_BRG_TMEN_Msk (0x8UL) |
| |
| #define | USIC_CH_BRG_PPPEN_Pos (4UL) |
| |
| #define | USIC_CH_BRG_PPPEN_Msk (0x10UL) |
| |
| #define | USIC_CH_BRG_CTQSEL_Pos (6UL) |
| |
| #define | USIC_CH_BRG_CTQSEL_Msk (0xc0UL) |
| |
| #define | USIC_CH_BRG_PCTQ_Pos (8UL) |
| |
| #define | USIC_CH_BRG_PCTQ_Msk (0x300UL) |
| |
| #define | USIC_CH_BRG_DCTQ_Pos (10UL) |
| |
| #define | USIC_CH_BRG_DCTQ_Msk (0x7c00UL) |
| |
| #define | USIC_CH_BRG_PDIV_Pos (16UL) |
| |
| #define | USIC_CH_BRG_PDIV_Msk (0x3ff0000UL) |
| |
| #define | USIC_CH_BRG_SCLKOSEL_Pos (28UL) |
| |
| #define | USIC_CH_BRG_SCLKOSEL_Msk (0x10000000UL) |
| |
| #define | USIC_CH_BRG_MCLKCFG_Pos (29UL) |
| |
| #define | USIC_CH_BRG_MCLKCFG_Msk (0x20000000UL) |
| |
| #define | USIC_CH_BRG_SCLKCFG_Pos (30UL) |
| |
| #define | USIC_CH_BRG_SCLKCFG_Msk (0xc0000000UL) |
| |
| #define | USIC_CH_INPR_TSINP_Pos (0UL) |
| |
| #define | USIC_CH_INPR_TSINP_Msk (0x7UL) |
| |
| #define | USIC_CH_INPR_TBINP_Pos (4UL) |
| |
| #define | USIC_CH_INPR_TBINP_Msk (0x70UL) |
| |
| #define | USIC_CH_INPR_RINP_Pos (8UL) |
| |
| #define | USIC_CH_INPR_RINP_Msk (0x700UL) |
| |
| #define | USIC_CH_INPR_AINP_Pos (12UL) |
| |
| #define | USIC_CH_INPR_AINP_Msk (0x7000UL) |
| |
| #define | USIC_CH_INPR_PINP_Pos (16UL) |
| |
| #define | USIC_CH_INPR_PINP_Msk (0x70000UL) |
| |
| #define | USIC_CH_DX0CR_DSEL_Pos (0UL) |
| |
| #define | USIC_CH_DX0CR_DSEL_Msk (0x7UL) |
| |
| #define | USIC_CH_DX0CR_INSW_Pos (4UL) |
| |
| #define | USIC_CH_DX0CR_INSW_Msk (0x10UL) |
| |
| #define | USIC_CH_DX0CR_DFEN_Pos (5UL) |
| |
| #define | USIC_CH_DX0CR_DFEN_Msk (0x20UL) |
| |
| #define | USIC_CH_DX0CR_DSEN_Pos (6UL) |
| |
| #define | USIC_CH_DX0CR_DSEN_Msk (0x40UL) |
| |
| #define | USIC_CH_DX0CR_DPOL_Pos (8UL) |
| |
| #define | USIC_CH_DX0CR_DPOL_Msk (0x100UL) |
| |
| #define | USIC_CH_DX0CR_SFSEL_Pos (9UL) |
| |
| #define | USIC_CH_DX0CR_SFSEL_Msk (0x200UL) |
| |
| #define | USIC_CH_DX0CR_CM_Pos (10UL) |
| |
| #define | USIC_CH_DX0CR_CM_Msk (0xc00UL) |
| |
| #define | USIC_CH_DX0CR_DXS_Pos (15UL) |
| |
| #define | USIC_CH_DX0CR_DXS_Msk (0x8000UL) |
| |
| #define | USIC_CH_DX1CR_DSEL_Pos (0UL) |
| |
| #define | USIC_CH_DX1CR_DSEL_Msk (0x7UL) |
| |
| #define | USIC_CH_DX1CR_DCEN_Pos (3UL) |
| |
| #define | USIC_CH_DX1CR_DCEN_Msk (0x8UL) |
| |
| #define | USIC_CH_DX1CR_INSW_Pos (4UL) |
| |
| #define | USIC_CH_DX1CR_INSW_Msk (0x10UL) |
| |
| #define | USIC_CH_DX1CR_DFEN_Pos (5UL) |
| |
| #define | USIC_CH_DX1CR_DFEN_Msk (0x20UL) |
| |
| #define | USIC_CH_DX1CR_DSEN_Pos (6UL) |
| |
| #define | USIC_CH_DX1CR_DSEN_Msk (0x40UL) |
| |
| #define | USIC_CH_DX1CR_DPOL_Pos (8UL) |
| |
| #define | USIC_CH_DX1CR_DPOL_Msk (0x100UL) |
| |
| #define | USIC_CH_DX1CR_SFSEL_Pos (9UL) |
| |
| #define | USIC_CH_DX1CR_SFSEL_Msk (0x200UL) |
| |
| #define | USIC_CH_DX1CR_CM_Pos (10UL) |
| |
| #define | USIC_CH_DX1CR_CM_Msk (0xc00UL) |
| |
| #define | USIC_CH_DX1CR_DXS_Pos (15UL) |
| |
| #define | USIC_CH_DX1CR_DXS_Msk (0x8000UL) |
| |
| #define | USIC_CH_DX2CR_DSEL_Pos (0UL) |
| |
| #define | USIC_CH_DX2CR_DSEL_Msk (0x7UL) |
| |
| #define | USIC_CH_DX2CR_INSW_Pos (4UL) |
| |
| #define | USIC_CH_DX2CR_INSW_Msk (0x10UL) |
| |
| #define | USIC_CH_DX2CR_DFEN_Pos (5UL) |
| |
| #define | USIC_CH_DX2CR_DFEN_Msk (0x20UL) |
| |
| #define | USIC_CH_DX2CR_DSEN_Pos (6UL) |
| |
| #define | USIC_CH_DX2CR_DSEN_Msk (0x40UL) |
| |
| #define | USIC_CH_DX2CR_DPOL_Pos (8UL) |
| |
| #define | USIC_CH_DX2CR_DPOL_Msk (0x100UL) |
| |
| #define | USIC_CH_DX2CR_SFSEL_Pos (9UL) |
| |
| #define | USIC_CH_DX2CR_SFSEL_Msk (0x200UL) |
| |
| #define | USIC_CH_DX2CR_CM_Pos (10UL) |
| |
| #define | USIC_CH_DX2CR_CM_Msk (0xc00UL) |
| |
| #define | USIC_CH_DX2CR_DXS_Pos (15UL) |
| |
| #define | USIC_CH_DX2CR_DXS_Msk (0x8000UL) |
| |
| #define | USIC_CH_DX3CR_DSEL_Pos (0UL) |
| |
| #define | USIC_CH_DX3CR_DSEL_Msk (0x7UL) |
| |
| #define | USIC_CH_DX3CR_INSW_Pos (4UL) |
| |
| #define | USIC_CH_DX3CR_INSW_Msk (0x10UL) |
| |
| #define | USIC_CH_DX3CR_DFEN_Pos (5UL) |
| |
| #define | USIC_CH_DX3CR_DFEN_Msk (0x20UL) |
| |
| #define | USIC_CH_DX3CR_DSEN_Pos (6UL) |
| |
| #define | USIC_CH_DX3CR_DSEN_Msk (0x40UL) |
| |
| #define | USIC_CH_DX3CR_DPOL_Pos (8UL) |
| |
| #define | USIC_CH_DX3CR_DPOL_Msk (0x100UL) |
| |
| #define | USIC_CH_DX3CR_SFSEL_Pos (9UL) |
| |
| #define | USIC_CH_DX3CR_SFSEL_Msk (0x200UL) |
| |
| #define | USIC_CH_DX3CR_CM_Pos (10UL) |
| |
| #define | USIC_CH_DX3CR_CM_Msk (0xc00UL) |
| |
| #define | USIC_CH_DX3CR_DXS_Pos (15UL) |
| |
| #define | USIC_CH_DX3CR_DXS_Msk (0x8000UL) |
| |
| #define | USIC_CH_DX4CR_DSEL_Pos (0UL) |
| |
| #define | USIC_CH_DX4CR_DSEL_Msk (0x7UL) |
| |
| #define | USIC_CH_DX4CR_INSW_Pos (4UL) |
| |
| #define | USIC_CH_DX4CR_INSW_Msk (0x10UL) |
| |
| #define | USIC_CH_DX4CR_DFEN_Pos (5UL) |
| |
| #define | USIC_CH_DX4CR_DFEN_Msk (0x20UL) |
| |
| #define | USIC_CH_DX4CR_DSEN_Pos (6UL) |
| |
| #define | USIC_CH_DX4CR_DSEN_Msk (0x40UL) |
| |
| #define | USIC_CH_DX4CR_DPOL_Pos (8UL) |
| |
| #define | USIC_CH_DX4CR_DPOL_Msk (0x100UL) |
| |
| #define | USIC_CH_DX4CR_SFSEL_Pos (9UL) |
| |
| #define | USIC_CH_DX4CR_SFSEL_Msk (0x200UL) |
| |
| #define | USIC_CH_DX4CR_CM_Pos (10UL) |
| |
| #define | USIC_CH_DX4CR_CM_Msk (0xc00UL) |
| |
| #define | USIC_CH_DX4CR_DXS_Pos (15UL) |
| |
| #define | USIC_CH_DX4CR_DXS_Msk (0x8000UL) |
| |
| #define | USIC_CH_DX5CR_DSEL_Pos (0UL) |
| |
| #define | USIC_CH_DX5CR_DSEL_Msk (0x7UL) |
| |
| #define | USIC_CH_DX5CR_INSW_Pos (4UL) |
| |
| #define | USIC_CH_DX5CR_INSW_Msk (0x10UL) |
| |
| #define | USIC_CH_DX5CR_DFEN_Pos (5UL) |
| |
| #define | USIC_CH_DX5CR_DFEN_Msk (0x20UL) |
| |
| #define | USIC_CH_DX5CR_DSEN_Pos (6UL) |
| |
| #define | USIC_CH_DX5CR_DSEN_Msk (0x40UL) |
| |
| #define | USIC_CH_DX5CR_DPOL_Pos (8UL) |
| |
| #define | USIC_CH_DX5CR_DPOL_Msk (0x100UL) |
| |
| #define | USIC_CH_DX5CR_SFSEL_Pos (9UL) |
| |
| #define | USIC_CH_DX5CR_SFSEL_Msk (0x200UL) |
| |
| #define | USIC_CH_DX5CR_CM_Pos (10UL) |
| |
| #define | USIC_CH_DX5CR_CM_Msk (0xc00UL) |
| |
| #define | USIC_CH_DX5CR_DXS_Pos (15UL) |
| |
| #define | USIC_CH_DX5CR_DXS_Msk (0x8000UL) |
| |
| #define | USIC_CH_SCTR_SDIR_Pos (0UL) |
| |
| #define | USIC_CH_SCTR_SDIR_Msk (0x1UL) |
| |
| #define | USIC_CH_SCTR_PDL_Pos (1UL) |
| |
| #define | USIC_CH_SCTR_PDL_Msk (0x2UL) |
| |
| #define | USIC_CH_SCTR_DSM_Pos (2UL) |
| |
| #define | USIC_CH_SCTR_DSM_Msk (0xcUL) |
| |
| #define | USIC_CH_SCTR_HPCDIR_Pos (4UL) |
| |
| #define | USIC_CH_SCTR_HPCDIR_Msk (0x10UL) |
| |
| #define | USIC_CH_SCTR_DOCFG_Pos (6UL) |
| |
| #define | USIC_CH_SCTR_DOCFG_Msk (0xc0UL) |
| |
| #define | USIC_CH_SCTR_TRM_Pos (8UL) |
| |
| #define | USIC_CH_SCTR_TRM_Msk (0x300UL) |
| |
| #define | USIC_CH_SCTR_FLE_Pos (16UL) |
| |
| #define | USIC_CH_SCTR_FLE_Msk (0x3f0000UL) |
| |
| #define | USIC_CH_SCTR_WLE_Pos (24UL) |
| |
| #define | USIC_CH_SCTR_WLE_Msk (0xf000000UL) |
| |
| #define | USIC_CH_TCSR_WLEMD_Pos (0UL) |
| |
| #define | USIC_CH_TCSR_WLEMD_Msk (0x1UL) |
| |
| #define | USIC_CH_TCSR_SELMD_Pos (1UL) |
| |
| #define | USIC_CH_TCSR_SELMD_Msk (0x2UL) |
| |
| #define | USIC_CH_TCSR_FLEMD_Pos (2UL) |
| |
| #define | USIC_CH_TCSR_FLEMD_Msk (0x4UL) |
| |
| #define | USIC_CH_TCSR_WAMD_Pos (3UL) |
| |
| #define | USIC_CH_TCSR_WAMD_Msk (0x8UL) |
| |
| #define | USIC_CH_TCSR_HPCMD_Pos (4UL) |
| |
| #define | USIC_CH_TCSR_HPCMD_Msk (0x10UL) |
| |
| #define | USIC_CH_TCSR_SOF_Pos (5UL) |
| |
| #define | USIC_CH_TCSR_SOF_Msk (0x20UL) |
| |
| #define | USIC_CH_TCSR_EOF_Pos (6UL) |
| |
| #define | USIC_CH_TCSR_EOF_Msk (0x40UL) |
| |
| #define | USIC_CH_TCSR_TDV_Pos (7UL) |
| |
| #define | USIC_CH_TCSR_TDV_Msk (0x80UL) |
| |
| #define | USIC_CH_TCSR_TDSSM_Pos (8UL) |
| |
| #define | USIC_CH_TCSR_TDSSM_Msk (0x100UL) |
| |
| #define | USIC_CH_TCSR_TDEN_Pos (10UL) |
| |
| #define | USIC_CH_TCSR_TDEN_Msk (0xc00UL) |
| |
| #define | USIC_CH_TCSR_TDVTR_Pos (12UL) |
| |
| #define | USIC_CH_TCSR_TDVTR_Msk (0x1000UL) |
| |
| #define | USIC_CH_TCSR_WA_Pos (13UL) |
| |
| #define | USIC_CH_TCSR_WA_Msk (0x2000UL) |
| |
| #define | USIC_CH_TCSR_TSOF_Pos (24UL) |
| |
| #define | USIC_CH_TCSR_TSOF_Msk (0x1000000UL) |
| |
| #define | USIC_CH_TCSR_TV_Pos (26UL) |
| |
| #define | USIC_CH_TCSR_TV_Msk (0x4000000UL) |
| |
| #define | USIC_CH_TCSR_TVC_Pos (27UL) |
| |
| #define | USIC_CH_TCSR_TVC_Msk (0x8000000UL) |
| |
| #define | USIC_CH_TCSR_TE_Pos (28UL) |
| |
| #define | USIC_CH_TCSR_TE_Msk (0x10000000UL) |
| |
| #define | USIC_CH_PCR_CTR0_Pos (0UL) |
| |
| #define | USIC_CH_PCR_CTR0_Msk (0x1UL) |
| |
| #define | USIC_CH_PCR_CTR1_Pos (1UL) |
| |
| #define | USIC_CH_PCR_CTR1_Msk (0x2UL) |
| |
| #define | USIC_CH_PCR_CTR2_Pos (2UL) |
| |
| #define | USIC_CH_PCR_CTR2_Msk (0x4UL) |
| |
| #define | USIC_CH_PCR_CTR3_Pos (3UL) |
| |
| #define | USIC_CH_PCR_CTR3_Msk (0x8UL) |
| |
| #define | USIC_CH_PCR_CTR4_Pos (4UL) |
| |
| #define | USIC_CH_PCR_CTR4_Msk (0x10UL) |
| |
| #define | USIC_CH_PCR_CTR5_Pos (5UL) |
| |
| #define | USIC_CH_PCR_CTR5_Msk (0x20UL) |
| |
| #define | USIC_CH_PCR_CTR6_Pos (6UL) |
| |
| #define | USIC_CH_PCR_CTR6_Msk (0x40UL) |
| |
| #define | USIC_CH_PCR_CTR7_Pos (7UL) |
| |
| #define | USIC_CH_PCR_CTR7_Msk (0x80UL) |
| |
| #define | USIC_CH_PCR_CTR8_Pos (8UL) |
| |
| #define | USIC_CH_PCR_CTR8_Msk (0x100UL) |
| |
| #define | USIC_CH_PCR_CTR9_Pos (9UL) |
| |
| #define | USIC_CH_PCR_CTR9_Msk (0x200UL) |
| |
| #define | USIC_CH_PCR_CTR10_Pos (10UL) |
| |
| #define | USIC_CH_PCR_CTR10_Msk (0x400UL) |
| |
| #define | USIC_CH_PCR_CTR11_Pos (11UL) |
| |
| #define | USIC_CH_PCR_CTR11_Msk (0x800UL) |
| |
| #define | USIC_CH_PCR_CTR12_Pos (12UL) |
| |
| #define | USIC_CH_PCR_CTR12_Msk (0x1000UL) |
| |
| #define | USIC_CH_PCR_CTR13_Pos (13UL) |
| |
| #define | USIC_CH_PCR_CTR13_Msk (0x2000UL) |
| |
| #define | USIC_CH_PCR_CTR14_Pos (14UL) |
| |
| #define | USIC_CH_PCR_CTR14_Msk (0x4000UL) |
| |
| #define | USIC_CH_PCR_CTR15_Pos (15UL) |
| |
| #define | USIC_CH_PCR_CTR15_Msk (0x8000UL) |
| |
| #define | USIC_CH_PCR_CTR16_Pos (16UL) |
| |
| #define | USIC_CH_PCR_CTR16_Msk (0x10000UL) |
| |
| #define | USIC_CH_PCR_CTR17_Pos (17UL) |
| |
| #define | USIC_CH_PCR_CTR17_Msk (0x20000UL) |
| |
| #define | USIC_CH_PCR_CTR18_Pos (18UL) |
| |
| #define | USIC_CH_PCR_CTR18_Msk (0x40000UL) |
| |
| #define | USIC_CH_PCR_CTR19_Pos (19UL) |
| |
| #define | USIC_CH_PCR_CTR19_Msk (0x80000UL) |
| |
| #define | USIC_CH_PCR_CTR20_Pos (20UL) |
| |
| #define | USIC_CH_PCR_CTR20_Msk (0x100000UL) |
| |
| #define | USIC_CH_PCR_CTR21_Pos (21UL) |
| |
| #define | USIC_CH_PCR_CTR21_Msk (0x200000UL) |
| |
| #define | USIC_CH_PCR_CTR22_Pos (22UL) |
| |
| #define | USIC_CH_PCR_CTR22_Msk (0x400000UL) |
| |
| #define | USIC_CH_PCR_CTR23_Pos (23UL) |
| |
| #define | USIC_CH_PCR_CTR23_Msk (0x800000UL) |
| |
| #define | USIC_CH_PCR_CTR24_Pos (24UL) |
| |
| #define | USIC_CH_PCR_CTR24_Msk (0x1000000UL) |
| |
| #define | USIC_CH_PCR_CTR25_Pos (25UL) |
| |
| #define | USIC_CH_PCR_CTR25_Msk (0x2000000UL) |
| |
| #define | USIC_CH_PCR_CTR26_Pos (26UL) |
| |
| #define | USIC_CH_PCR_CTR26_Msk (0x4000000UL) |
| |
| #define | USIC_CH_PCR_CTR27_Pos (27UL) |
| |
| #define | USIC_CH_PCR_CTR27_Msk (0x8000000UL) |
| |
| #define | USIC_CH_PCR_CTR28_Pos (28UL) |
| |
| #define | USIC_CH_PCR_CTR28_Msk (0x10000000UL) |
| |
| #define | USIC_CH_PCR_CTR29_Pos (29UL) |
| |
| #define | USIC_CH_PCR_CTR29_Msk (0x20000000UL) |
| |
| #define | USIC_CH_PCR_CTR30_Pos (30UL) |
| |
| #define | USIC_CH_PCR_CTR30_Msk (0x40000000UL) |
| |
| #define | USIC_CH_PCR_CTR31_Pos (31UL) |
| |
| #define | USIC_CH_PCR_CTR31_Msk (0x80000000UL) |
| |
| #define | USIC_CH_PCR_ASCMode_SMD_Pos (0UL) |
| |
| #define | USIC_CH_PCR_ASCMode_SMD_Msk (0x1UL) |
| |
| #define | USIC_CH_PCR_ASCMode_STPB_Pos (1UL) |
| |
| #define | USIC_CH_PCR_ASCMode_STPB_Msk (0x2UL) |
| |
| #define | USIC_CH_PCR_ASCMode_IDM_Pos (2UL) |
| |
| #define | USIC_CH_PCR_ASCMode_IDM_Msk (0x4UL) |
| |
| #define | USIC_CH_PCR_ASCMode_SBIEN_Pos (3UL) |
| |
| #define | USIC_CH_PCR_ASCMode_SBIEN_Msk (0x8UL) |
| |
| #define | USIC_CH_PCR_ASCMode_CDEN_Pos (4UL) |
| |
| #define | USIC_CH_PCR_ASCMode_CDEN_Msk (0x10UL) |
| |
| #define | USIC_CH_PCR_ASCMode_RNIEN_Pos (5UL) |
| |
| #define | USIC_CH_PCR_ASCMode_RNIEN_Msk (0x20UL) |
| |
| #define | USIC_CH_PCR_ASCMode_FEIEN_Pos (6UL) |
| |
| #define | USIC_CH_PCR_ASCMode_FEIEN_Msk (0x40UL) |
| |
| #define | USIC_CH_PCR_ASCMode_FFIEN_Pos (7UL) |
| |
| #define | USIC_CH_PCR_ASCMode_FFIEN_Msk (0x80UL) |
| |
| #define | USIC_CH_PCR_ASCMode_SP_Pos (8UL) |
| |
| #define | USIC_CH_PCR_ASCMode_SP_Msk (0x1f00UL) |
| |
| #define | USIC_CH_PCR_ASCMode_PL_Pos (13UL) |
| |
| #define | USIC_CH_PCR_ASCMode_PL_Msk (0xe000UL) |
| |
| #define | USIC_CH_PCR_ASCMode_RSTEN_Pos (16UL) |
| |
| #define | USIC_CH_PCR_ASCMode_RSTEN_Msk (0x10000UL) |
| |
| #define | USIC_CH_PCR_ASCMode_TSTEN_Pos (17UL) |
| |
| #define | USIC_CH_PCR_ASCMode_TSTEN_Msk (0x20000UL) |
| |
| #define | USIC_CH_PCR_ASCMode_MCLK_Pos (31UL) |
| |
| #define | USIC_CH_PCR_ASCMode_MCLK_Msk (0x80000000UL) |
| |
| #define | USIC_CH_PCR_SSCMode_MSLSEN_Pos (0UL) |
| |
| #define | USIC_CH_PCR_SSCMode_MSLSEN_Msk (0x1UL) |
| |
| #define | USIC_CH_PCR_SSCMode_SELCTR_Pos (1UL) |
| |
| #define | USIC_CH_PCR_SSCMode_SELCTR_Msk (0x2UL) |
| |
| #define | USIC_CH_PCR_SSCMode_SELINV_Pos (2UL) |
| |
| #define | USIC_CH_PCR_SSCMode_SELINV_Msk (0x4UL) |
| |
| #define | USIC_CH_PCR_SSCMode_FEM_Pos (3UL) |
| |
| #define | USIC_CH_PCR_SSCMode_FEM_Msk (0x8UL) |
| |
| #define | USIC_CH_PCR_SSCMode_CTQSEL1_Pos (4UL) |
| |
| #define | USIC_CH_PCR_SSCMode_CTQSEL1_Msk (0x30UL) |
| |
| #define | USIC_CH_PCR_SSCMode_PCTQ1_Pos (6UL) |
| |
| #define | USIC_CH_PCR_SSCMode_PCTQ1_Msk (0xc0UL) |
| |
| #define | USIC_CH_PCR_SSCMode_DCTQ1_Pos (8UL) |
| |
| #define | USIC_CH_PCR_SSCMode_DCTQ1_Msk (0x1f00UL) |
| |
| #define | USIC_CH_PCR_SSCMode_PARIEN_Pos (13UL) |
| |
| #define | USIC_CH_PCR_SSCMode_PARIEN_Msk (0x2000UL) |
| |
| #define | USIC_CH_PCR_SSCMode_MSLSIEN_Pos (14UL) |
| |
| #define | USIC_CH_PCR_SSCMode_MSLSIEN_Msk (0x4000UL) |
| |
| #define | USIC_CH_PCR_SSCMode_DX2TIEN_Pos (15UL) |
| |
| #define | USIC_CH_PCR_SSCMode_DX2TIEN_Msk (0x8000UL) |
| |
| #define | USIC_CH_PCR_SSCMode_SELO_Pos (16UL) |
| |
| #define | USIC_CH_PCR_SSCMode_SELO_Msk (0xff0000UL) |
| |
| #define | USIC_CH_PCR_SSCMode_TIWEN_Pos (24UL) |
| |
| #define | USIC_CH_PCR_SSCMode_TIWEN_Msk (0x1000000UL) |
| |
| #define | USIC_CH_PCR_SSCMode_SLPHSEL_Pos (25UL) |
| |
| #define | USIC_CH_PCR_SSCMode_SLPHSEL_Msk (0x2000000UL) |
| |
| #define | USIC_CH_PCR_SSCMode_MCLK_Pos (31UL) |
| |
| #define | USIC_CH_PCR_SSCMode_MCLK_Msk (0x80000000UL) |
| |
| #define | USIC_CH_PCR_IICMode_SLAD_Pos (0UL) |
| |
| #define | USIC_CH_PCR_IICMode_SLAD_Msk (0xffffUL) |
| |
| #define | USIC_CH_PCR_IICMode_ACK00_Pos (16UL) |
| |
| #define | USIC_CH_PCR_IICMode_ACK00_Msk (0x10000UL) |
| |
| #define | USIC_CH_PCR_IICMode_STIM_Pos (17UL) |
| |
| #define | USIC_CH_PCR_IICMode_STIM_Msk (0x20000UL) |
| |
| #define | USIC_CH_PCR_IICMode_SCRIEN_Pos (18UL) |
| |
| #define | USIC_CH_PCR_IICMode_SCRIEN_Msk (0x40000UL) |
| |
| #define | USIC_CH_PCR_IICMode_RSCRIEN_Pos (19UL) |
| |
| #define | USIC_CH_PCR_IICMode_RSCRIEN_Msk (0x80000UL) |
| |
| #define | USIC_CH_PCR_IICMode_PCRIEN_Pos (20UL) |
| |
| #define | USIC_CH_PCR_IICMode_PCRIEN_Msk (0x100000UL) |
| |
| #define | USIC_CH_PCR_IICMode_NACKIEN_Pos (21UL) |
| |
| #define | USIC_CH_PCR_IICMode_NACKIEN_Msk (0x200000UL) |
| |
| #define | USIC_CH_PCR_IICMode_ARLIEN_Pos (22UL) |
| |
| #define | USIC_CH_PCR_IICMode_ARLIEN_Msk (0x400000UL) |
| |
| #define | USIC_CH_PCR_IICMode_SRRIEN_Pos (23UL) |
| |
| #define | USIC_CH_PCR_IICMode_SRRIEN_Msk (0x800000UL) |
| |
| #define | USIC_CH_PCR_IICMode_ERRIEN_Pos (24UL) |
| |
| #define | USIC_CH_PCR_IICMode_ERRIEN_Msk (0x1000000UL) |
| |
| #define | USIC_CH_PCR_IICMode_SACKDIS_Pos (25UL) |
| |
| #define | USIC_CH_PCR_IICMode_SACKDIS_Msk (0x2000000UL) |
| |
| #define | USIC_CH_PCR_IICMode_HDEL_Pos (26UL) |
| |
| #define | USIC_CH_PCR_IICMode_HDEL_Msk (0x3c000000UL) |
| |
| #define | USIC_CH_PCR_IICMode_ACKIEN_Pos (30UL) |
| |
| #define | USIC_CH_PCR_IICMode_ACKIEN_Msk (0x40000000UL) |
| |
| #define | USIC_CH_PCR_IICMode_MCLK_Pos (31UL) |
| |
| #define | USIC_CH_PCR_IICMode_MCLK_Msk (0x80000000UL) |
| |
| #define | USIC_CH_PCR_IISMode_WAGEN_Pos (0UL) |
| |
| #define | USIC_CH_PCR_IISMode_WAGEN_Msk (0x1UL) |
| |
| #define | USIC_CH_PCR_IISMode_DTEN_Pos (1UL) |
| |
| #define | USIC_CH_PCR_IISMode_DTEN_Msk (0x2UL) |
| |
| #define | USIC_CH_PCR_IISMode_SELINV_Pos (2UL) |
| |
| #define | USIC_CH_PCR_IISMode_SELINV_Msk (0x4UL) |
| |
| #define | USIC_CH_PCR_IISMode_WAFEIEN_Pos (4UL) |
| |
| #define | USIC_CH_PCR_IISMode_WAFEIEN_Msk (0x10UL) |
| |
| #define | USIC_CH_PCR_IISMode_WAREIEN_Pos (5UL) |
| |
| #define | USIC_CH_PCR_IISMode_WAREIEN_Msk (0x20UL) |
| |
| #define | USIC_CH_PCR_IISMode_ENDIEN_Pos (6UL) |
| |
| #define | USIC_CH_PCR_IISMode_ENDIEN_Msk (0x40UL) |
| |
| #define | USIC_CH_PCR_IISMode_DX2TIEN_Pos (15UL) |
| |
| #define | USIC_CH_PCR_IISMode_DX2TIEN_Msk (0x8000UL) |
| |
| #define | USIC_CH_PCR_IISMode_TDEL_Pos (16UL) |
| |
| #define | USIC_CH_PCR_IISMode_TDEL_Msk (0x3f0000UL) |
| |
| #define | USIC_CH_PCR_IISMode_MCLK_Pos (31UL) |
| |
| #define | USIC_CH_PCR_IISMode_MCLK_Msk (0x80000000UL) |
| |
| #define | USIC_CH_CCR_MODE_Pos (0UL) |
| |
| #define | USIC_CH_CCR_MODE_Msk (0xfUL) |
| |
| #define | USIC_CH_CCR_HPCEN_Pos (6UL) |
| |
| #define | USIC_CH_CCR_HPCEN_Msk (0xc0UL) |
| |
| #define | USIC_CH_CCR_PM_Pos (8UL) |
| |
| #define | USIC_CH_CCR_PM_Msk (0x300UL) |
| |
| #define | USIC_CH_CCR_RSIEN_Pos (10UL) |
| |
| #define | USIC_CH_CCR_RSIEN_Msk (0x400UL) |
| |
| #define | USIC_CH_CCR_DLIEN_Pos (11UL) |
| |
| #define | USIC_CH_CCR_DLIEN_Msk (0x800UL) |
| |
| #define | USIC_CH_CCR_TSIEN_Pos (12UL) |
| |
| #define | USIC_CH_CCR_TSIEN_Msk (0x1000UL) |
| |
| #define | USIC_CH_CCR_TBIEN_Pos (13UL) |
| |
| #define | USIC_CH_CCR_TBIEN_Msk (0x2000UL) |
| |
| #define | USIC_CH_CCR_RIEN_Pos (14UL) |
| |
| #define | USIC_CH_CCR_RIEN_Msk (0x4000UL) |
| |
| #define | USIC_CH_CCR_AIEN_Pos (15UL) |
| |
| #define | USIC_CH_CCR_AIEN_Msk (0x8000UL) |
| |
| #define | USIC_CH_CCR_BRGIEN_Pos (16UL) |
| |
| #define | USIC_CH_CCR_BRGIEN_Msk (0x10000UL) |
| |
| #define | USIC_CH_CMTR_CTV_Pos (0UL) |
| |
| #define | USIC_CH_CMTR_CTV_Msk (0x3ffUL) |
| |
| #define | USIC_CH_PSR_ST0_Pos (0UL) |
| |
| #define | USIC_CH_PSR_ST0_Msk (0x1UL) |
| |
| #define | USIC_CH_PSR_ST1_Pos (1UL) |
| |
| #define | USIC_CH_PSR_ST1_Msk (0x2UL) |
| |
| #define | USIC_CH_PSR_ST2_Pos (2UL) |
| |
| #define | USIC_CH_PSR_ST2_Msk (0x4UL) |
| |
| #define | USIC_CH_PSR_ST3_Pos (3UL) |
| |
| #define | USIC_CH_PSR_ST3_Msk (0x8UL) |
| |
| #define | USIC_CH_PSR_ST4_Pos (4UL) |
| |
| #define | USIC_CH_PSR_ST4_Msk (0x10UL) |
| |
| #define | USIC_CH_PSR_ST5_Pos (5UL) |
| |
| #define | USIC_CH_PSR_ST5_Msk (0x20UL) |
| |
| #define | USIC_CH_PSR_ST6_Pos (6UL) |
| |
| #define | USIC_CH_PSR_ST6_Msk (0x40UL) |
| |
| #define | USIC_CH_PSR_ST7_Pos (7UL) |
| |
| #define | USIC_CH_PSR_ST7_Msk (0x80UL) |
| |
| #define | USIC_CH_PSR_ST8_Pos (8UL) |
| |
| #define | USIC_CH_PSR_ST8_Msk (0x100UL) |
| |
| #define | USIC_CH_PSR_ST9_Pos (9UL) |
| |
| #define | USIC_CH_PSR_ST9_Msk (0x200UL) |
| |
| #define | USIC_CH_PSR_RSIF_Pos (10UL) |
| |
| #define | USIC_CH_PSR_RSIF_Msk (0x400UL) |
| |
| #define | USIC_CH_PSR_DLIF_Pos (11UL) |
| |
| #define | USIC_CH_PSR_DLIF_Msk (0x800UL) |
| |
| #define | USIC_CH_PSR_TSIF_Pos (12UL) |
| |
| #define | USIC_CH_PSR_TSIF_Msk (0x1000UL) |
| |
| #define | USIC_CH_PSR_TBIF_Pos (13UL) |
| |
| #define | USIC_CH_PSR_TBIF_Msk (0x2000UL) |
| |
| #define | USIC_CH_PSR_RIF_Pos (14UL) |
| |
| #define | USIC_CH_PSR_RIF_Msk (0x4000UL) |
| |
| #define | USIC_CH_PSR_AIF_Pos (15UL) |
| |
| #define | USIC_CH_PSR_AIF_Msk (0x8000UL) |
| |
| #define | USIC_CH_PSR_BRGIF_Pos (16UL) |
| |
| #define | USIC_CH_PSR_BRGIF_Msk (0x10000UL) |
| |
| #define | USIC_CH_PSR_ASCMode_TXIDLE_Pos (0UL) |
| |
| #define | USIC_CH_PSR_ASCMode_TXIDLE_Msk (0x1UL) |
| |
| #define | USIC_CH_PSR_ASCMode_RXIDLE_Pos (1UL) |
| |
| #define | USIC_CH_PSR_ASCMode_RXIDLE_Msk (0x2UL) |
| |
| #define | USIC_CH_PSR_ASCMode_SBD_Pos (2UL) |
| |
| #define | USIC_CH_PSR_ASCMode_SBD_Msk (0x4UL) |
| |
| #define | USIC_CH_PSR_ASCMode_COL_Pos (3UL) |
| |
| #define | USIC_CH_PSR_ASCMode_COL_Msk (0x8UL) |
| |
| #define | USIC_CH_PSR_ASCMode_RNS_Pos (4UL) |
| |
| #define | USIC_CH_PSR_ASCMode_RNS_Msk (0x10UL) |
| |
| #define | USIC_CH_PSR_ASCMode_FER0_Pos (5UL) |
| |
| #define | USIC_CH_PSR_ASCMode_FER0_Msk (0x20UL) |
| |
| #define | USIC_CH_PSR_ASCMode_FER1_Pos (6UL) |
| |
| #define | USIC_CH_PSR_ASCMode_FER1_Msk (0x40UL) |
| |
| #define | USIC_CH_PSR_ASCMode_RFF_Pos (7UL) |
| |
| #define | USIC_CH_PSR_ASCMode_RFF_Msk (0x80UL) |
| |
| #define | USIC_CH_PSR_ASCMode_TFF_Pos (8UL) |
| |
| #define | USIC_CH_PSR_ASCMode_TFF_Msk (0x100UL) |
| |
| #define | USIC_CH_PSR_ASCMode_BUSY_Pos (9UL) |
| |
| #define | USIC_CH_PSR_ASCMode_BUSY_Msk (0x200UL) |
| |
| #define | USIC_CH_PSR_ASCMode_RSIF_Pos (10UL) |
| |
| #define | USIC_CH_PSR_ASCMode_RSIF_Msk (0x400UL) |
| |
| #define | USIC_CH_PSR_ASCMode_DLIF_Pos (11UL) |
| |
| #define | USIC_CH_PSR_ASCMode_DLIF_Msk (0x800UL) |
| |
| #define | USIC_CH_PSR_ASCMode_TSIF_Pos (12UL) |
| |
| #define | USIC_CH_PSR_ASCMode_TSIF_Msk (0x1000UL) |
| |
| #define | USIC_CH_PSR_ASCMode_TBIF_Pos (13UL) |
| |
| #define | USIC_CH_PSR_ASCMode_TBIF_Msk (0x2000UL) |
| |
| #define | USIC_CH_PSR_ASCMode_RIF_Pos (14UL) |
| |
| #define | USIC_CH_PSR_ASCMode_RIF_Msk (0x4000UL) |
| |
| #define | USIC_CH_PSR_ASCMode_AIF_Pos (15UL) |
| |
| #define | USIC_CH_PSR_ASCMode_AIF_Msk (0x8000UL) |
| |
| #define | USIC_CH_PSR_ASCMode_BRGIF_Pos (16UL) |
| |
| #define | USIC_CH_PSR_ASCMode_BRGIF_Msk (0x10000UL) |
| |
| #define | USIC_CH_PSR_SSCMode_MSLS_Pos (0UL) |
| |
| #define | USIC_CH_PSR_SSCMode_MSLS_Msk (0x1UL) |
| |
| #define | USIC_CH_PSR_SSCMode_DX2S_Pos (1UL) |
| |
| #define | USIC_CH_PSR_SSCMode_DX2S_Msk (0x2UL) |
| |
| #define | USIC_CH_PSR_SSCMode_MSLSEV_Pos (2UL) |
| |
| #define | USIC_CH_PSR_SSCMode_MSLSEV_Msk (0x4UL) |
| |
| #define | USIC_CH_PSR_SSCMode_DX2TEV_Pos (3UL) |
| |
| #define | USIC_CH_PSR_SSCMode_DX2TEV_Msk (0x8UL) |
| |
| #define | USIC_CH_PSR_SSCMode_PARERR_Pos (4UL) |
| |
| #define | USIC_CH_PSR_SSCMode_PARERR_Msk (0x10UL) |
| |
| #define | USIC_CH_PSR_SSCMode_RSIF_Pos (10UL) |
| |
| #define | USIC_CH_PSR_SSCMode_RSIF_Msk (0x400UL) |
| |
| #define | USIC_CH_PSR_SSCMode_DLIF_Pos (11UL) |
| |
| #define | USIC_CH_PSR_SSCMode_DLIF_Msk (0x800UL) |
| |
| #define | USIC_CH_PSR_SSCMode_TSIF_Pos (12UL) |
| |
| #define | USIC_CH_PSR_SSCMode_TSIF_Msk (0x1000UL) |
| |
| #define | USIC_CH_PSR_SSCMode_TBIF_Pos (13UL) |
| |
| #define | USIC_CH_PSR_SSCMode_TBIF_Msk (0x2000UL) |
| |
| #define | USIC_CH_PSR_SSCMode_RIF_Pos (14UL) |
| |
| #define | USIC_CH_PSR_SSCMode_RIF_Msk (0x4000UL) |
| |
| #define | USIC_CH_PSR_SSCMode_AIF_Pos (15UL) |
| |
| #define | USIC_CH_PSR_SSCMode_AIF_Msk (0x8000UL) |
| |
| #define | USIC_CH_PSR_SSCMode_BRGIF_Pos (16UL) |
| |
| #define | USIC_CH_PSR_SSCMode_BRGIF_Msk (0x10000UL) |
| |
| #define | USIC_CH_PSR_IICMode_SLSEL_Pos (0UL) |
| |
| #define | USIC_CH_PSR_IICMode_SLSEL_Msk (0x1UL) |
| |
| #define | USIC_CH_PSR_IICMode_WTDF_Pos (1UL) |
| |
| #define | USIC_CH_PSR_IICMode_WTDF_Msk (0x2UL) |
| |
| #define | USIC_CH_PSR_IICMode_SCR_Pos (2UL) |
| |
| #define | USIC_CH_PSR_IICMode_SCR_Msk (0x4UL) |
| |
| #define | USIC_CH_PSR_IICMode_RSCR_Pos (3UL) |
| |
| #define | USIC_CH_PSR_IICMode_RSCR_Msk (0x8UL) |
| |
| #define | USIC_CH_PSR_IICMode_PCR_Pos (4UL) |
| |
| #define | USIC_CH_PSR_IICMode_PCR_Msk (0x10UL) |
| |
| #define | USIC_CH_PSR_IICMode_NACK_Pos (5UL) |
| |
| #define | USIC_CH_PSR_IICMode_NACK_Msk (0x20UL) |
| |
| #define | USIC_CH_PSR_IICMode_ARL_Pos (6UL) |
| |
| #define | USIC_CH_PSR_IICMode_ARL_Msk (0x40UL) |
| |
| #define | USIC_CH_PSR_IICMode_SRR_Pos (7UL) |
| |
| #define | USIC_CH_PSR_IICMode_SRR_Msk (0x80UL) |
| |
| #define | USIC_CH_PSR_IICMode_ERR_Pos (8UL) |
| |
| #define | USIC_CH_PSR_IICMode_ERR_Msk (0x100UL) |
| |
| #define | USIC_CH_PSR_IICMode_ACK_Pos (9UL) |
| |
| #define | USIC_CH_PSR_IICMode_ACK_Msk (0x200UL) |
| |
| #define | USIC_CH_PSR_IICMode_RSIF_Pos (10UL) |
| |
| #define | USIC_CH_PSR_IICMode_RSIF_Msk (0x400UL) |
| |
| #define | USIC_CH_PSR_IICMode_DLIF_Pos (11UL) |
| |
| #define | USIC_CH_PSR_IICMode_DLIF_Msk (0x800UL) |
| |
| #define | USIC_CH_PSR_IICMode_TSIF_Pos (12UL) |
| |
| #define | USIC_CH_PSR_IICMode_TSIF_Msk (0x1000UL) |
| |
| #define | USIC_CH_PSR_IICMode_TBIF_Pos (13UL) |
| |
| #define | USIC_CH_PSR_IICMode_TBIF_Msk (0x2000UL) |
| |
| #define | USIC_CH_PSR_IICMode_RIF_Pos (14UL) |
| |
| #define | USIC_CH_PSR_IICMode_RIF_Msk (0x4000UL) |
| |
| #define | USIC_CH_PSR_IICMode_AIF_Pos (15UL) |
| |
| #define | USIC_CH_PSR_IICMode_AIF_Msk (0x8000UL) |
| |
| #define | USIC_CH_PSR_IICMode_BRGIF_Pos (16UL) |
| |
| #define | USIC_CH_PSR_IICMode_BRGIF_Msk (0x10000UL) |
| |
| #define | USIC_CH_PSR_IISMode_WA_Pos (0UL) |
| |
| #define | USIC_CH_PSR_IISMode_WA_Msk (0x1UL) |
| |
| #define | USIC_CH_PSR_IISMode_DX2S_Pos (1UL) |
| |
| #define | USIC_CH_PSR_IISMode_DX2S_Msk (0x2UL) |
| |
| #define | USIC_CH_PSR_IISMode_DX2TEV_Pos (3UL) |
| |
| #define | USIC_CH_PSR_IISMode_DX2TEV_Msk (0x8UL) |
| |
| #define | USIC_CH_PSR_IISMode_WAFE_Pos (4UL) |
| |
| #define | USIC_CH_PSR_IISMode_WAFE_Msk (0x10UL) |
| |
| #define | USIC_CH_PSR_IISMode_WARE_Pos (5UL) |
| |
| #define | USIC_CH_PSR_IISMode_WARE_Msk (0x20UL) |
| |
| #define | USIC_CH_PSR_IISMode_END_Pos (6UL) |
| |
| #define | USIC_CH_PSR_IISMode_END_Msk (0x40UL) |
| |
| #define | USIC_CH_PSR_IISMode_RSIF_Pos (10UL) |
| |
| #define | USIC_CH_PSR_IISMode_RSIF_Msk (0x400UL) |
| |
| #define | USIC_CH_PSR_IISMode_DLIF_Pos (11UL) |
| |
| #define | USIC_CH_PSR_IISMode_DLIF_Msk (0x800UL) |
| |
| #define | USIC_CH_PSR_IISMode_TSIF_Pos (12UL) |
| |
| #define | USIC_CH_PSR_IISMode_TSIF_Msk (0x1000UL) |
| |
| #define | USIC_CH_PSR_IISMode_TBIF_Pos (13UL) |
| |
| #define | USIC_CH_PSR_IISMode_TBIF_Msk (0x2000UL) |
| |
| #define | USIC_CH_PSR_IISMode_RIF_Pos (14UL) |
| |
| #define | USIC_CH_PSR_IISMode_RIF_Msk (0x4000UL) |
| |
| #define | USIC_CH_PSR_IISMode_AIF_Pos (15UL) |
| |
| #define | USIC_CH_PSR_IISMode_AIF_Msk (0x8000UL) |
| |
| #define | USIC_CH_PSR_IISMode_BRGIF_Pos (16UL) |
| |
| #define | USIC_CH_PSR_IISMode_BRGIF_Msk (0x10000UL) |
| |
| #define | USIC_CH_PSCR_CST0_Pos (0UL) |
| |
| #define | USIC_CH_PSCR_CST0_Msk (0x1UL) |
| |
| #define | USIC_CH_PSCR_CST1_Pos (1UL) |
| |
| #define | USIC_CH_PSCR_CST1_Msk (0x2UL) |
| |
| #define | USIC_CH_PSCR_CST2_Pos (2UL) |
| |
| #define | USIC_CH_PSCR_CST2_Msk (0x4UL) |
| |
| #define | USIC_CH_PSCR_CST3_Pos (3UL) |
| |
| #define | USIC_CH_PSCR_CST3_Msk (0x8UL) |
| |
| #define | USIC_CH_PSCR_CST4_Pos (4UL) |
| |
| #define | USIC_CH_PSCR_CST4_Msk (0x10UL) |
| |
| #define | USIC_CH_PSCR_CST5_Pos (5UL) |
| |
| #define | USIC_CH_PSCR_CST5_Msk (0x20UL) |
| |
| #define | USIC_CH_PSCR_CST6_Pos (6UL) |
| |
| #define | USIC_CH_PSCR_CST6_Msk (0x40UL) |
| |
| #define | USIC_CH_PSCR_CST7_Pos (7UL) |
| |
| #define | USIC_CH_PSCR_CST7_Msk (0x80UL) |
| |
| #define | USIC_CH_PSCR_CST8_Pos (8UL) |
| |
| #define | USIC_CH_PSCR_CST8_Msk (0x100UL) |
| |
| #define | USIC_CH_PSCR_CST9_Pos (9UL) |
| |
| #define | USIC_CH_PSCR_CST9_Msk (0x200UL) |
| |
| #define | USIC_CH_PSCR_CRSIF_Pos (10UL) |
| |
| #define | USIC_CH_PSCR_CRSIF_Msk (0x400UL) |
| |
| #define | USIC_CH_PSCR_CDLIF_Pos (11UL) |
| |
| #define | USIC_CH_PSCR_CDLIF_Msk (0x800UL) |
| |
| #define | USIC_CH_PSCR_CTSIF_Pos (12UL) |
| |
| #define | USIC_CH_PSCR_CTSIF_Msk (0x1000UL) |
| |
| #define | USIC_CH_PSCR_CTBIF_Pos (13UL) |
| |
| #define | USIC_CH_PSCR_CTBIF_Msk (0x2000UL) |
| |
| #define | USIC_CH_PSCR_CRIF_Pos (14UL) |
| |
| #define | USIC_CH_PSCR_CRIF_Msk (0x4000UL) |
| |
| #define | USIC_CH_PSCR_CAIF_Pos (15UL) |
| |
| #define | USIC_CH_PSCR_CAIF_Msk (0x8000UL) |
| |
| #define | USIC_CH_PSCR_CBRGIF_Pos (16UL) |
| |
| #define | USIC_CH_PSCR_CBRGIF_Msk (0x10000UL) |
| |
| #define | USIC_CH_RBUFSR_WLEN_Pos (0UL) |
| |
| #define | USIC_CH_RBUFSR_WLEN_Msk (0xfUL) |
| |
| #define | USIC_CH_RBUFSR_SOF_Pos (6UL) |
| |
| #define | USIC_CH_RBUFSR_SOF_Msk (0x40UL) |
| |
| #define | USIC_CH_RBUFSR_PAR_Pos (8UL) |
| |
| #define | USIC_CH_RBUFSR_PAR_Msk (0x100UL) |
| |
| #define | USIC_CH_RBUFSR_PERR_Pos (9UL) |
| |
| #define | USIC_CH_RBUFSR_PERR_Msk (0x200UL) |
| |
| #define | USIC_CH_RBUFSR_RDV0_Pos (13UL) |
| |
| #define | USIC_CH_RBUFSR_RDV0_Msk (0x2000UL) |
| |
| #define | USIC_CH_RBUFSR_RDV1_Pos (14UL) |
| |
| #define | USIC_CH_RBUFSR_RDV1_Msk (0x4000UL) |
| |
| #define | USIC_CH_RBUFSR_DS_Pos (15UL) |
| |
| #define | USIC_CH_RBUFSR_DS_Msk (0x8000UL) |
| |
| #define | USIC_CH_RBUF_DSR_Pos (0UL) |
| |
| #define | USIC_CH_RBUF_DSR_Msk (0xffffUL) |
| |
| #define | USIC_CH_RBUFD_DSR_Pos (0UL) |
| |
| #define | USIC_CH_RBUFD_DSR_Msk (0xffffUL) |
| |
| #define | USIC_CH_RBUF0_DSR0_Pos (0UL) |
| |
| #define | USIC_CH_RBUF0_DSR0_Msk (0xffffUL) |
| |
| #define | USIC_CH_RBUF1_DSR1_Pos (0UL) |
| |
| #define | USIC_CH_RBUF1_DSR1_Msk (0xffffUL) |
| |
| #define | USIC_CH_RBUF01SR_WLEN0_Pos (0UL) |
| |
| #define | USIC_CH_RBUF01SR_WLEN0_Msk (0xfUL) |
| |
| #define | USIC_CH_RBUF01SR_SOF0_Pos (6UL) |
| |
| #define | USIC_CH_RBUF01SR_SOF0_Msk (0x40UL) |
| |
| #define | USIC_CH_RBUF01SR_PAR0_Pos (8UL) |
| |
| #define | USIC_CH_RBUF01SR_PAR0_Msk (0x100UL) |
| |
| #define | USIC_CH_RBUF01SR_PERR0_Pos (9UL) |
| |
| #define | USIC_CH_RBUF01SR_PERR0_Msk (0x200UL) |
| |
| #define | USIC_CH_RBUF01SR_RDV00_Pos (13UL) |
| |
| #define | USIC_CH_RBUF01SR_RDV00_Msk (0x2000UL) |
| |
| #define | USIC_CH_RBUF01SR_RDV01_Pos (14UL) |
| |
| #define | USIC_CH_RBUF01SR_RDV01_Msk (0x4000UL) |
| |
| #define | USIC_CH_RBUF01SR_DS0_Pos (15UL) |
| |
| #define | USIC_CH_RBUF01SR_DS0_Msk (0x8000UL) |
| |
| #define | USIC_CH_RBUF01SR_WLEN1_Pos (16UL) |
| |
| #define | USIC_CH_RBUF01SR_WLEN1_Msk (0xf0000UL) |
| |
| #define | USIC_CH_RBUF01SR_SOF1_Pos (22UL) |
| |
| #define | USIC_CH_RBUF01SR_SOF1_Msk (0x400000UL) |
| |
| #define | USIC_CH_RBUF01SR_PAR1_Pos (24UL) |
| |
| #define | USIC_CH_RBUF01SR_PAR1_Msk (0x1000000UL) |
| |
| #define | USIC_CH_RBUF01SR_PERR1_Pos (25UL) |
| |
| #define | USIC_CH_RBUF01SR_PERR1_Msk (0x2000000UL) |
| |
| #define | USIC_CH_RBUF01SR_RDV10_Pos (29UL) |
| |
| #define | USIC_CH_RBUF01SR_RDV10_Msk (0x20000000UL) |
| |
| #define | USIC_CH_RBUF01SR_RDV11_Pos (30UL) |
| |
| #define | USIC_CH_RBUF01SR_RDV11_Msk (0x40000000UL) |
| |
| #define | USIC_CH_RBUF01SR_DS1_Pos (31UL) |
| |
| #define | USIC_CH_RBUF01SR_DS1_Msk (0x80000000UL) |
| |
| #define | USIC_CH_FMR_MTDV_Pos (0UL) |
| |
| #define | USIC_CH_FMR_MTDV_Msk (0x3UL) |
| |
| #define | USIC_CH_FMR_ATVC_Pos (4UL) |
| |
| #define | USIC_CH_FMR_ATVC_Msk (0x10UL) |
| |
| #define | USIC_CH_FMR_CRDV0_Pos (14UL) |
| |
| #define | USIC_CH_FMR_CRDV0_Msk (0x4000UL) |
| |
| #define | USIC_CH_FMR_CRDV1_Pos (15UL) |
| |
| #define | USIC_CH_FMR_CRDV1_Msk (0x8000UL) |
| |
| #define | USIC_CH_FMR_SIO0_Pos (16UL) |
| |
| #define | USIC_CH_FMR_SIO0_Msk (0x10000UL) |
| |
| #define | USIC_CH_FMR_SIO1_Pos (17UL) |
| |
| #define | USIC_CH_FMR_SIO1_Msk (0x20000UL) |
| |
| #define | USIC_CH_FMR_SIO2_Pos (18UL) |
| |
| #define | USIC_CH_FMR_SIO2_Msk (0x40000UL) |
| |
| #define | USIC_CH_FMR_SIO3_Pos (19UL) |
| |
| #define | USIC_CH_FMR_SIO3_Msk (0x80000UL) |
| |
| #define | USIC_CH_FMR_SIO4_Pos (20UL) |
| |
| #define | USIC_CH_FMR_SIO4_Msk (0x100000UL) |
| |
| #define | USIC_CH_FMR_SIO5_Pos (21UL) |
| |
| #define | USIC_CH_FMR_SIO5_Msk (0x200000UL) |
| |
| #define | USIC_CH_TBUF_TDATA_Pos (0UL) |
| |
| #define | USIC_CH_TBUF_TDATA_Msk (0xffffUL) |
| |
| #define | USIC_CH_BYP_BDATA_Pos (0UL) |
| |
| #define | USIC_CH_BYP_BDATA_Msk (0xffffUL) |
| |
| #define | USIC_CH_BYPCR_BWLE_Pos (0UL) |
| |
| #define | USIC_CH_BYPCR_BWLE_Msk (0xfUL) |
| |
| #define | USIC_CH_BYPCR_BDSSM_Pos (8UL) |
| |
| #define | USIC_CH_BYPCR_BDSSM_Msk (0x100UL) |
| |
| #define | USIC_CH_BYPCR_BDEN_Pos (10UL) |
| |
| #define | USIC_CH_BYPCR_BDEN_Msk (0xc00UL) |
| |
| #define | USIC_CH_BYPCR_BDVTR_Pos (12UL) |
| |
| #define | USIC_CH_BYPCR_BDVTR_Msk (0x1000UL) |
| |
| #define | USIC_CH_BYPCR_BPRIO_Pos (13UL) |
| |
| #define | USIC_CH_BYPCR_BPRIO_Msk (0x2000UL) |
| |
| #define | USIC_CH_BYPCR_BDV_Pos (15UL) |
| |
| #define | USIC_CH_BYPCR_BDV_Msk (0x8000UL) |
| |
| #define | USIC_CH_BYPCR_BSELO_Pos (16UL) |
| |
| #define | USIC_CH_BYPCR_BSELO_Msk (0x1f0000UL) |
| |
| #define | USIC_CH_BYPCR_BHPC_Pos (21UL) |
| |
| #define | USIC_CH_BYPCR_BHPC_Msk (0xe00000UL) |
| |
| #define | USIC_CH_TBCTR_DPTR_Pos (0UL) |
| |
| #define | USIC_CH_TBCTR_DPTR_Msk (0x3fUL) |
| |
| #define | USIC_CH_TBCTR_LIMIT_Pos (8UL) |
| |
| #define | USIC_CH_TBCTR_LIMIT_Msk (0x3f00UL) |
| |
| #define | USIC_CH_TBCTR_STBTM_Pos (14UL) |
| |
| #define | USIC_CH_TBCTR_STBTM_Msk (0x4000UL) |
| |
| #define | USIC_CH_TBCTR_STBTEN_Pos (15UL) |
| |
| #define | USIC_CH_TBCTR_STBTEN_Msk (0x8000UL) |
| |
| #define | USIC_CH_TBCTR_STBINP_Pos (16UL) |
| |
| #define | USIC_CH_TBCTR_STBINP_Msk (0x70000UL) |
| |
| #define | USIC_CH_TBCTR_ATBINP_Pos (19UL) |
| |
| #define | USIC_CH_TBCTR_ATBINP_Msk (0x380000UL) |
| |
| #define | USIC_CH_TBCTR_SIZE_Pos (24UL) |
| |
| #define | USIC_CH_TBCTR_SIZE_Msk (0x7000000UL) |
| |
| #define | USIC_CH_TBCTR_LOF_Pos (28UL) |
| |
| #define | USIC_CH_TBCTR_LOF_Msk (0x10000000UL) |
| |
| #define | USIC_CH_TBCTR_STBIEN_Pos (30UL) |
| |
| #define | USIC_CH_TBCTR_STBIEN_Msk (0x40000000UL) |
| |
| #define | USIC_CH_TBCTR_TBERIEN_Pos (31UL) |
| |
| #define | USIC_CH_TBCTR_TBERIEN_Msk (0x80000000UL) |
| |
| #define | USIC_CH_RBCTR_DPTR_Pos (0UL) |
| |
| #define | USIC_CH_RBCTR_DPTR_Msk (0x3fUL) |
| |
| #define | USIC_CH_RBCTR_LIMIT_Pos (8UL) |
| |
| #define | USIC_CH_RBCTR_LIMIT_Msk (0x3f00UL) |
| |
| #define | USIC_CH_RBCTR_SRBTM_Pos (14UL) |
| |
| #define | USIC_CH_RBCTR_SRBTM_Msk (0x4000UL) |
| |
| #define | USIC_CH_RBCTR_SRBTEN_Pos (15UL) |
| |
| #define | USIC_CH_RBCTR_SRBTEN_Msk (0x8000UL) |
| |
| #define | USIC_CH_RBCTR_SRBINP_Pos (16UL) |
| |
| #define | USIC_CH_RBCTR_SRBINP_Msk (0x70000UL) |
| |
| #define | USIC_CH_RBCTR_ARBINP_Pos (19UL) |
| |
| #define | USIC_CH_RBCTR_ARBINP_Msk (0x380000UL) |
| |
| #define | USIC_CH_RBCTR_RCIM_Pos (22UL) |
| |
| #define | USIC_CH_RBCTR_RCIM_Msk (0xc00000UL) |
| |
| #define | USIC_CH_RBCTR_SIZE_Pos (24UL) |
| |
| #define | USIC_CH_RBCTR_SIZE_Msk (0x7000000UL) |
| |
| #define | USIC_CH_RBCTR_RNM_Pos (27UL) |
| |
| #define | USIC_CH_RBCTR_RNM_Msk (0x8000000UL) |
| |
| #define | USIC_CH_RBCTR_LOF_Pos (28UL) |
| |
| #define | USIC_CH_RBCTR_LOF_Msk (0x10000000UL) |
| |
| #define | USIC_CH_RBCTR_ARBIEN_Pos (29UL) |
| |
| #define | USIC_CH_RBCTR_ARBIEN_Msk (0x20000000UL) |
| |
| #define | USIC_CH_RBCTR_SRBIEN_Pos (30UL) |
| |
| #define | USIC_CH_RBCTR_SRBIEN_Msk (0x40000000UL) |
| |
| #define | USIC_CH_RBCTR_RBERIEN_Pos (31UL) |
| |
| #define | USIC_CH_RBCTR_RBERIEN_Msk (0x80000000UL) |
| |
| #define | USIC_CH_TRBPTR_TDIPTR_Pos (0UL) |
| |
| #define | USIC_CH_TRBPTR_TDIPTR_Msk (0x3fUL) |
| |
| #define | USIC_CH_TRBPTR_TDOPTR_Pos (8UL) |
| |
| #define | USIC_CH_TRBPTR_TDOPTR_Msk (0x3f00UL) |
| |
| #define | USIC_CH_TRBPTR_RDIPTR_Pos (16UL) |
| |
| #define | USIC_CH_TRBPTR_RDIPTR_Msk (0x3f0000UL) |
| |
| #define | USIC_CH_TRBPTR_RDOPTR_Pos (24UL) |
| |
| #define | USIC_CH_TRBPTR_RDOPTR_Msk (0x3f000000UL) |
| |
| #define | USIC_CH_TRBSR_SRBI_Pos (0UL) |
| |
| #define | USIC_CH_TRBSR_SRBI_Msk (0x1UL) |
| |
| #define | USIC_CH_TRBSR_RBERI_Pos (1UL) |
| |
| #define | USIC_CH_TRBSR_RBERI_Msk (0x2UL) |
| |
| #define | USIC_CH_TRBSR_ARBI_Pos (2UL) |
| |
| #define | USIC_CH_TRBSR_ARBI_Msk (0x4UL) |
| |
| #define | USIC_CH_TRBSR_REMPTY_Pos (3UL) |
| |
| #define | USIC_CH_TRBSR_REMPTY_Msk (0x8UL) |
| |
| #define | USIC_CH_TRBSR_RFULL_Pos (4UL) |
| |
| #define | USIC_CH_TRBSR_RFULL_Msk (0x10UL) |
| |
| #define | USIC_CH_TRBSR_RBUS_Pos (5UL) |
| |
| #define | USIC_CH_TRBSR_RBUS_Msk (0x20UL) |
| |
| #define | USIC_CH_TRBSR_SRBT_Pos (6UL) |
| |
| #define | USIC_CH_TRBSR_SRBT_Msk (0x40UL) |
| |
| #define | USIC_CH_TRBSR_STBI_Pos (8UL) |
| |
| #define | USIC_CH_TRBSR_STBI_Msk (0x100UL) |
| |
| #define | USIC_CH_TRBSR_TBERI_Pos (9UL) |
| |
| #define | USIC_CH_TRBSR_TBERI_Msk (0x200UL) |
| |
| #define | USIC_CH_TRBSR_TEMPTY_Pos (11UL) |
| |
| #define | USIC_CH_TRBSR_TEMPTY_Msk (0x800UL) |
| |
| #define | USIC_CH_TRBSR_TFULL_Pos (12UL) |
| |
| #define | USIC_CH_TRBSR_TFULL_Msk (0x1000UL) |
| |
| #define | USIC_CH_TRBSR_TBUS_Pos (13UL) |
| |
| #define | USIC_CH_TRBSR_TBUS_Msk (0x2000UL) |
| |
| #define | USIC_CH_TRBSR_STBT_Pos (14UL) |
| |
| #define | USIC_CH_TRBSR_STBT_Msk (0x4000UL) |
| |
| #define | USIC_CH_TRBSR_RBFLVL_Pos (16UL) |
| |
| #define | USIC_CH_TRBSR_RBFLVL_Msk (0x7f0000UL) |
| |
| #define | USIC_CH_TRBSR_TBFLVL_Pos (24UL) |
| |
| #define | USIC_CH_TRBSR_TBFLVL_Msk (0x7f000000UL) |
| |
| #define | USIC_CH_TRBSCR_CSRBI_Pos (0UL) |
| |
| #define | USIC_CH_TRBSCR_CSRBI_Msk (0x1UL) |
| |
| #define | USIC_CH_TRBSCR_CRBERI_Pos (1UL) |
| |
| #define | USIC_CH_TRBSCR_CRBERI_Msk (0x2UL) |
| |
| #define | USIC_CH_TRBSCR_CARBI_Pos (2UL) |
| |
| #define | USIC_CH_TRBSCR_CARBI_Msk (0x4UL) |
| |
| #define | USIC_CH_TRBSCR_CSTBI_Pos (8UL) |
| |
| #define | USIC_CH_TRBSCR_CSTBI_Msk (0x100UL) |
| |
| #define | USIC_CH_TRBSCR_CTBERI_Pos (9UL) |
| |
| #define | USIC_CH_TRBSCR_CTBERI_Msk (0x200UL) |
| |
| #define | USIC_CH_TRBSCR_CBDV_Pos (10UL) |
| |
| #define | USIC_CH_TRBSCR_CBDV_Msk (0x400UL) |
| |
| #define | USIC_CH_TRBSCR_FLUSHRB_Pos (14UL) |
| |
| #define | USIC_CH_TRBSCR_FLUSHRB_Msk (0x4000UL) |
| |
| #define | USIC_CH_TRBSCR_FLUSHTB_Pos (15UL) |
| |
| #define | USIC_CH_TRBSCR_FLUSHTB_Msk (0x8000UL) |
| |
| #define | USIC_CH_OUTR_DSR_Pos (0UL) |
| |
| #define | USIC_CH_OUTR_DSR_Msk (0xffffUL) |
| |
| #define | USIC_CH_OUTR_RCI_Pos (16UL) |
| |
| #define | USIC_CH_OUTR_RCI_Msk (0x1f0000UL) |
| |
| #define | USIC_CH_OUTDR_DSR_Pos (0UL) |
| |
| #define | USIC_CH_OUTDR_DSR_Msk (0xffffUL) |
| |
| #define | USIC_CH_OUTDR_RCI_Pos (16UL) |
| |
| #define | USIC_CH_OUTDR_RCI_Msk (0x1f0000UL) |
| |
| #define | USIC_CH_IN_TDATA_Pos (0UL) |
| |
| #define | USIC_CH_IN_TDATA_Msk (0xffffUL) |
| |
| #define | CAN_CLC_DISR_Pos (0UL) |
| |
| #define | CAN_CLC_DISR_Msk (0x1UL) |
| |
| #define | CAN_CLC_DISS_Pos (1UL) |
| |
| #define | CAN_CLC_DISS_Msk (0x2UL) |
| |
| #define | CAN_CLC_EDIS_Pos (3UL) |
| |
| #define | CAN_CLC_EDIS_Msk (0x8UL) |
| |
| #define | CAN_ID_MOD_REV_Pos (0UL) |
| |
| #define | CAN_ID_MOD_REV_Msk (0xffUL) |
| |
| #define | CAN_ID_MOD_TYPE_Pos (8UL) |
| |
| #define | CAN_ID_MOD_TYPE_Msk (0xff00UL) |
| |
| #define | CAN_ID_MOD_NUMBER_Pos (16UL) |
| |
| #define | CAN_ID_MOD_NUMBER_Msk (0xffff0000UL) |
| |
| #define | CAN_FDR_STEP_Pos (0UL) |
| |
| #define | CAN_FDR_STEP_Msk (0x3ffUL) |
| |
| #define | CAN_FDR_DM_Pos (14UL) |
| |
| #define | CAN_FDR_DM_Msk (0xc000UL) |
| |
| #define | CAN_LIST_BEGIN_Pos (0UL) |
| |
| #define | CAN_LIST_BEGIN_Msk (0xffUL) |
| |
| #define | CAN_LIST_END_Pos (8UL) |
| |
| #define | CAN_LIST_END_Msk (0xff00UL) |
| |
| #define | CAN_LIST_SIZE_Pos (16UL) |
| |
| #define | CAN_LIST_SIZE_Msk (0xff0000UL) |
| |
| #define | CAN_LIST_EMPTY_Pos (24UL) |
| |
| #define | CAN_LIST_EMPTY_Msk (0x1000000UL) |
| |
| #define | CAN_MSPND_PND_Pos (0UL) |
| |
| #define | CAN_MSPND_PND_Msk (0xffffffffUL) |
| |
| #define | CAN_MSID_INDEX_Pos (0UL) |
| |
| #define | CAN_MSID_INDEX_Msk (0x3fUL) |
| |
| #define | CAN_MSIMASK_IM_Pos (0UL) |
| |
| #define | CAN_MSIMASK_IM_Msk (0xffffffffUL) |
| |
| #define | CAN_PANCTR_PANCMD_Pos (0UL) |
| |
| #define | CAN_PANCTR_PANCMD_Msk (0xffUL) |
| |
| #define | CAN_PANCTR_BUSY_Pos (8UL) |
| |
| #define | CAN_PANCTR_BUSY_Msk (0x100UL) |
| |
| #define | CAN_PANCTR_RBUSY_Pos (9UL) |
| |
| #define | CAN_PANCTR_RBUSY_Msk (0x200UL) |
| |
| #define | CAN_PANCTR_PANAR1_Pos (16UL) |
| |
| #define | CAN_PANCTR_PANAR1_Msk (0xff0000UL) |
| |
| #define | CAN_PANCTR_PANAR2_Pos (24UL) |
| |
| #define | CAN_PANCTR_PANAR2_Msk (0xff000000UL) |
| |
| #define | CAN_MCR_CLKSEL_Pos (0UL) |
| |
| #define | CAN_MCR_CLKSEL_Msk (0xfUL) |
| |
| #define | CAN_MCR_MPSEL_Pos (12UL) |
| |
| #define | CAN_MCR_MPSEL_Msk (0xf000UL) |
| |
| #define | CAN_MITR_IT_Pos (0UL) |
| |
| #define | CAN_MITR_IT_Msk (0xffUL) |
| |
| #define | CAN_NODE_NCR_INIT_Pos (0UL) |
| |
| #define | CAN_NODE_NCR_INIT_Msk (0x1UL) |
| |
| #define | CAN_NODE_NCR_TRIE_Pos (1UL) |
| |
| #define | CAN_NODE_NCR_TRIE_Msk (0x2UL) |
| |
| #define | CAN_NODE_NCR_LECIE_Pos (2UL) |
| |
| #define | CAN_NODE_NCR_LECIE_Msk (0x4UL) |
| |
| #define | CAN_NODE_NCR_ALIE_Pos (3UL) |
| |
| #define | CAN_NODE_NCR_ALIE_Msk (0x8UL) |
| |
| #define | CAN_NODE_NCR_CANDIS_Pos (4UL) |
| |
| #define | CAN_NODE_NCR_CANDIS_Msk (0x10UL) |
| |
| #define | CAN_NODE_NCR_TXDIS_Pos (5UL) |
| |
| #define | CAN_NODE_NCR_TXDIS_Msk (0x20UL) |
| |
| #define | CAN_NODE_NCR_CCE_Pos (6UL) |
| |
| #define | CAN_NODE_NCR_CCE_Msk (0x40UL) |
| |
| #define | CAN_NODE_NCR_CALM_Pos (7UL) |
| |
| #define | CAN_NODE_NCR_CALM_Msk (0x80UL) |
| |
| #define | CAN_NODE_NSR_LEC_Pos (0UL) |
| |
| #define | CAN_NODE_NSR_LEC_Msk (0x7UL) |
| |
| #define | CAN_NODE_NSR_TXOK_Pos (3UL) |
| |
| #define | CAN_NODE_NSR_TXOK_Msk (0x8UL) |
| |
| #define | CAN_NODE_NSR_RXOK_Pos (4UL) |
| |
| #define | CAN_NODE_NSR_RXOK_Msk (0x10UL) |
| |
| #define | CAN_NODE_NSR_ALERT_Pos (5UL) |
| |
| #define | CAN_NODE_NSR_ALERT_Msk (0x20UL) |
| |
| #define | CAN_NODE_NSR_EWRN_Pos (6UL) |
| |
| #define | CAN_NODE_NSR_EWRN_Msk (0x40UL) |
| |
| #define | CAN_NODE_NSR_BOFF_Pos (7UL) |
| |
| #define | CAN_NODE_NSR_BOFF_Msk (0x80UL) |
| |
| #define | CAN_NODE_NSR_LLE_Pos (8UL) |
| |
| #define | CAN_NODE_NSR_LLE_Msk (0x100UL) |
| |
| #define | CAN_NODE_NSR_LOE_Pos (9UL) |
| |
| #define | CAN_NODE_NSR_LOE_Msk (0x200UL) |
| |
| #define | CAN_NODE_NIPR_ALINP_Pos (0UL) |
| |
| #define | CAN_NODE_NIPR_ALINP_Msk (0xfUL) |
| |
| #define | CAN_NODE_NIPR_LECINP_Pos (4UL) |
| |
| #define | CAN_NODE_NIPR_LECINP_Msk (0xf0UL) |
| |
| #define | CAN_NODE_NIPR_TRINP_Pos (8UL) |
| |
| #define | CAN_NODE_NIPR_TRINP_Msk (0xf00UL) |
| |
| #define | CAN_NODE_NIPR_CFCINP_Pos (12UL) |
| |
| #define | CAN_NODE_NIPR_CFCINP_Msk (0xf000UL) |
| |
| #define | CAN_NODE_NPCR_RXSEL_Pos (0UL) |
| |
| #define | CAN_NODE_NPCR_RXSEL_Msk (0x7UL) |
| |
| #define | CAN_NODE_NPCR_LBM_Pos (8UL) |
| |
| #define | CAN_NODE_NPCR_LBM_Msk (0x100UL) |
| |
| #define | CAN_NODE_NBTR_BRP_Pos (0UL) |
| |
| #define | CAN_NODE_NBTR_BRP_Msk (0x3fUL) |
| |
| #define | CAN_NODE_NBTR_SJW_Pos (6UL) |
| |
| #define | CAN_NODE_NBTR_SJW_Msk (0xc0UL) |
| |
| #define | CAN_NODE_NBTR_TSEG1_Pos (8UL) |
| |
| #define | CAN_NODE_NBTR_TSEG1_Msk (0xf00UL) |
| |
| #define | CAN_NODE_NBTR_TSEG2_Pos (12UL) |
| |
| #define | CAN_NODE_NBTR_TSEG2_Msk (0x7000UL) |
| |
| #define | CAN_NODE_NBTR_DIV8_Pos (15UL) |
| |
| #define | CAN_NODE_NBTR_DIV8_Msk (0x8000UL) |
| |
| #define | CAN_NODE_NECNT_REC_Pos (0UL) |
| |
| #define | CAN_NODE_NECNT_REC_Msk (0xffUL) |
| |
| #define | CAN_NODE_NECNT_TEC_Pos (8UL) |
| |
| #define | CAN_NODE_NECNT_TEC_Msk (0xff00UL) |
| |
| #define | CAN_NODE_NECNT_EWRNLVL_Pos (16UL) |
| |
| #define | CAN_NODE_NECNT_EWRNLVL_Msk (0xff0000UL) |
| |
| #define | CAN_NODE_NECNT_LETD_Pos (24UL) |
| |
| #define | CAN_NODE_NECNT_LETD_Msk (0x1000000UL) |
| |
| #define | CAN_NODE_NECNT_LEINC_Pos (25UL) |
| |
| #define | CAN_NODE_NECNT_LEINC_Msk (0x2000000UL) |
| |
| #define | CAN_NODE_NFCR_CFC_Pos (0UL) |
| |
| #define | CAN_NODE_NFCR_CFC_Msk (0xffffUL) |
| |
| #define | CAN_NODE_NFCR_CFSEL_Pos (16UL) |
| |
| #define | CAN_NODE_NFCR_CFSEL_Msk (0x70000UL) |
| |
| #define | CAN_NODE_NFCR_CFMOD_Pos (19UL) |
| |
| #define | CAN_NODE_NFCR_CFMOD_Msk (0x180000UL) |
| |
| #define | CAN_NODE_NFCR_CFCIE_Pos (22UL) |
| |
| #define | CAN_NODE_NFCR_CFCIE_Msk (0x400000UL) |
| |
| #define | CAN_NODE_NFCR_CFCOV_Pos (23UL) |
| |
| #define | CAN_NODE_NFCR_CFCOV_Msk (0x800000UL) |
| |
| #define | CAN_MO_MOFCR_MMC_Pos (0UL) |
| |
| #define | CAN_MO_MOFCR_MMC_Msk (0xfUL) |
| |
| #define | CAN_MO_MOFCR_RXTOE_Pos (4UL) |
| |
| #define | CAN_MO_MOFCR_RXTOE_Msk (0x10UL) |
| |
| #define | CAN_MO_MOFCR_GDFS_Pos (8UL) |
| |
| #define | CAN_MO_MOFCR_GDFS_Msk (0x100UL) |
| |
| #define | CAN_MO_MOFCR_IDC_Pos (9UL) |
| |
| #define | CAN_MO_MOFCR_IDC_Msk (0x200UL) |
| |
| #define | CAN_MO_MOFCR_DLCC_Pos (10UL) |
| |
| #define | CAN_MO_MOFCR_DLCC_Msk (0x400UL) |
| |
| #define | CAN_MO_MOFCR_DATC_Pos (11UL) |
| |
| #define | CAN_MO_MOFCR_DATC_Msk (0x800UL) |
| |
| #define | CAN_MO_MOFCR_RXIE_Pos (16UL) |
| |
| #define | CAN_MO_MOFCR_RXIE_Msk (0x10000UL) |
| |
| #define | CAN_MO_MOFCR_TXIE_Pos (17UL) |
| |
| #define | CAN_MO_MOFCR_TXIE_Msk (0x20000UL) |
| |
| #define | CAN_MO_MOFCR_OVIE_Pos (18UL) |
| |
| #define | CAN_MO_MOFCR_OVIE_Msk (0x40000UL) |
| |
| #define | CAN_MO_MOFCR_FRREN_Pos (20UL) |
| |
| #define | CAN_MO_MOFCR_FRREN_Msk (0x100000UL) |
| |
| #define | CAN_MO_MOFCR_RMM_Pos (21UL) |
| |
| #define | CAN_MO_MOFCR_RMM_Msk (0x200000UL) |
| |
| #define | CAN_MO_MOFCR_SDT_Pos (22UL) |
| |
| #define | CAN_MO_MOFCR_SDT_Msk (0x400000UL) |
| |
| #define | CAN_MO_MOFCR_STT_Pos (23UL) |
| |
| #define | CAN_MO_MOFCR_STT_Msk (0x800000UL) |
| |
| #define | CAN_MO_MOFCR_DLC_Pos (24UL) |
| |
| #define | CAN_MO_MOFCR_DLC_Msk (0xf000000UL) |
| |
| #define | CAN_MO_MOFGPR_BOT_Pos (0UL) |
| |
| #define | CAN_MO_MOFGPR_BOT_Msk (0xffUL) |
| |
| #define | CAN_MO_MOFGPR_TOP_Pos (8UL) |
| |
| #define | CAN_MO_MOFGPR_TOP_Msk (0xff00UL) |
| |
| #define | CAN_MO_MOFGPR_CUR_Pos (16UL) |
| |
| #define | CAN_MO_MOFGPR_CUR_Msk (0xff0000UL) |
| |
| #define | CAN_MO_MOFGPR_SEL_Pos (24UL) |
| |
| #define | CAN_MO_MOFGPR_SEL_Msk (0xff000000UL) |
| |
| #define | CAN_MO_MOIPR_RXINP_Pos (0UL) |
| |
| #define | CAN_MO_MOIPR_RXINP_Msk (0xfUL) |
| |
| #define | CAN_MO_MOIPR_TXINP_Pos (4UL) |
| |
| #define | CAN_MO_MOIPR_TXINP_Msk (0xf0UL) |
| |
| #define | CAN_MO_MOIPR_MPN_Pos (8UL) |
| |
| #define | CAN_MO_MOIPR_MPN_Msk (0xff00UL) |
| |
| #define | CAN_MO_MOIPR_CFCVAL_Pos (16UL) |
| |
| #define | CAN_MO_MOIPR_CFCVAL_Msk (0xffff0000UL) |
| |
| #define | CAN_MO_MOAMR_AM_Pos (0UL) |
| |
| #define | CAN_MO_MOAMR_AM_Msk (0x1fffffffUL) |
| |
| #define | CAN_MO_MOAMR_MIDE_Pos (29UL) |
| |
| #define | CAN_MO_MOAMR_MIDE_Msk (0x20000000UL) |
| |
| #define | CAN_MO_MODATAL_DB0_Pos (0UL) |
| |
| #define | CAN_MO_MODATAL_DB0_Msk (0xffUL) |
| |
| #define | CAN_MO_MODATAL_DB1_Pos (8UL) |
| |
| #define | CAN_MO_MODATAL_DB1_Msk (0xff00UL) |
| |
| #define | CAN_MO_MODATAL_DB2_Pos (16UL) |
| |
| #define | CAN_MO_MODATAL_DB2_Msk (0xff0000UL) |
| |
| #define | CAN_MO_MODATAL_DB3_Pos (24UL) |
| |
| #define | CAN_MO_MODATAL_DB3_Msk (0xff000000UL) |
| |
| #define | CAN_MO_MODATAH_DB4_Pos (0UL) |
| |
| #define | CAN_MO_MODATAH_DB4_Msk (0xffUL) |
| |
| #define | CAN_MO_MODATAH_DB5_Pos (8UL) |
| |
| #define | CAN_MO_MODATAH_DB5_Msk (0xff00UL) |
| |
| #define | CAN_MO_MODATAH_DB6_Pos (16UL) |
| |
| #define | CAN_MO_MODATAH_DB6_Msk (0xff0000UL) |
| |
| #define | CAN_MO_MODATAH_DB7_Pos (24UL) |
| |
| #define | CAN_MO_MODATAH_DB7_Msk (0xff000000UL) |
| |
| #define | CAN_MO_MOAR_ID_Pos (0UL) |
| |
| #define | CAN_MO_MOAR_ID_Msk (0x1fffffffUL) |
| |
| #define | CAN_MO_MOAR_IDE_Pos (29UL) |
| |
| #define | CAN_MO_MOAR_IDE_Msk (0x20000000UL) |
| |
| #define | CAN_MO_MOAR_PRI_Pos (30UL) |
| |
| #define | CAN_MO_MOAR_PRI_Msk (0xc0000000UL) |
| |
| #define | CAN_MO_MOCTR_RESRXPND_Pos (0UL) |
| |
| #define | CAN_MO_MOCTR_RESRXPND_Msk (0x1UL) |
| |
| #define | CAN_MO_MOCTR_RESTXPND_Pos (1UL) |
| |
| #define | CAN_MO_MOCTR_RESTXPND_Msk (0x2UL) |
| |
| #define | CAN_MO_MOCTR_RESRXUPD_Pos (2UL) |
| |
| #define | CAN_MO_MOCTR_RESRXUPD_Msk (0x4UL) |
| |
| #define | CAN_MO_MOCTR_RESNEWDAT_Pos (3UL) |
| |
| #define | CAN_MO_MOCTR_RESNEWDAT_Msk (0x8UL) |
| |
| #define | CAN_MO_MOCTR_RESMSGLST_Pos (4UL) |
| |
| #define | CAN_MO_MOCTR_RESMSGLST_Msk (0x10UL) |
| |
| #define | CAN_MO_MOCTR_RESMSGVAL_Pos (5UL) |
| |
| #define | CAN_MO_MOCTR_RESMSGVAL_Msk (0x20UL) |
| |
| #define | CAN_MO_MOCTR_RESRTSEL_Pos (6UL) |
| |
| #define | CAN_MO_MOCTR_RESRTSEL_Msk (0x40UL) |
| |
| #define | CAN_MO_MOCTR_RESRXEN_Pos (7UL) |
| |
| #define | CAN_MO_MOCTR_RESRXEN_Msk (0x80UL) |
| |
| #define | CAN_MO_MOCTR_RESTXRQ_Pos (8UL) |
| |
| #define | CAN_MO_MOCTR_RESTXRQ_Msk (0x100UL) |
| |
| #define | CAN_MO_MOCTR_RESTXEN0_Pos (9UL) |
| |
| #define | CAN_MO_MOCTR_RESTXEN0_Msk (0x200UL) |
| |
| #define | CAN_MO_MOCTR_RESTXEN1_Pos (10UL) |
| |
| #define | CAN_MO_MOCTR_RESTXEN1_Msk (0x400UL) |
| |
| #define | CAN_MO_MOCTR_RESDIR_Pos (11UL) |
| |
| #define | CAN_MO_MOCTR_RESDIR_Msk (0x800UL) |
| |
| #define | CAN_MO_MOCTR_SETRXPND_Pos (16UL) |
| |
| #define | CAN_MO_MOCTR_SETRXPND_Msk (0x10000UL) |
| |
| #define | CAN_MO_MOCTR_SETTXPND_Pos (17UL) |
| |
| #define | CAN_MO_MOCTR_SETTXPND_Msk (0x20000UL) |
| |
| #define | CAN_MO_MOCTR_SETRXUPD_Pos (18UL) |
| |
| #define | CAN_MO_MOCTR_SETRXUPD_Msk (0x40000UL) |
| |
| #define | CAN_MO_MOCTR_SETNEWDAT_Pos (19UL) |
| |
| #define | CAN_MO_MOCTR_SETNEWDAT_Msk (0x80000UL) |
| |
| #define | CAN_MO_MOCTR_SETMSGLST_Pos (20UL) |
| |
| #define | CAN_MO_MOCTR_SETMSGLST_Msk (0x100000UL) |
| |
| #define | CAN_MO_MOCTR_SETMSGVAL_Pos (21UL) |
| |
| #define | CAN_MO_MOCTR_SETMSGVAL_Msk (0x200000UL) |
| |
| #define | CAN_MO_MOCTR_SETRTSEL_Pos (22UL) |
| |
| #define | CAN_MO_MOCTR_SETRTSEL_Msk (0x400000UL) |
| |
| #define | CAN_MO_MOCTR_SETRXEN_Pos (23UL) |
| |
| #define | CAN_MO_MOCTR_SETRXEN_Msk (0x800000UL) |
| |
| #define | CAN_MO_MOCTR_SETTXRQ_Pos (24UL) |
| |
| #define | CAN_MO_MOCTR_SETTXRQ_Msk (0x1000000UL) |
| |
| #define | CAN_MO_MOCTR_SETTXEN0_Pos (25UL) |
| |
| #define | CAN_MO_MOCTR_SETTXEN0_Msk (0x2000000UL) |
| |
| #define | CAN_MO_MOCTR_SETTXEN1_Pos (26UL) |
| |
| #define | CAN_MO_MOCTR_SETTXEN1_Msk (0x4000000UL) |
| |
| #define | CAN_MO_MOCTR_SETDIR_Pos (27UL) |
| |
| #define | CAN_MO_MOCTR_SETDIR_Msk (0x8000000UL) |
| |
| #define | CAN_MO_MOSTAT_RXPND_Pos (0UL) |
| |
| #define | CAN_MO_MOSTAT_RXPND_Msk (0x1UL) |
| |
| #define | CAN_MO_MOSTAT_TXPND_Pos (1UL) |
| |
| #define | CAN_MO_MOSTAT_TXPND_Msk (0x2UL) |
| |
| #define | CAN_MO_MOSTAT_RXUPD_Pos (2UL) |
| |
| #define | CAN_MO_MOSTAT_RXUPD_Msk (0x4UL) |
| |
| #define | CAN_MO_MOSTAT_NEWDAT_Pos (3UL) |
| |
| #define | CAN_MO_MOSTAT_NEWDAT_Msk (0x8UL) |
| |
| #define | CAN_MO_MOSTAT_MSGLST_Pos (4UL) |
| |
| #define | CAN_MO_MOSTAT_MSGLST_Msk (0x10UL) |
| |
| #define | CAN_MO_MOSTAT_MSGVAL_Pos (5UL) |
| |
| #define | CAN_MO_MOSTAT_MSGVAL_Msk (0x20UL) |
| |
| #define | CAN_MO_MOSTAT_RTSEL_Pos (6UL) |
| |
| #define | CAN_MO_MOSTAT_RTSEL_Msk (0x40UL) |
| |
| #define | CAN_MO_MOSTAT_RXEN_Pos (7UL) |
| |
| #define | CAN_MO_MOSTAT_RXEN_Msk (0x80UL) |
| |
| #define | CAN_MO_MOSTAT_TXRQ_Pos (8UL) |
| |
| #define | CAN_MO_MOSTAT_TXRQ_Msk (0x100UL) |
| |
| #define | CAN_MO_MOSTAT_TXEN0_Pos (9UL) |
| |
| #define | CAN_MO_MOSTAT_TXEN0_Msk (0x200UL) |
| |
| #define | CAN_MO_MOSTAT_TXEN1_Pos (10UL) |
| |
| #define | CAN_MO_MOSTAT_TXEN1_Msk (0x400UL) |
| |
| #define | CAN_MO_MOSTAT_DIR_Pos (11UL) |
| |
| #define | CAN_MO_MOSTAT_DIR_Msk (0x800UL) |
| |
| #define | CAN_MO_MOSTAT_LIST_Pos (12UL) |
| |
| #define | CAN_MO_MOSTAT_LIST_Msk (0xf000UL) |
| |
| #define | CAN_MO_MOSTAT_PPREV_Pos (16UL) |
| |
| #define | CAN_MO_MOSTAT_PPREV_Msk (0xff0000UL) |
| |
| #define | CAN_MO_MOSTAT_PNEXT_Pos (24UL) |
| |
| #define | CAN_MO_MOSTAT_PNEXT_Msk (0xff000000UL) |
| |
| #define | VADC_CLC_DISR_Pos (0UL) |
| |
| #define | VADC_CLC_DISR_Msk (0x1UL) |
| |
| #define | VADC_CLC_DISS_Pos (1UL) |
| |
| #define | VADC_CLC_DISS_Msk (0x2UL) |
| |
| #define | VADC_CLC_EDIS_Pos (3UL) |
| |
| #define | VADC_CLC_EDIS_Msk (0x8UL) |
| |
| #define | VADC_ID_MOD_REV_Pos (0UL) |
| |
| #define | VADC_ID_MOD_REV_Msk (0xffUL) |
| |
| #define | VADC_ID_MOD_TYPE_Pos (8UL) |
| |
| #define | VADC_ID_MOD_TYPE_Msk (0xff00UL) |
| |
| #define | VADC_ID_MOD_NUMBER_Pos (16UL) |
| |
| #define | VADC_ID_MOD_NUMBER_Msk (0xffff0000UL) |
| |
| #define | VADC_OCS_TGS_Pos (0UL) |
| |
| #define | VADC_OCS_TGS_Msk (0x3UL) |
| |
| #define | VADC_OCS_TGB_Pos (2UL) |
| |
| #define | VADC_OCS_TGB_Msk (0x4UL) |
| |
| #define | VADC_OCS_TG_P_Pos (3UL) |
| |
| #define | VADC_OCS_TG_P_Msk (0x8UL) |
| |
| #define | VADC_OCS_SUS_Pos (24UL) |
| |
| #define | VADC_OCS_SUS_Msk (0xf000000UL) |
| |
| #define | VADC_OCS_SUS_P_Pos (28UL) |
| |
| #define | VADC_OCS_SUS_P_Msk (0x10000000UL) |
| |
| #define | VADC_OCS_SUSSTA_Pos (29UL) |
| |
| #define | VADC_OCS_SUSSTA_Msk (0x20000000UL) |
| |
| #define | VADC_GLOBCFG_DIVA_Pos (0UL) |
| |
| #define | VADC_GLOBCFG_DIVA_Msk (0x1fUL) |
| |
| #define | VADC_GLOBCFG_DCMSB_Pos (7UL) |
| |
| #define | VADC_GLOBCFG_DCMSB_Msk (0x80UL) |
| |
| #define | VADC_GLOBCFG_DIVD_Pos (8UL) |
| |
| #define | VADC_GLOBCFG_DIVD_Msk (0x300UL) |
| |
| #define | VADC_GLOBCFG_DIVWC_Pos (15UL) |
| |
| #define | VADC_GLOBCFG_DIVWC_Msk (0x8000UL) |
| |
| #define | VADC_GLOBCFG_DPCAL0_Pos (16UL) |
| |
| #define | VADC_GLOBCFG_DPCAL0_Msk (0x10000UL) |
| |
| #define | VADC_GLOBCFG_DPCAL1_Pos (17UL) |
| |
| #define | VADC_GLOBCFG_DPCAL1_Msk (0x20000UL) |
| |
| #define | VADC_GLOBCFG_DPCAL2_Pos (18UL) |
| |
| #define | VADC_GLOBCFG_DPCAL2_Msk (0x40000UL) |
| |
| #define | VADC_GLOBCFG_DPCAL3_Pos (19UL) |
| |
| #define | VADC_GLOBCFG_DPCAL3_Msk (0x80000UL) |
| |
| #define | VADC_GLOBCFG_SUCAL_Pos (31UL) |
| |
| #define | VADC_GLOBCFG_SUCAL_Msk (0x80000000UL) |
| |
| #define | VADC_GLOBICLASS_STCS_Pos (0UL) |
| |
| #define | VADC_GLOBICLASS_STCS_Msk (0x1fUL) |
| |
| #define | VADC_GLOBICLASS_CMS_Pos (8UL) |
| |
| #define | VADC_GLOBICLASS_CMS_Msk (0x700UL) |
| |
| #define | VADC_GLOBICLASS_STCE_Pos (16UL) |
| |
| #define | VADC_GLOBICLASS_STCE_Msk (0x1f0000UL) |
| |
| #define | VADC_GLOBICLASS_CME_Pos (24UL) |
| |
| #define | VADC_GLOBICLASS_CME_Msk (0x7000000UL) |
| |
| #define | VADC_GLOBBOUND_BOUNDARY0_Pos (0UL) |
| |
| #define | VADC_GLOBBOUND_BOUNDARY0_Msk (0xfffUL) |
| |
| #define | VADC_GLOBBOUND_BOUNDARY1_Pos (16UL) |
| |
| #define | VADC_GLOBBOUND_BOUNDARY1_Msk (0xfff0000UL) |
| |
| #define | VADC_GLOBEFLAG_SEVGLB_Pos (0UL) |
| |
| #define | VADC_GLOBEFLAG_SEVGLB_Msk (0x1UL) |
| |
| #define | VADC_GLOBEFLAG_REVGLB_Pos (8UL) |
| |
| #define | VADC_GLOBEFLAG_REVGLB_Msk (0x100UL) |
| |
| #define | VADC_GLOBEFLAG_SEVGLBCLR_Pos (16UL) |
| |
| #define | VADC_GLOBEFLAG_SEVGLBCLR_Msk (0x10000UL) |
| |
| #define | VADC_GLOBEFLAG_REVGLBCLR_Pos (24UL) |
| |
| #define | VADC_GLOBEFLAG_REVGLBCLR_Msk (0x1000000UL) |
| |
| #define | VADC_GLOBEVNP_SEV0NP_Pos (0UL) |
| |
| #define | VADC_GLOBEVNP_SEV0NP_Msk (0xfUL) |
| |
| #define | VADC_GLOBEVNP_REV0NP_Pos (16UL) |
| |
| #define | VADC_GLOBEVNP_REV0NP_Msk (0xf0000UL) |
| |
| #define | VADC_GLOBTF_CDGR_Pos (4UL) |
| |
| #define | VADC_GLOBTF_CDGR_Msk (0xf0UL) |
| |
| #define | VADC_GLOBTF_CDEN_Pos (8UL) |
| |
| #define | VADC_GLOBTF_CDEN_Msk (0x100UL) |
| |
| #define | VADC_GLOBTF_CDSEL_Pos (9UL) |
| |
| #define | VADC_GLOBTF_CDSEL_Msk (0x600UL) |
| |
| #define | VADC_GLOBTF_CDWC_Pos (15UL) |
| |
| #define | VADC_GLOBTF_CDWC_Msk (0x8000UL) |
| |
| #define | VADC_GLOBTF_PDD_Pos (16UL) |
| |
| #define | VADC_GLOBTF_PDD_Msk (0x10000UL) |
| |
| #define | VADC_GLOBTF_MDWC_Pos (23UL) |
| |
| #define | VADC_GLOBTF_MDWC_Msk (0x800000UL) |
| |
| #define | VADC_BRSSEL_CHSELG0_Pos (0UL) |
| |
| #define | VADC_BRSSEL_CHSELG0_Msk (0x1UL) |
| |
| #define | VADC_BRSSEL_CHSELG1_Pos (1UL) |
| |
| #define | VADC_BRSSEL_CHSELG1_Msk (0x2UL) |
| |
| #define | VADC_BRSSEL_CHSELG2_Pos (2UL) |
| |
| #define | VADC_BRSSEL_CHSELG2_Msk (0x4UL) |
| |
| #define | VADC_BRSSEL_CHSELG3_Pos (3UL) |
| |
| #define | VADC_BRSSEL_CHSELG3_Msk (0x8UL) |
| |
| #define | VADC_BRSSEL_CHSELG4_Pos (4UL) |
| |
| #define | VADC_BRSSEL_CHSELG4_Msk (0x10UL) |
| |
| #define | VADC_BRSSEL_CHSELG5_Pos (5UL) |
| |
| #define | VADC_BRSSEL_CHSELG5_Msk (0x20UL) |
| |
| #define | VADC_BRSSEL_CHSELG6_Pos (6UL) |
| |
| #define | VADC_BRSSEL_CHSELG6_Msk (0x40UL) |
| |
| #define | VADC_BRSSEL_CHSELG7_Pos (7UL) |
| |
| #define | VADC_BRSSEL_CHSELG7_Msk (0x80UL) |
| |
| #define | VADC_BRSPND_CHPNDG0_Pos (0UL) |
| |
| #define | VADC_BRSPND_CHPNDG0_Msk (0x1UL) |
| |
| #define | VADC_BRSPND_CHPNDG1_Pos (1UL) |
| |
| #define | VADC_BRSPND_CHPNDG1_Msk (0x2UL) |
| |
| #define | VADC_BRSPND_CHPNDG2_Pos (2UL) |
| |
| #define | VADC_BRSPND_CHPNDG2_Msk (0x4UL) |
| |
| #define | VADC_BRSPND_CHPNDG3_Pos (3UL) |
| |
| #define | VADC_BRSPND_CHPNDG3_Msk (0x8UL) |
| |
| #define | VADC_BRSPND_CHPNDG4_Pos (4UL) |
| |
| #define | VADC_BRSPND_CHPNDG4_Msk (0x10UL) |
| |
| #define | VADC_BRSPND_CHPNDG5_Pos (5UL) |
| |
| #define | VADC_BRSPND_CHPNDG5_Msk (0x20UL) |
| |
| #define | VADC_BRSPND_CHPNDG6_Pos (6UL) |
| |
| #define | VADC_BRSPND_CHPNDG6_Msk (0x40UL) |
| |
| #define | VADC_BRSPND_CHPNDG7_Pos (7UL) |
| |
| #define | VADC_BRSPND_CHPNDG7_Msk (0x80UL) |
| |
| #define | VADC_BRSCTRL_SRCRESREG_Pos (0UL) |
| |
| #define | VADC_BRSCTRL_SRCRESREG_Msk (0xfUL) |
| |
| #define | VADC_BRSCTRL_XTSEL_Pos (8UL) |
| |
| #define | VADC_BRSCTRL_XTSEL_Msk (0xf00UL) |
| |
| #define | VADC_BRSCTRL_XTLVL_Pos (12UL) |
| |
| #define | VADC_BRSCTRL_XTLVL_Msk (0x1000UL) |
| |
| #define | VADC_BRSCTRL_XTMODE_Pos (13UL) |
| |
| #define | VADC_BRSCTRL_XTMODE_Msk (0x6000UL) |
| |
| #define | VADC_BRSCTRL_XTWC_Pos (15UL) |
| |
| #define | VADC_BRSCTRL_XTWC_Msk (0x8000UL) |
| |
| #define | VADC_BRSCTRL_GTSEL_Pos (16UL) |
| |
| #define | VADC_BRSCTRL_GTSEL_Msk (0xf0000UL) |
| |
| #define | VADC_BRSCTRL_GTLVL_Pos (20UL) |
| |
| #define | VADC_BRSCTRL_GTLVL_Msk (0x100000UL) |
| |
| #define | VADC_BRSCTRL_GTWC_Pos (23UL) |
| |
| #define | VADC_BRSCTRL_GTWC_Msk (0x800000UL) |
| |
| #define | VADC_BRSMR_ENGT_Pos (0UL) |
| |
| #define | VADC_BRSMR_ENGT_Msk (0x3UL) |
| |
| #define | VADC_BRSMR_ENTR_Pos (2UL) |
| |
| #define | VADC_BRSMR_ENTR_Msk (0x4UL) |
| |
| #define | VADC_BRSMR_ENSI_Pos (3UL) |
| |
| #define | VADC_BRSMR_ENSI_Msk (0x8UL) |
| |
| #define | VADC_BRSMR_SCAN_Pos (4UL) |
| |
| #define | VADC_BRSMR_SCAN_Msk (0x10UL) |
| |
| #define | VADC_BRSMR_LDM_Pos (5UL) |
| |
| #define | VADC_BRSMR_LDM_Msk (0x20UL) |
| |
| #define | VADC_BRSMR_REQGT_Pos (7UL) |
| |
| #define | VADC_BRSMR_REQGT_Msk (0x80UL) |
| |
| #define | VADC_BRSMR_CLRPND_Pos (8UL) |
| |
| #define | VADC_BRSMR_CLRPND_Msk (0x100UL) |
| |
| #define | VADC_BRSMR_LDEV_Pos (9UL) |
| |
| #define | VADC_BRSMR_LDEV_Msk (0x200UL) |
| |
| #define | VADC_BRSMR_RPTDIS_Pos (16UL) |
| |
| #define | VADC_BRSMR_RPTDIS_Msk (0x10000UL) |
| |
| #define | VADC_GLOBRCR_DRCTR_Pos (16UL) |
| |
| #define | VADC_GLOBRCR_DRCTR_Msk (0xf0000UL) |
| |
| #define | VADC_GLOBRCR_WFR_Pos (24UL) |
| |
| #define | VADC_GLOBRCR_WFR_Msk (0x1000000UL) |
| |
| #define | VADC_GLOBRCR_SRGEN_Pos (31UL) |
| |
| #define | VADC_GLOBRCR_SRGEN_Msk (0x80000000UL) |
| |
| #define | VADC_GLOBRES_RESULT_Pos (0UL) |
| |
| #define | VADC_GLOBRES_RESULT_Msk (0xffffUL) |
| |
| #define | VADC_GLOBRES_GNR_Pos (16UL) |
| |
| #define | VADC_GLOBRES_GNR_Msk (0xf0000UL) |
| |
| #define | VADC_GLOBRES_CHNR_Pos (20UL) |
| |
| #define | VADC_GLOBRES_CHNR_Msk (0x1f00000UL) |
| |
| #define | VADC_GLOBRES_EMUX_Pos (25UL) |
| |
| #define | VADC_GLOBRES_EMUX_Msk (0xe000000UL) |
| |
| #define | VADC_GLOBRES_CRS_Pos (28UL) |
| |
| #define | VADC_GLOBRES_CRS_Msk (0x30000000UL) |
| |
| #define | VADC_GLOBRES_FCR_Pos (30UL) |
| |
| #define | VADC_GLOBRES_FCR_Msk (0x40000000UL) |
| |
| #define | VADC_GLOBRES_VF_Pos (31UL) |
| |
| #define | VADC_GLOBRES_VF_Msk (0x80000000UL) |
| |
| #define | VADC_GLOBRESD_RESULT_Pos (0UL) |
| |
| #define | VADC_GLOBRESD_RESULT_Msk (0xffffUL) |
| |
| #define | VADC_GLOBRESD_GNR_Pos (16UL) |
| |
| #define | VADC_GLOBRESD_GNR_Msk (0xf0000UL) |
| |
| #define | VADC_GLOBRESD_CHNR_Pos (20UL) |
| |
| #define | VADC_GLOBRESD_CHNR_Msk (0x1f00000UL) |
| |
| #define | VADC_GLOBRESD_EMUX_Pos (25UL) |
| |
| #define | VADC_GLOBRESD_EMUX_Msk (0xe000000UL) |
| |
| #define | VADC_GLOBRESD_CRS_Pos (28UL) |
| |
| #define | VADC_GLOBRESD_CRS_Msk (0x30000000UL) |
| |
| #define | VADC_GLOBRESD_FCR_Pos (30UL) |
| |
| #define | VADC_GLOBRESD_FCR_Msk (0x40000000UL) |
| |
| #define | VADC_GLOBRESD_VF_Pos (31UL) |
| |
| #define | VADC_GLOBRESD_VF_Msk (0x80000000UL) |
| |
| #define | VADC_EMUXSEL_EMUXGRP0_Pos (0UL) |
| |
| #define | VADC_EMUXSEL_EMUXGRP0_Msk (0xfUL) |
| |
| #define | VADC_EMUXSEL_EMUXGRP1_Pos (4UL) |
| |
| #define | VADC_EMUXSEL_EMUXGRP1_Msk (0xf0UL) |
| |
| #define | VADC_G_ARBCFG_ANONC_Pos (0UL) |
| |
| #define | VADC_G_ARBCFG_ANONC_Msk (0x3UL) |
| |
| #define | VADC_G_ARBCFG_ARBRND_Pos (4UL) |
| |
| #define | VADC_G_ARBCFG_ARBRND_Msk (0x30UL) |
| |
| #define | VADC_G_ARBCFG_ARBM_Pos (7UL) |
| |
| #define | VADC_G_ARBCFG_ARBM_Msk (0x80UL) |
| |
| #define | VADC_G_ARBCFG_ANONS_Pos (16UL) |
| |
| #define | VADC_G_ARBCFG_ANONS_Msk (0x30000UL) |
| |
| #define | VADC_G_ARBCFG_CAL_Pos (28UL) |
| |
| #define | VADC_G_ARBCFG_CAL_Msk (0x10000000UL) |
| |
| #define | VADC_G_ARBCFG_BUSY_Pos (30UL) |
| |
| #define | VADC_G_ARBCFG_BUSY_Msk (0x40000000UL) |
| |
| #define | VADC_G_ARBCFG_SAMPLE_Pos (31UL) |
| |
| #define | VADC_G_ARBCFG_SAMPLE_Msk (0x80000000UL) |
| |
| #define | VADC_G_ARBPR_PRIO0_Pos (0UL) |
| |
| #define | VADC_G_ARBPR_PRIO0_Msk (0x3UL) |
| |
| #define | VADC_G_ARBPR_CSM0_Pos (3UL) |
| |
| #define | VADC_G_ARBPR_CSM0_Msk (0x8UL) |
| |
| #define | VADC_G_ARBPR_PRIO1_Pos (4UL) |
| |
| #define | VADC_G_ARBPR_PRIO1_Msk (0x30UL) |
| |
| #define | VADC_G_ARBPR_CSM1_Pos (7UL) |
| |
| #define | VADC_G_ARBPR_CSM1_Msk (0x80UL) |
| |
| #define | VADC_G_ARBPR_PRIO2_Pos (8UL) |
| |
| #define | VADC_G_ARBPR_PRIO2_Msk (0x300UL) |
| |
| #define | VADC_G_ARBPR_CSM2_Pos (11UL) |
| |
| #define | VADC_G_ARBPR_CSM2_Msk (0x800UL) |
| |
| #define | VADC_G_ARBPR_ASEN0_Pos (24UL) |
| |
| #define | VADC_G_ARBPR_ASEN0_Msk (0x1000000UL) |
| |
| #define | VADC_G_ARBPR_ASEN1_Pos (25UL) |
| |
| #define | VADC_G_ARBPR_ASEN1_Msk (0x2000000UL) |
| |
| #define | VADC_G_ARBPR_ASEN2_Pos (26UL) |
| |
| #define | VADC_G_ARBPR_ASEN2_Msk (0x4000000UL) |
| |
| #define | VADC_G_CHASS_ASSCH0_Pos (0UL) |
| |
| #define | VADC_G_CHASS_ASSCH0_Msk (0x1UL) |
| |
| #define | VADC_G_CHASS_ASSCH1_Pos (1UL) |
| |
| #define | VADC_G_CHASS_ASSCH1_Msk (0x2UL) |
| |
| #define | VADC_G_CHASS_ASSCH2_Pos (2UL) |
| |
| #define | VADC_G_CHASS_ASSCH2_Msk (0x4UL) |
| |
| #define | VADC_G_CHASS_ASSCH3_Pos (3UL) |
| |
| #define | VADC_G_CHASS_ASSCH3_Msk (0x8UL) |
| |
| #define | VADC_G_CHASS_ASSCH4_Pos (4UL) |
| |
| #define | VADC_G_CHASS_ASSCH4_Msk (0x10UL) |
| |
| #define | VADC_G_CHASS_ASSCH5_Pos (5UL) |
| |
| #define | VADC_G_CHASS_ASSCH5_Msk (0x20UL) |
| |
| #define | VADC_G_CHASS_ASSCH6_Pos (6UL) |
| |
| #define | VADC_G_CHASS_ASSCH6_Msk (0x40UL) |
| |
| #define | VADC_G_CHASS_ASSCH7_Pos (7UL) |
| |
| #define | VADC_G_CHASS_ASSCH7_Msk (0x80UL) |
| |
| #define | VADC_G_ICLASS_STCS_Pos (0UL) |
| |
| #define | VADC_G_ICLASS_STCS_Msk (0x1fUL) |
| |
| #define | VADC_G_ICLASS_CMS_Pos (8UL) |
| |
| #define | VADC_G_ICLASS_CMS_Msk (0x700UL) |
| |
| #define | VADC_G_ICLASS_STCE_Pos (16UL) |
| |
| #define | VADC_G_ICLASS_STCE_Msk (0x1f0000UL) |
| |
| #define | VADC_G_ICLASS_CME_Pos (24UL) |
| |
| #define | VADC_G_ICLASS_CME_Msk (0x7000000UL) |
| |
| #define | VADC_G_ALIAS_ALIAS0_Pos (0UL) |
| |
| #define | VADC_G_ALIAS_ALIAS0_Msk (0x1fUL) |
| |
| #define | VADC_G_ALIAS_ALIAS1_Pos (8UL) |
| |
| #define | VADC_G_ALIAS_ALIAS1_Msk (0x1f00UL) |
| |
| #define | VADC_G_BOUND_BOUNDARY0_Pos (0UL) |
| |
| #define | VADC_G_BOUND_BOUNDARY0_Msk (0xfffUL) |
| |
| #define | VADC_G_BOUND_BOUNDARY1_Pos (16UL) |
| |
| #define | VADC_G_BOUND_BOUNDARY1_Msk (0xfff0000UL) |
| |
| #define | VADC_G_SYNCTR_STSEL_Pos (0UL) |
| |
| #define | VADC_G_SYNCTR_STSEL_Msk (0x3UL) |
| |
| #define | VADC_G_SYNCTR_EVALR1_Pos (4UL) |
| |
| #define | VADC_G_SYNCTR_EVALR1_Msk (0x10UL) |
| |
| #define | VADC_G_SYNCTR_EVALR2_Pos (5UL) |
| |
| #define | VADC_G_SYNCTR_EVALR2_Msk (0x20UL) |
| |
| #define | VADC_G_SYNCTR_EVALR3_Pos (6UL) |
| |
| #define | VADC_G_SYNCTR_EVALR3_Msk (0x40UL) |
| |
| #define | VADC_G_BFL_BFL0_Pos (0UL) |
| |
| #define | VADC_G_BFL_BFL0_Msk (0x1UL) |
| |
| #define | VADC_G_BFL_BFL1_Pos (1UL) |
| |
| #define | VADC_G_BFL_BFL1_Msk (0x2UL) |
| |
| #define | VADC_G_BFL_BFL2_Pos (2UL) |
| |
| #define | VADC_G_BFL_BFL2_Msk (0x4UL) |
| |
| #define | VADC_G_BFL_BFL3_Pos (3UL) |
| |
| #define | VADC_G_BFL_BFL3_Msk (0x8UL) |
| |
| #define | VADC_G_BFL_BFA0_Pos (8UL) |
| |
| #define | VADC_G_BFL_BFA0_Msk (0x100UL) |
| |
| #define | VADC_G_BFL_BFA1_Pos (9UL) |
| |
| #define | VADC_G_BFL_BFA1_Msk (0x200UL) |
| |
| #define | VADC_G_BFL_BFA2_Pos (10UL) |
| |
| #define | VADC_G_BFL_BFA2_Msk (0x400UL) |
| |
| #define | VADC_G_BFL_BFA3_Pos (11UL) |
| |
| #define | VADC_G_BFL_BFA3_Msk (0x800UL) |
| |
| #define | VADC_G_BFL_BFI0_Pos (16UL) |
| |
| #define | VADC_G_BFL_BFI0_Msk (0x10000UL) |
| |
| #define | VADC_G_BFL_BFI1_Pos (17UL) |
| |
| #define | VADC_G_BFL_BFI1_Msk (0x20000UL) |
| |
| #define | VADC_G_BFL_BFI2_Pos (18UL) |
| |
| #define | VADC_G_BFL_BFI2_Msk (0x40000UL) |
| |
| #define | VADC_G_BFL_BFI3_Pos (19UL) |
| |
| #define | VADC_G_BFL_BFI3_Msk (0x80000UL) |
| |
| #define | VADC_G_BFLS_BFC0_Pos (0UL) |
| |
| #define | VADC_G_BFLS_BFC0_Msk (0x1UL) |
| |
| #define | VADC_G_BFLS_BFC1_Pos (1UL) |
| |
| #define | VADC_G_BFLS_BFC1_Msk (0x2UL) |
| |
| #define | VADC_G_BFLS_BFC2_Pos (2UL) |
| |
| #define | VADC_G_BFLS_BFC2_Msk (0x4UL) |
| |
| #define | VADC_G_BFLS_BFC3_Pos (3UL) |
| |
| #define | VADC_G_BFLS_BFC3_Msk (0x8UL) |
| |
| #define | VADC_G_BFLS_BFS0_Pos (16UL) |
| |
| #define | VADC_G_BFLS_BFS0_Msk (0x10000UL) |
| |
| #define | VADC_G_BFLS_BFS1_Pos (17UL) |
| |
| #define | VADC_G_BFLS_BFS1_Msk (0x20000UL) |
| |
| #define | VADC_G_BFLS_BFS2_Pos (18UL) |
| |
| #define | VADC_G_BFLS_BFS2_Msk (0x40000UL) |
| |
| #define | VADC_G_BFLS_BFS3_Pos (19UL) |
| |
| #define | VADC_G_BFLS_BFS3_Msk (0x80000UL) |
| |
| #define | VADC_G_BFLC_BFM0_Pos (0UL) |
| |
| #define | VADC_G_BFLC_BFM0_Msk (0xfUL) |
| |
| #define | VADC_G_BFLC_BFM1_Pos (4UL) |
| |
| #define | VADC_G_BFLC_BFM1_Msk (0xf0UL) |
| |
| #define | VADC_G_BFLC_BFM2_Pos (8UL) |
| |
| #define | VADC_G_BFLC_BFM2_Msk (0xf00UL) |
| |
| #define | VADC_G_BFLC_BFM3_Pos (12UL) |
| |
| #define | VADC_G_BFLC_BFM3_Msk (0xf000UL) |
| |
| #define | VADC_G_BFLNP_BFL0NP_Pos (0UL) |
| |
| #define | VADC_G_BFLNP_BFL0NP_Msk (0xfUL) |
| |
| #define | VADC_G_BFLNP_BFL1NP_Pos (4UL) |
| |
| #define | VADC_G_BFLNP_BFL1NP_Msk (0xf0UL) |
| |
| #define | VADC_G_BFLNP_BFL2NP_Pos (8UL) |
| |
| #define | VADC_G_BFLNP_BFL2NP_Msk (0xf00UL) |
| |
| #define | VADC_G_BFLNP_BFL3NP_Pos (12UL) |
| |
| #define | VADC_G_BFLNP_BFL3NP_Msk (0xf000UL) |
| |
| #define | VADC_G_QCTRL0_SRCRESREG_Pos (0UL) |
| |
| #define | VADC_G_QCTRL0_SRCRESREG_Msk (0xfUL) |
| |
| #define | VADC_G_QCTRL0_XTSEL_Pos (8UL) |
| |
| #define | VADC_G_QCTRL0_XTSEL_Msk (0xf00UL) |
| |
| #define | VADC_G_QCTRL0_XTLVL_Pos (12UL) |
| |
| #define | VADC_G_QCTRL0_XTLVL_Msk (0x1000UL) |
| |
| #define | VADC_G_QCTRL0_XTMODE_Pos (13UL) |
| |
| #define | VADC_G_QCTRL0_XTMODE_Msk (0x6000UL) |
| |
| #define | VADC_G_QCTRL0_XTWC_Pos (15UL) |
| |
| #define | VADC_G_QCTRL0_XTWC_Msk (0x8000UL) |
| |
| #define | VADC_G_QCTRL0_GTSEL_Pos (16UL) |
| |
| #define | VADC_G_QCTRL0_GTSEL_Msk (0xf0000UL) |
| |
| #define | VADC_G_QCTRL0_GTLVL_Pos (20UL) |
| |
| #define | VADC_G_QCTRL0_GTLVL_Msk (0x100000UL) |
| |
| #define | VADC_G_QCTRL0_GTWC_Pos (23UL) |
| |
| #define | VADC_G_QCTRL0_GTWC_Msk (0x800000UL) |
| |
| #define | VADC_G_QCTRL0_TMEN_Pos (28UL) |
| |
| #define | VADC_G_QCTRL0_TMEN_Msk (0x10000000UL) |
| |
| #define | VADC_G_QCTRL0_TMWC_Pos (31UL) |
| |
| #define | VADC_G_QCTRL0_TMWC_Msk (0x80000000UL) |
| |
| #define | VADC_G_QMR0_ENGT_Pos (0UL) |
| |
| #define | VADC_G_QMR0_ENGT_Msk (0x3UL) |
| |
| #define | VADC_G_QMR0_ENTR_Pos (2UL) |
| |
| #define | VADC_G_QMR0_ENTR_Msk (0x4UL) |
| |
| #define | VADC_G_QMR0_CLRV_Pos (8UL) |
| |
| #define | VADC_G_QMR0_CLRV_Msk (0x100UL) |
| |
| #define | VADC_G_QMR0_TREV_Pos (9UL) |
| |
| #define | VADC_G_QMR0_TREV_Msk (0x200UL) |
| |
| #define | VADC_G_QMR0_FLUSH_Pos (10UL) |
| |
| #define | VADC_G_QMR0_FLUSH_Msk (0x400UL) |
| |
| #define | VADC_G_QMR0_CEV_Pos (11UL) |
| |
| #define | VADC_G_QMR0_CEV_Msk (0x800UL) |
| |
| #define | VADC_G_QMR0_RPTDIS_Pos (16UL) |
| |
| #define | VADC_G_QMR0_RPTDIS_Msk (0x10000UL) |
| |
| #define | VADC_G_QSR0_FILL_Pos (0UL) |
| |
| #define | VADC_G_QSR0_FILL_Msk (0xfUL) |
| |
| #define | VADC_G_QSR0_EMPTY_Pos (5UL) |
| |
| #define | VADC_G_QSR0_EMPTY_Msk (0x20UL) |
| |
| #define | VADC_G_QSR0_REQGT_Pos (7UL) |
| |
| #define | VADC_G_QSR0_REQGT_Msk (0x80UL) |
| |
| #define | VADC_G_QSR0_EV_Pos (8UL) |
| |
| #define | VADC_G_QSR0_EV_Msk (0x100UL) |
| |
| #define | VADC_G_Q0R0_REQCHNR_Pos (0UL) |
| |
| #define | VADC_G_Q0R0_REQCHNR_Msk (0x1fUL) |
| |
| #define | VADC_G_Q0R0_RF_Pos (5UL) |
| |
| #define | VADC_G_Q0R0_RF_Msk (0x20UL) |
| |
| #define | VADC_G_Q0R0_ENSI_Pos (6UL) |
| |
| #define | VADC_G_Q0R0_ENSI_Msk (0x40UL) |
| |
| #define | VADC_G_Q0R0_EXTR_Pos (7UL) |
| |
| #define | VADC_G_Q0R0_EXTR_Msk (0x80UL) |
| |
| #define | VADC_G_Q0R0_V_Pos (8UL) |
| |
| #define | VADC_G_Q0R0_V_Msk (0x100UL) |
| |
| #define | VADC_G_QINR0_REQCHNR_Pos (0UL) |
| |
| #define | VADC_G_QINR0_REQCHNR_Msk (0x1fUL) |
| |
| #define | VADC_G_QINR0_RF_Pos (5UL) |
| |
| #define | VADC_G_QINR0_RF_Msk (0x20UL) |
| |
| #define | VADC_G_QINR0_ENSI_Pos (6UL) |
| |
| #define | VADC_G_QINR0_ENSI_Msk (0x40UL) |
| |
| #define | VADC_G_QINR0_EXTR_Pos (7UL) |
| |
| #define | VADC_G_QINR0_EXTR_Msk (0x80UL) |
| |
| #define | VADC_G_QBUR0_REQCHNR_Pos (0UL) |
| |
| #define | VADC_G_QBUR0_REQCHNR_Msk (0x1fUL) |
| |
| #define | VADC_G_QBUR0_RF_Pos (5UL) |
| |
| #define | VADC_G_QBUR0_RF_Msk (0x20UL) |
| |
| #define | VADC_G_QBUR0_ENSI_Pos (6UL) |
| |
| #define | VADC_G_QBUR0_ENSI_Msk (0x40UL) |
| |
| #define | VADC_G_QBUR0_EXTR_Pos (7UL) |
| |
| #define | VADC_G_QBUR0_EXTR_Msk (0x80UL) |
| |
| #define | VADC_G_QBUR0_V_Pos (8UL) |
| |
| #define | VADC_G_QBUR0_V_Msk (0x100UL) |
| |
| #define | VADC_G_ASCTRL_SRCRESREG_Pos (0UL) |
| |
| #define | VADC_G_ASCTRL_SRCRESREG_Msk (0xfUL) |
| |
| #define | VADC_G_ASCTRL_XTSEL_Pos (8UL) |
| |
| #define | VADC_G_ASCTRL_XTSEL_Msk (0xf00UL) |
| |
| #define | VADC_G_ASCTRL_XTLVL_Pos (12UL) |
| |
| #define | VADC_G_ASCTRL_XTLVL_Msk (0x1000UL) |
| |
| #define | VADC_G_ASCTRL_XTMODE_Pos (13UL) |
| |
| #define | VADC_G_ASCTRL_XTMODE_Msk (0x6000UL) |
| |
| #define | VADC_G_ASCTRL_XTWC_Pos (15UL) |
| |
| #define | VADC_G_ASCTRL_XTWC_Msk (0x8000UL) |
| |
| #define | VADC_G_ASCTRL_GTSEL_Pos (16UL) |
| |
| #define | VADC_G_ASCTRL_GTSEL_Msk (0xf0000UL) |
| |
| #define | VADC_G_ASCTRL_GTLVL_Pos (20UL) |
| |
| #define | VADC_G_ASCTRL_GTLVL_Msk (0x100000UL) |
| |
| #define | VADC_G_ASCTRL_GTWC_Pos (23UL) |
| |
| #define | VADC_G_ASCTRL_GTWC_Msk (0x800000UL) |
| |
| #define | VADC_G_ASCTRL_TMEN_Pos (28UL) |
| |
| #define | VADC_G_ASCTRL_TMEN_Msk (0x10000000UL) |
| |
| #define | VADC_G_ASCTRL_TMWC_Pos (31UL) |
| |
| #define | VADC_G_ASCTRL_TMWC_Msk (0x80000000UL) |
| |
| #define | VADC_G_ASMR_ENGT_Pos (0UL) |
| |
| #define | VADC_G_ASMR_ENGT_Msk (0x3UL) |
| |
| #define | VADC_G_ASMR_ENTR_Pos (2UL) |
| |
| #define | VADC_G_ASMR_ENTR_Msk (0x4UL) |
| |
| #define | VADC_G_ASMR_ENSI_Pos (3UL) |
| |
| #define | VADC_G_ASMR_ENSI_Msk (0x8UL) |
| |
| #define | VADC_G_ASMR_SCAN_Pos (4UL) |
| |
| #define | VADC_G_ASMR_SCAN_Msk (0x10UL) |
| |
| #define | VADC_G_ASMR_LDM_Pos (5UL) |
| |
| #define | VADC_G_ASMR_LDM_Msk (0x20UL) |
| |
| #define | VADC_G_ASMR_REQGT_Pos (7UL) |
| |
| #define | VADC_G_ASMR_REQGT_Msk (0x80UL) |
| |
| #define | VADC_G_ASMR_CLRPND_Pos (8UL) |
| |
| #define | VADC_G_ASMR_CLRPND_Msk (0x100UL) |
| |
| #define | VADC_G_ASMR_LDEV_Pos (9UL) |
| |
| #define | VADC_G_ASMR_LDEV_Msk (0x200UL) |
| |
| #define | VADC_G_ASMR_RPTDIS_Pos (16UL) |
| |
| #define | VADC_G_ASMR_RPTDIS_Msk (0x10000UL) |
| |
| #define | VADC_G_ASSEL_CHSEL0_Pos (0UL) |
| |
| #define | VADC_G_ASSEL_CHSEL0_Msk (0x1UL) |
| |
| #define | VADC_G_ASSEL_CHSEL1_Pos (1UL) |
| |
| #define | VADC_G_ASSEL_CHSEL1_Msk (0x2UL) |
| |
| #define | VADC_G_ASSEL_CHSEL2_Pos (2UL) |
| |
| #define | VADC_G_ASSEL_CHSEL2_Msk (0x4UL) |
| |
| #define | VADC_G_ASSEL_CHSEL3_Pos (3UL) |
| |
| #define | VADC_G_ASSEL_CHSEL3_Msk (0x8UL) |
| |
| #define | VADC_G_ASSEL_CHSEL4_Pos (4UL) |
| |
| #define | VADC_G_ASSEL_CHSEL4_Msk (0x10UL) |
| |
| #define | VADC_G_ASSEL_CHSEL5_Pos (5UL) |
| |
| #define | VADC_G_ASSEL_CHSEL5_Msk (0x20UL) |
| |
| #define | VADC_G_ASSEL_CHSEL6_Pos (6UL) |
| |
| #define | VADC_G_ASSEL_CHSEL6_Msk (0x40UL) |
| |
| #define | VADC_G_ASSEL_CHSEL7_Pos (7UL) |
| |
| #define | VADC_G_ASSEL_CHSEL7_Msk (0x80UL) |
| |
| #define | VADC_G_ASPND_CHPND0_Pos (0UL) |
| |
| #define | VADC_G_ASPND_CHPND0_Msk (0x1UL) |
| |
| #define | VADC_G_ASPND_CHPND1_Pos (1UL) |
| |
| #define | VADC_G_ASPND_CHPND1_Msk (0x2UL) |
| |
| #define | VADC_G_ASPND_CHPND2_Pos (2UL) |
| |
| #define | VADC_G_ASPND_CHPND2_Msk (0x4UL) |
| |
| #define | VADC_G_ASPND_CHPND3_Pos (3UL) |
| |
| #define | VADC_G_ASPND_CHPND3_Msk (0x8UL) |
| |
| #define | VADC_G_ASPND_CHPND4_Pos (4UL) |
| |
| #define | VADC_G_ASPND_CHPND4_Msk (0x10UL) |
| |
| #define | VADC_G_ASPND_CHPND5_Pos (5UL) |
| |
| #define | VADC_G_ASPND_CHPND5_Msk (0x20UL) |
| |
| #define | VADC_G_ASPND_CHPND6_Pos (6UL) |
| |
| #define | VADC_G_ASPND_CHPND6_Msk (0x40UL) |
| |
| #define | VADC_G_ASPND_CHPND7_Pos (7UL) |
| |
| #define | VADC_G_ASPND_CHPND7_Msk (0x80UL) |
| |
| #define | VADC_G_CEFLAG_CEV0_Pos (0UL) |
| |
| #define | VADC_G_CEFLAG_CEV0_Msk (0x1UL) |
| |
| #define | VADC_G_CEFLAG_CEV1_Pos (1UL) |
| |
| #define | VADC_G_CEFLAG_CEV1_Msk (0x2UL) |
| |
| #define | VADC_G_CEFLAG_CEV2_Pos (2UL) |
| |
| #define | VADC_G_CEFLAG_CEV2_Msk (0x4UL) |
| |
| #define | VADC_G_CEFLAG_CEV3_Pos (3UL) |
| |
| #define | VADC_G_CEFLAG_CEV3_Msk (0x8UL) |
| |
| #define | VADC_G_CEFLAG_CEV4_Pos (4UL) |
| |
| #define | VADC_G_CEFLAG_CEV4_Msk (0x10UL) |
| |
| #define | VADC_G_CEFLAG_CEV5_Pos (5UL) |
| |
| #define | VADC_G_CEFLAG_CEV5_Msk (0x20UL) |
| |
| #define | VADC_G_CEFLAG_CEV6_Pos (6UL) |
| |
| #define | VADC_G_CEFLAG_CEV6_Msk (0x40UL) |
| |
| #define | VADC_G_CEFLAG_CEV7_Pos (7UL) |
| |
| #define | VADC_G_CEFLAG_CEV7_Msk (0x80UL) |
| |
| #define | VADC_G_REFLAG_REV0_Pos (0UL) |
| |
| #define | VADC_G_REFLAG_REV0_Msk (0x1UL) |
| |
| #define | VADC_G_REFLAG_REV1_Pos (1UL) |
| |
| #define | VADC_G_REFLAG_REV1_Msk (0x2UL) |
| |
| #define | VADC_G_REFLAG_REV2_Pos (2UL) |
| |
| #define | VADC_G_REFLAG_REV2_Msk (0x4UL) |
| |
| #define | VADC_G_REFLAG_REV3_Pos (3UL) |
| |
| #define | VADC_G_REFLAG_REV3_Msk (0x8UL) |
| |
| #define | VADC_G_REFLAG_REV4_Pos (4UL) |
| |
| #define | VADC_G_REFLAG_REV4_Msk (0x10UL) |
| |
| #define | VADC_G_REFLAG_REV5_Pos (5UL) |
| |
| #define | VADC_G_REFLAG_REV5_Msk (0x20UL) |
| |
| #define | VADC_G_REFLAG_REV6_Pos (6UL) |
| |
| #define | VADC_G_REFLAG_REV6_Msk (0x40UL) |
| |
| #define | VADC_G_REFLAG_REV7_Pos (7UL) |
| |
| #define | VADC_G_REFLAG_REV7_Msk (0x80UL) |
| |
| #define | VADC_G_REFLAG_REV8_Pos (8UL) |
| |
| #define | VADC_G_REFLAG_REV8_Msk (0x100UL) |
| |
| #define | VADC_G_REFLAG_REV9_Pos (9UL) |
| |
| #define | VADC_G_REFLAG_REV9_Msk (0x200UL) |
| |
| #define | VADC_G_REFLAG_REV10_Pos (10UL) |
| |
| #define | VADC_G_REFLAG_REV10_Msk (0x400UL) |
| |
| #define | VADC_G_REFLAG_REV11_Pos (11UL) |
| |
| #define | VADC_G_REFLAG_REV11_Msk (0x800UL) |
| |
| #define | VADC_G_REFLAG_REV12_Pos (12UL) |
| |
| #define | VADC_G_REFLAG_REV12_Msk (0x1000UL) |
| |
| #define | VADC_G_REFLAG_REV13_Pos (13UL) |
| |
| #define | VADC_G_REFLAG_REV13_Msk (0x2000UL) |
| |
| #define | VADC_G_REFLAG_REV14_Pos (14UL) |
| |
| #define | VADC_G_REFLAG_REV14_Msk (0x4000UL) |
| |
| #define | VADC_G_REFLAG_REV15_Pos (15UL) |
| |
| #define | VADC_G_REFLAG_REV15_Msk (0x8000UL) |
| |
| #define | VADC_G_SEFLAG_SEV0_Pos (0UL) |
| |
| #define | VADC_G_SEFLAG_SEV0_Msk (0x1UL) |
| |
| #define | VADC_G_SEFLAG_SEV1_Pos (1UL) |
| |
| #define | VADC_G_SEFLAG_SEV1_Msk (0x2UL) |
| |
| #define | VADC_G_CEFCLR_CEV0_Pos (0UL) |
| |
| #define | VADC_G_CEFCLR_CEV0_Msk (0x1UL) |
| |
| #define | VADC_G_CEFCLR_CEV1_Pos (1UL) |
| |
| #define | VADC_G_CEFCLR_CEV1_Msk (0x2UL) |
| |
| #define | VADC_G_CEFCLR_CEV2_Pos (2UL) |
| |
| #define | VADC_G_CEFCLR_CEV2_Msk (0x4UL) |
| |
| #define | VADC_G_CEFCLR_CEV3_Pos (3UL) |
| |
| #define | VADC_G_CEFCLR_CEV3_Msk (0x8UL) |
| |
| #define | VADC_G_CEFCLR_CEV4_Pos (4UL) |
| |
| #define | VADC_G_CEFCLR_CEV4_Msk (0x10UL) |
| |
| #define | VADC_G_CEFCLR_CEV5_Pos (5UL) |
| |
| #define | VADC_G_CEFCLR_CEV5_Msk (0x20UL) |
| |
| #define | VADC_G_CEFCLR_CEV6_Pos (6UL) |
| |
| #define | VADC_G_CEFCLR_CEV6_Msk (0x40UL) |
| |
| #define | VADC_G_CEFCLR_CEV7_Pos (7UL) |
| |
| #define | VADC_G_CEFCLR_CEV7_Msk (0x80UL) |
| |
| #define | VADC_G_REFCLR_REV0_Pos (0UL) |
| |
| #define | VADC_G_REFCLR_REV0_Msk (0x1UL) |
| |
| #define | VADC_G_REFCLR_REV1_Pos (1UL) |
| |
| #define | VADC_G_REFCLR_REV1_Msk (0x2UL) |
| |
| #define | VADC_G_REFCLR_REV2_Pos (2UL) |
| |
| #define | VADC_G_REFCLR_REV2_Msk (0x4UL) |
| |
| #define | VADC_G_REFCLR_REV3_Pos (3UL) |
| |
| #define | VADC_G_REFCLR_REV3_Msk (0x8UL) |
| |
| #define | VADC_G_REFCLR_REV4_Pos (4UL) |
| |
| #define | VADC_G_REFCLR_REV4_Msk (0x10UL) |
| |
| #define | VADC_G_REFCLR_REV5_Pos (5UL) |
| |
| #define | VADC_G_REFCLR_REV5_Msk (0x20UL) |
| |
| #define | VADC_G_REFCLR_REV6_Pos (6UL) |
| |
| #define | VADC_G_REFCLR_REV6_Msk (0x40UL) |
| |
| #define | VADC_G_REFCLR_REV7_Pos (7UL) |
| |
| #define | VADC_G_REFCLR_REV7_Msk (0x80UL) |
| |
| #define | VADC_G_REFCLR_REV8_Pos (8UL) |
| |
| #define | VADC_G_REFCLR_REV8_Msk (0x100UL) |
| |
| #define | VADC_G_REFCLR_REV9_Pos (9UL) |
| |
| #define | VADC_G_REFCLR_REV9_Msk (0x200UL) |
| |
| #define | VADC_G_REFCLR_REV10_Pos (10UL) |
| |
| #define | VADC_G_REFCLR_REV10_Msk (0x400UL) |
| |
| #define | VADC_G_REFCLR_REV11_Pos (11UL) |
| |
| #define | VADC_G_REFCLR_REV11_Msk (0x800UL) |
| |
| #define | VADC_G_REFCLR_REV12_Pos (12UL) |
| |
| #define | VADC_G_REFCLR_REV12_Msk (0x1000UL) |
| |
| #define | VADC_G_REFCLR_REV13_Pos (13UL) |
| |
| #define | VADC_G_REFCLR_REV13_Msk (0x2000UL) |
| |
| #define | VADC_G_REFCLR_REV14_Pos (14UL) |
| |
| #define | VADC_G_REFCLR_REV14_Msk (0x4000UL) |
| |
| #define | VADC_G_REFCLR_REV15_Pos (15UL) |
| |
| #define | VADC_G_REFCLR_REV15_Msk (0x8000UL) |
| |
| #define | VADC_G_SEFCLR_SEV0_Pos (0UL) |
| |
| #define | VADC_G_SEFCLR_SEV0_Msk (0x1UL) |
| |
| #define | VADC_G_SEFCLR_SEV1_Pos (1UL) |
| |
| #define | VADC_G_SEFCLR_SEV1_Msk (0x2UL) |
| |
| #define | VADC_G_CEVNP0_CEV0NP_Pos (0UL) |
| |
| #define | VADC_G_CEVNP0_CEV0NP_Msk (0xfUL) |
| |
| #define | VADC_G_CEVNP0_CEV1NP_Pos (4UL) |
| |
| #define | VADC_G_CEVNP0_CEV1NP_Msk (0xf0UL) |
| |
| #define | VADC_G_CEVNP0_CEV2NP_Pos (8UL) |
| |
| #define | VADC_G_CEVNP0_CEV2NP_Msk (0xf00UL) |
| |
| #define | VADC_G_CEVNP0_CEV3NP_Pos (12UL) |
| |
| #define | VADC_G_CEVNP0_CEV3NP_Msk (0xf000UL) |
| |
| #define | VADC_G_CEVNP0_CEV4NP_Pos (16UL) |
| |
| #define | VADC_G_CEVNP0_CEV4NP_Msk (0xf0000UL) |
| |
| #define | VADC_G_CEVNP0_CEV5NP_Pos (20UL) |
| |
| #define | VADC_G_CEVNP0_CEV5NP_Msk (0xf00000UL) |
| |
| #define | VADC_G_CEVNP0_CEV6NP_Pos (24UL) |
| |
| #define | VADC_G_CEVNP0_CEV6NP_Msk (0xf000000UL) |
| |
| #define | VADC_G_CEVNP0_CEV7NP_Pos (28UL) |
| |
| #define | VADC_G_CEVNP0_CEV7NP_Msk (0xf0000000UL) |
| |
| #define | VADC_G_REVNP0_REV0NP_Pos (0UL) |
| |
| #define | VADC_G_REVNP0_REV0NP_Msk (0xfUL) |
| |
| #define | VADC_G_REVNP0_REV1NP_Pos (4UL) |
| |
| #define | VADC_G_REVNP0_REV1NP_Msk (0xf0UL) |
| |
| #define | VADC_G_REVNP0_REV2NP_Pos (8UL) |
| |
| #define | VADC_G_REVNP0_REV2NP_Msk (0xf00UL) |
| |
| #define | VADC_G_REVNP0_REV3NP_Pos (12UL) |
| |
| #define | VADC_G_REVNP0_REV3NP_Msk (0xf000UL) |
| |
| #define | VADC_G_REVNP0_REV4NP_Pos (16UL) |
| |
| #define | VADC_G_REVNP0_REV4NP_Msk (0xf0000UL) |
| |
| #define | VADC_G_REVNP0_REV5NP_Pos (20UL) |
| |
| #define | VADC_G_REVNP0_REV5NP_Msk (0xf00000UL) |
| |
| #define | VADC_G_REVNP0_REV6NP_Pos (24UL) |
| |
| #define | VADC_G_REVNP0_REV6NP_Msk (0xf000000UL) |
| |
| #define | VADC_G_REVNP0_REV7NP_Pos (28UL) |
| |
| #define | VADC_G_REVNP0_REV7NP_Msk (0xf0000000UL) |
| |
| #define | VADC_G_REVNP1_REV8NP_Pos (0UL) |
| |
| #define | VADC_G_REVNP1_REV8NP_Msk (0xfUL) |
| |
| #define | VADC_G_REVNP1_REV9NP_Pos (4UL) |
| |
| #define | VADC_G_REVNP1_REV9NP_Msk (0xf0UL) |
| |
| #define | VADC_G_REVNP1_REV10NP_Pos (8UL) |
| |
| #define | VADC_G_REVNP1_REV10NP_Msk (0xf00UL) |
| |
| #define | VADC_G_REVNP1_REV11NP_Pos (12UL) |
| |
| #define | VADC_G_REVNP1_REV11NP_Msk (0xf000UL) |
| |
| #define | VADC_G_REVNP1_REV12NP_Pos (16UL) |
| |
| #define | VADC_G_REVNP1_REV12NP_Msk (0xf0000UL) |
| |
| #define | VADC_G_REVNP1_REV13NP_Pos (20UL) |
| |
| #define | VADC_G_REVNP1_REV13NP_Msk (0xf00000UL) |
| |
| #define | VADC_G_REVNP1_REV14NP_Pos (24UL) |
| |
| #define | VADC_G_REVNP1_REV14NP_Msk (0xf000000UL) |
| |
| #define | VADC_G_REVNP1_REV15NP_Pos (28UL) |
| |
| #define | VADC_G_REVNP1_REV15NP_Msk (0xf0000000UL) |
| |
| #define | VADC_G_SEVNP_SEV0NP_Pos (0UL) |
| |
| #define | VADC_G_SEVNP_SEV0NP_Msk (0xfUL) |
| |
| #define | VADC_G_SEVNP_SEV1NP_Pos (4UL) |
| |
| #define | VADC_G_SEVNP_SEV1NP_Msk (0xf0UL) |
| |
| #define | VADC_G_SRACT_AGSR0_Pos (0UL) |
| |
| #define | VADC_G_SRACT_AGSR0_Msk (0x1UL) |
| |
| #define | VADC_G_SRACT_AGSR1_Pos (1UL) |
| |
| #define | VADC_G_SRACT_AGSR1_Msk (0x2UL) |
| |
| #define | VADC_G_SRACT_AGSR2_Pos (2UL) |
| |
| #define | VADC_G_SRACT_AGSR2_Msk (0x4UL) |
| |
| #define | VADC_G_SRACT_AGSR3_Pos (3UL) |
| |
| #define | VADC_G_SRACT_AGSR3_Msk (0x8UL) |
| |
| #define | VADC_G_SRACT_ASSR0_Pos (8UL) |
| |
| #define | VADC_G_SRACT_ASSR0_Msk (0x100UL) |
| |
| #define | VADC_G_SRACT_ASSR1_Pos (9UL) |
| |
| #define | VADC_G_SRACT_ASSR1_Msk (0x200UL) |
| |
| #define | VADC_G_SRACT_ASSR2_Pos (10UL) |
| |
| #define | VADC_G_SRACT_ASSR2_Msk (0x400UL) |
| |
| #define | VADC_G_SRACT_ASSR3_Pos (11UL) |
| |
| #define | VADC_G_SRACT_ASSR3_Msk (0x800UL) |
| |
| #define | VADC_G_EMUXCTR_EMUXSET_Pos (0UL) |
| |
| #define | VADC_G_EMUXCTR_EMUXSET_Msk (0x7UL) |
| |
| #define | VADC_G_EMUXCTR_EMUXACT_Pos (8UL) |
| |
| #define | VADC_G_EMUXCTR_EMUXACT_Msk (0x700UL) |
| |
| #define | VADC_G_EMUXCTR_EMUXCH_Pos (16UL) |
| |
| #define | VADC_G_EMUXCTR_EMUXCH_Msk (0x3ff0000UL) |
| |
| #define | VADC_G_EMUXCTR_EMUXMODE_Pos (26UL) |
| |
| #define | VADC_G_EMUXCTR_EMUXMODE_Msk (0xc000000UL) |
| |
| #define | VADC_G_EMUXCTR_EMXCOD_Pos (28UL) |
| |
| #define | VADC_G_EMUXCTR_EMXCOD_Msk (0x10000000UL) |
| |
| #define | VADC_G_EMUXCTR_EMXST_Pos (29UL) |
| |
| #define | VADC_G_EMUXCTR_EMXST_Msk (0x20000000UL) |
| |
| #define | VADC_G_EMUXCTR_EMXCSS_Pos (30UL) |
| |
| #define | VADC_G_EMUXCTR_EMXCSS_Msk (0x40000000UL) |
| |
| #define | VADC_G_EMUXCTR_EMXWC_Pos (31UL) |
| |
| #define | VADC_G_EMUXCTR_EMXWC_Msk (0x80000000UL) |
| |
| #define | VADC_G_VFR_VF0_Pos (0UL) |
| |
| #define | VADC_G_VFR_VF0_Msk (0x1UL) |
| |
| #define | VADC_G_VFR_VF1_Pos (1UL) |
| |
| #define | VADC_G_VFR_VF1_Msk (0x2UL) |
| |
| #define | VADC_G_VFR_VF2_Pos (2UL) |
| |
| #define | VADC_G_VFR_VF2_Msk (0x4UL) |
| |
| #define | VADC_G_VFR_VF3_Pos (3UL) |
| |
| #define | VADC_G_VFR_VF3_Msk (0x8UL) |
| |
| #define | VADC_G_VFR_VF4_Pos (4UL) |
| |
| #define | VADC_G_VFR_VF4_Msk (0x10UL) |
| |
| #define | VADC_G_VFR_VF5_Pos (5UL) |
| |
| #define | VADC_G_VFR_VF5_Msk (0x20UL) |
| |
| #define | VADC_G_VFR_VF6_Pos (6UL) |
| |
| #define | VADC_G_VFR_VF6_Msk (0x40UL) |
| |
| #define | VADC_G_VFR_VF7_Pos (7UL) |
| |
| #define | VADC_G_VFR_VF7_Msk (0x80UL) |
| |
| #define | VADC_G_VFR_VF8_Pos (8UL) |
| |
| #define | VADC_G_VFR_VF8_Msk (0x100UL) |
| |
| #define | VADC_G_VFR_VF9_Pos (9UL) |
| |
| #define | VADC_G_VFR_VF9_Msk (0x200UL) |
| |
| #define | VADC_G_VFR_VF10_Pos (10UL) |
| |
| #define | VADC_G_VFR_VF10_Msk (0x400UL) |
| |
| #define | VADC_G_VFR_VF11_Pos (11UL) |
| |
| #define | VADC_G_VFR_VF11_Msk (0x800UL) |
| |
| #define | VADC_G_VFR_VF12_Pos (12UL) |
| |
| #define | VADC_G_VFR_VF12_Msk (0x1000UL) |
| |
| #define | VADC_G_VFR_VF13_Pos (13UL) |
| |
| #define | VADC_G_VFR_VF13_Msk (0x2000UL) |
| |
| #define | VADC_G_VFR_VF14_Pos (14UL) |
| |
| #define | VADC_G_VFR_VF14_Msk (0x4000UL) |
| |
| #define | VADC_G_VFR_VF15_Pos (15UL) |
| |
| #define | VADC_G_VFR_VF15_Msk (0x8000UL) |
| |
| #define | VADC_G_CHCTR_ICLSEL_Pos (0UL) |
| |
| #define | VADC_G_CHCTR_ICLSEL_Msk (0x3UL) |
| |
| #define | VADC_G_CHCTR_BNDSELL_Pos (4UL) |
| |
| #define | VADC_G_CHCTR_BNDSELL_Msk (0x30UL) |
| |
| #define | VADC_G_CHCTR_BNDSELU_Pos (6UL) |
| |
| #define | VADC_G_CHCTR_BNDSELU_Msk (0xc0UL) |
| |
| #define | VADC_G_CHCTR_CHEVMODE_Pos (8UL) |
| |
| #define | VADC_G_CHCTR_CHEVMODE_Msk (0x300UL) |
| |
| #define | VADC_G_CHCTR_SYNC_Pos (10UL) |
| |
| #define | VADC_G_CHCTR_SYNC_Msk (0x400UL) |
| |
| #define | VADC_G_CHCTR_REFSEL_Pos (11UL) |
| |
| #define | VADC_G_CHCTR_REFSEL_Msk (0x800UL) |
| |
| #define | VADC_G_CHCTR_RESREG_Pos (16UL) |
| |
| #define | VADC_G_CHCTR_RESREG_Msk (0xf0000UL) |
| |
| #define | VADC_G_CHCTR_RESTBS_Pos (20UL) |
| |
| #define | VADC_G_CHCTR_RESTBS_Msk (0x100000UL) |
| |
| #define | VADC_G_CHCTR_RESPOS_Pos (21UL) |
| |
| #define | VADC_G_CHCTR_RESPOS_Msk (0x200000UL) |
| |
| #define | VADC_G_CHCTR_BWDCH_Pos (28UL) |
| |
| #define | VADC_G_CHCTR_BWDCH_Msk (0x30000000UL) |
| |
| #define | VADC_G_CHCTR_BWDEN_Pos (30UL) |
| |
| #define | VADC_G_CHCTR_BWDEN_Msk (0x40000000UL) |
| |
| #define | VADC_G_RCR_DRCTR_Pos (16UL) |
| |
| #define | VADC_G_RCR_DRCTR_Msk (0xf0000UL) |
| |
| #define | VADC_G_RCR_DMM_Pos (20UL) |
| |
| #define | VADC_G_RCR_DMM_Msk (0x300000UL) |
| |
| #define | VADC_G_RCR_WFR_Pos (24UL) |
| |
| #define | VADC_G_RCR_WFR_Msk (0x1000000UL) |
| |
| #define | VADC_G_RCR_FEN_Pos (25UL) |
| |
| #define | VADC_G_RCR_FEN_Msk (0x6000000UL) |
| |
| #define | VADC_G_RCR_SRGEN_Pos (31UL) |
| |
| #define | VADC_G_RCR_SRGEN_Msk (0x80000000UL) |
| |
| #define | VADC_G_RES_RESULT_Pos (0UL) |
| |
| #define | VADC_G_RES_RESULT_Msk (0xffffUL) |
| |
| #define | VADC_G_RES_DRC_Pos (16UL) |
| |
| #define | VADC_G_RES_DRC_Msk (0xf0000UL) |
| |
| #define | VADC_G_RES_CHNR_Pos (20UL) |
| |
| #define | VADC_G_RES_CHNR_Msk (0x1f00000UL) |
| |
| #define | VADC_G_RES_EMUX_Pos (25UL) |
| |
| #define | VADC_G_RES_EMUX_Msk (0xe000000UL) |
| |
| #define | VADC_G_RES_CRS_Pos (28UL) |
| |
| #define | VADC_G_RES_CRS_Msk (0x30000000UL) |
| |
| #define | VADC_G_RES_FCR_Pos (30UL) |
| |
| #define | VADC_G_RES_FCR_Msk (0x40000000UL) |
| |
| #define | VADC_G_RES_VF_Pos (31UL) |
| |
| #define | VADC_G_RES_VF_Msk (0x80000000UL) |
| |
| #define | VADC_G_RESD_RESULT_Pos (0UL) |
| |
| #define | VADC_G_RESD_RESULT_Msk (0xffffUL) |
| |
| #define | VADC_G_RESD_DRC_Pos (16UL) |
| |
| #define | VADC_G_RESD_DRC_Msk (0xf0000UL) |
| |
| #define | VADC_G_RESD_CHNR_Pos (20UL) |
| |
| #define | VADC_G_RESD_CHNR_Msk (0x1f00000UL) |
| |
| #define | VADC_G_RESD_EMUX_Pos (25UL) |
| |
| #define | VADC_G_RESD_EMUX_Msk (0xe000000UL) |
| |
| #define | VADC_G_RESD_CRS_Pos (28UL) |
| |
| #define | VADC_G_RESD_CRS_Msk (0x30000000UL) |
| |
| #define | VADC_G_RESD_FCR_Pos (30UL) |
| |
| #define | VADC_G_RESD_FCR_Msk (0x40000000UL) |
| |
| #define | VADC_G_RESD_VF_Pos (31UL) |
| |
| #define | VADC_G_RESD_VF_Msk (0x80000000UL) |
| |
| #define | DSD_CLC_DISR_Pos (0UL) |
| |
| #define | DSD_CLC_DISR_Msk (0x1UL) |
| |
| #define | DSD_CLC_DISS_Pos (1UL) |
| |
| #define | DSD_CLC_DISS_Msk (0x2UL) |
| |
| #define | DSD_CLC_EDIS_Pos (3UL) |
| |
| #define | DSD_CLC_EDIS_Msk (0x8UL) |
| |
| #define | DSD_ID_MOD_REV_Pos (0UL) |
| |
| #define | DSD_ID_MOD_REV_Msk (0xffUL) |
| |
| #define | DSD_ID_MOD_TYPE_Pos (8UL) |
| |
| #define | DSD_ID_MOD_TYPE_Msk (0xff00UL) |
| |
| #define | DSD_ID_MOD_NUMBER_Pos (16UL) |
| |
| #define | DSD_ID_MOD_NUMBER_Msk (0xffff0000UL) |
| |
| #define | DSD_OCS_SUS_Pos (24UL) |
| |
| #define | DSD_OCS_SUS_Msk (0xf000000UL) |
| |
| #define | DSD_OCS_SUS_P_Pos (28UL) |
| |
| #define | DSD_OCS_SUS_P_Msk (0x10000000UL) |
| |
| #define | DSD_OCS_SUSSTA_Pos (29UL) |
| |
| #define | DSD_OCS_SUSSTA_Msk (0x20000000UL) |
| |
| #define | DSD_GLOBCFG_MCSEL_Pos (0UL) |
| |
| #define | DSD_GLOBCFG_MCSEL_Msk (0x7UL) |
| |
| #define | DSD_GLOBRC_CH0RUN_Pos (0UL) |
| |
| #define | DSD_GLOBRC_CH0RUN_Msk (0x1UL) |
| |
| #define | DSD_GLOBRC_CH1RUN_Pos (1UL) |
| |
| #define | DSD_GLOBRC_CH1RUN_Msk (0x2UL) |
| |
| #define | DSD_GLOBRC_CH2RUN_Pos (2UL) |
| |
| #define | DSD_GLOBRC_CH2RUN_Msk (0x4UL) |
| |
| #define | DSD_GLOBRC_CH3RUN_Pos (3UL) |
| |
| #define | DSD_GLOBRC_CH3RUN_Msk (0x8UL) |
| |
| #define | DSD_CGCFG_CGMOD_Pos (0UL) |
| |
| #define | DSD_CGCFG_CGMOD_Msk (0x3UL) |
| |
| #define | DSD_CGCFG_BREV_Pos (2UL) |
| |
| #define | DSD_CGCFG_BREV_Msk (0x4UL) |
| |
| #define | DSD_CGCFG_SIGPOL_Pos (3UL) |
| |
| #define | DSD_CGCFG_SIGPOL_Msk (0x8UL) |
| |
| #define | DSD_CGCFG_DIVCG_Pos (4UL) |
| |
| #define | DSD_CGCFG_DIVCG_Msk (0xf0UL) |
| |
| #define | DSD_CGCFG_RUN_Pos (15UL) |
| |
| #define | DSD_CGCFG_RUN_Msk (0x8000UL) |
| |
| #define | DSD_CGCFG_BITCOUNT_Pos (16UL) |
| |
| #define | DSD_CGCFG_BITCOUNT_Msk (0x1f0000UL) |
| |
| #define | DSD_CGCFG_STEPCOUNT_Pos (24UL) |
| |
| #define | DSD_CGCFG_STEPCOUNT_Msk (0xf000000UL) |
| |
| #define | DSD_CGCFG_STEPS_Pos (28UL) |
| |
| #define | DSD_CGCFG_STEPS_Msk (0x10000000UL) |
| |
| #define | DSD_CGCFG_STEPD_Pos (29UL) |
| |
| #define | DSD_CGCFG_STEPD_Msk (0x20000000UL) |
| |
| #define | DSD_CGCFG_SGNCG_Pos (30UL) |
| |
| #define | DSD_CGCFG_SGNCG_Msk (0x40000000UL) |
| |
| #define | DSD_EVFLAG_RESEV0_Pos (0UL) |
| |
| #define | DSD_EVFLAG_RESEV0_Msk (0x1UL) |
| |
| #define | DSD_EVFLAG_RESEV1_Pos (1UL) |
| |
| #define | DSD_EVFLAG_RESEV1_Msk (0x2UL) |
| |
| #define | DSD_EVFLAG_RESEV2_Pos (2UL) |
| |
| #define | DSD_EVFLAG_RESEV2_Msk (0x4UL) |
| |
| #define | DSD_EVFLAG_RESEV3_Pos (3UL) |
| |
| #define | DSD_EVFLAG_RESEV3_Msk (0x8UL) |
| |
| #define | DSD_EVFLAG_ALEV0_Pos (16UL) |
| |
| #define | DSD_EVFLAG_ALEV0_Msk (0x10000UL) |
| |
| #define | DSD_EVFLAG_ALEV1_Pos (17UL) |
| |
| #define | DSD_EVFLAG_ALEV1_Msk (0x20000UL) |
| |
| #define | DSD_EVFLAG_ALEV2_Pos (18UL) |
| |
| #define | DSD_EVFLAG_ALEV2_Msk (0x40000UL) |
| |
| #define | DSD_EVFLAG_ALEV3_Pos (19UL) |
| |
| #define | DSD_EVFLAG_ALEV3_Msk (0x80000UL) |
| |
| #define | DSD_EVFLAGCLR_RESEC0_Pos (0UL) |
| |
| #define | DSD_EVFLAGCLR_RESEC0_Msk (0x1UL) |
| |
| #define | DSD_EVFLAGCLR_RESEC1_Pos (1UL) |
| |
| #define | DSD_EVFLAGCLR_RESEC1_Msk (0x2UL) |
| |
| #define | DSD_EVFLAGCLR_RESEC2_Pos (2UL) |
| |
| #define | DSD_EVFLAGCLR_RESEC2_Msk (0x4UL) |
| |
| #define | DSD_EVFLAGCLR_RESEC3_Pos (3UL) |
| |
| #define | DSD_EVFLAGCLR_RESEC3_Msk (0x8UL) |
| |
| #define | DSD_EVFLAGCLR_ALEC0_Pos (16UL) |
| |
| #define | DSD_EVFLAGCLR_ALEC0_Msk (0x10000UL) |
| |
| #define | DSD_EVFLAGCLR_ALEC1_Pos (17UL) |
| |
| #define | DSD_EVFLAGCLR_ALEC1_Msk (0x20000UL) |
| |
| #define | DSD_EVFLAGCLR_ALEC2_Pos (18UL) |
| |
| #define | DSD_EVFLAGCLR_ALEC2_Msk (0x40000UL) |
| |
| #define | DSD_EVFLAGCLR_ALEC3_Pos (19UL) |
| |
| #define | DSD_EVFLAGCLR_ALEC3_Msk (0x80000UL) |
| |
| #define | DSD_CH_MODCFG_DIVM_Pos (16UL) |
| |
| #define | DSD_CH_MODCFG_DIVM_Msk (0xf0000UL) |
| |
| #define | DSD_CH_MODCFG_DWC_Pos (23UL) |
| |
| #define | DSD_CH_MODCFG_DWC_Msk (0x800000UL) |
| |
| #define | DSD_CH_DICFG_DSRC_Pos (0UL) |
| |
| #define | DSD_CH_DICFG_DSRC_Msk (0xfUL) |
| |
| #define | DSD_CH_DICFG_DSWC_Pos (7UL) |
| |
| #define | DSD_CH_DICFG_DSWC_Msk (0x80UL) |
| |
| #define | DSD_CH_DICFG_ITRMODE_Pos (8UL) |
| |
| #define | DSD_CH_DICFG_ITRMODE_Msk (0x300UL) |
| |
| #define | DSD_CH_DICFG_TSTRMODE_Pos (10UL) |
| |
| #define | DSD_CH_DICFG_TSTRMODE_Msk (0xc00UL) |
| |
| #define | DSD_CH_DICFG_TRSEL_Pos (12UL) |
| |
| #define | DSD_CH_DICFG_TRSEL_Msk (0x7000UL) |
| |
| #define | DSD_CH_DICFG_TRWC_Pos (15UL) |
| |
| #define | DSD_CH_DICFG_TRWC_Msk (0x8000UL) |
| |
| #define | DSD_CH_DICFG_CSRC_Pos (16UL) |
| |
| #define | DSD_CH_DICFG_CSRC_Msk (0xf0000UL) |
| |
| #define | DSD_CH_DICFG_STROBE_Pos (20UL) |
| |
| #define | DSD_CH_DICFG_STROBE_Msk (0xf00000UL) |
| |
| #define | DSD_CH_DICFG_SCWC_Pos (31UL) |
| |
| #define | DSD_CH_DICFG_SCWC_Msk (0x80000000UL) |
| |
| #define | DSD_CH_FCFGC_CFMDF_Pos (0UL) |
| |
| #define | DSD_CH_FCFGC_CFMDF_Msk (0xffUL) |
| |
| #define | DSD_CH_FCFGC_CFMC_Pos (8UL) |
| |
| #define | DSD_CH_FCFGC_CFMC_Msk (0x300UL) |
| |
| #define | DSD_CH_FCFGC_CFEN_Pos (10UL) |
| |
| #define | DSD_CH_FCFGC_CFEN_Msk (0x400UL) |
| |
| #define | DSD_CH_FCFGC_SRGM_Pos (14UL) |
| |
| #define | DSD_CH_FCFGC_SRGM_Msk (0xc000UL) |
| |
| #define | DSD_CH_FCFGC_CFMSV_Pos (16UL) |
| |
| #define | DSD_CH_FCFGC_CFMSV_Msk (0xff0000UL) |
| |
| #define | DSD_CH_FCFGC_CFMDCNT_Pos (24UL) |
| |
| #define | DSD_CH_FCFGC_CFMDCNT_Msk (0xff000000UL) |
| |
| #define | DSD_CH_FCFGA_CFADF_Pos (0UL) |
| |
| #define | DSD_CH_FCFGA_CFADF_Msk (0xffUL) |
| |
| #define | DSD_CH_FCFGA_CFAC_Pos (8UL) |
| |
| #define | DSD_CH_FCFGA_CFAC_Msk (0x300UL) |
| |
| #define | DSD_CH_FCFGA_SRGA_Pos (10UL) |
| |
| #define | DSD_CH_FCFGA_SRGA_Msk (0xc00UL) |
| |
| #define | DSD_CH_FCFGA_ESEL_Pos (12UL) |
| |
| #define | DSD_CH_FCFGA_ESEL_Msk (0x3000UL) |
| |
| #define | DSD_CH_FCFGA_EGT_Pos (14UL) |
| |
| #define | DSD_CH_FCFGA_EGT_Msk (0x4000UL) |
| |
| #define | DSD_CH_FCFGA_CFADCNT_Pos (24UL) |
| |
| #define | DSD_CH_FCFGA_CFADCNT_Msk (0xff000000UL) |
| |
| #define | DSD_CH_IWCTR_NVALCNT_Pos (0UL) |
| |
| #define | DSD_CH_IWCTR_NVALCNT_Msk (0x3fUL) |
| |
| #define | DSD_CH_IWCTR_INTEN_Pos (7UL) |
| |
| #define | DSD_CH_IWCTR_INTEN_Msk (0x80UL) |
| |
| #define | DSD_CH_IWCTR_REPCNT_Pos (8UL) |
| |
| #define | DSD_CH_IWCTR_REPCNT_Msk (0xf00UL) |
| |
| #define | DSD_CH_IWCTR_REPVAL_Pos (12UL) |
| |
| #define | DSD_CH_IWCTR_REPVAL_Msk (0xf000UL) |
| |
| #define | DSD_CH_IWCTR_NVALDIS_Pos (16UL) |
| |
| #define | DSD_CH_IWCTR_NVALDIS_Msk (0x3f0000UL) |
| |
| #define | DSD_CH_IWCTR_IWS_Pos (23UL) |
| |
| #define | DSD_CH_IWCTR_IWS_Msk (0x800000UL) |
| |
| #define | DSD_CH_IWCTR_NVALINT_Pos (24UL) |
| |
| #define | DSD_CH_IWCTR_NVALINT_Msk (0x3f000000UL) |
| |
| #define | DSD_CH_BOUNDSEL_BOUNDARYL_Pos (0UL) |
| |
| #define | DSD_CH_BOUNDSEL_BOUNDARYL_Msk (0xffffUL) |
| |
| #define | DSD_CH_BOUNDSEL_BOUNDARYU_Pos (16UL) |
| |
| #define | DSD_CH_BOUNDSEL_BOUNDARYU_Msk (0xffff0000UL) |
| |
| #define | DSD_CH_RESM_RESULT_Pos (0UL) |
| |
| #define | DSD_CH_RESM_RESULT_Msk (0xffffUL) |
| |
| #define | DSD_CH_OFFM_OFFSET_Pos (0UL) |
| |
| #define | DSD_CH_OFFM_OFFSET_Msk (0xffffUL) |
| |
| #define | DSD_CH_RESA_RESULT_Pos (0UL) |
| |
| #define | DSD_CH_RESA_RESULT_Msk (0xffffUL) |
| |
| #define | DSD_CH_TSTMP_RESULT_Pos (0UL) |
| |
| #define | DSD_CH_TSTMP_RESULT_Msk (0xffffUL) |
| |
| #define | DSD_CH_TSTMP_CFMDCNT_Pos (16UL) |
| |
| #define | DSD_CH_TSTMP_CFMDCNT_Msk (0xff0000UL) |
| |
| #define | DSD_CH_TSTMP_NVALCNT_Pos (24UL) |
| |
| #define | DSD_CH_TSTMP_NVALCNT_Msk (0x3f000000UL) |
| |
| #define | DSD_CH_CGSYNC_SDCOUNT_Pos (0UL) |
| |
| #define | DSD_CH_CGSYNC_SDCOUNT_Msk (0xffUL) |
| |
| #define | DSD_CH_CGSYNC_SDCAP_Pos (8UL) |
| |
| #define | DSD_CH_CGSYNC_SDCAP_Msk (0xff00UL) |
| |
| #define | DSD_CH_CGSYNC_SDPOS_Pos (16UL) |
| |
| #define | DSD_CH_CGSYNC_SDPOS_Msk (0xff0000UL) |
| |
| #define | DSD_CH_CGSYNC_SDNEG_Pos (24UL) |
| |
| #define | DSD_CH_CGSYNC_SDNEG_Msk (0xff000000UL) |
| |
| #define | DSD_CH_RECTCFG_RFEN_Pos (0UL) |
| |
| #define | DSD_CH_RECTCFG_RFEN_Msk (0x1UL) |
| |
| #define | DSD_CH_RECTCFG_SSRC_Pos (4UL) |
| |
| #define | DSD_CH_RECTCFG_SSRC_Msk (0x30UL) |
| |
| #define | DSD_CH_RECTCFG_SDVAL_Pos (15UL) |
| |
| #define | DSD_CH_RECTCFG_SDVAL_Msk (0x8000UL) |
| |
| #define | DSD_CH_RECTCFG_SGNCS_Pos (30UL) |
| |
| #define | DSD_CH_RECTCFG_SGNCS_Msk (0x40000000UL) |
| |
| #define | DSD_CH_RECTCFG_SGND_Pos (31UL) |
| |
| #define | DSD_CH_RECTCFG_SGND_Msk (0x80000000UL) |
| |
| #define | DAC_ID_MODR_Pos (0UL) |
| |
| #define | DAC_ID_MODR_Msk (0xffUL) |
| |
| #define | DAC_ID_MODT_Pos (8UL) |
| |
| #define | DAC_ID_MODT_Msk (0xff00UL) |
| |
| #define | DAC_ID_MODN_Pos (16UL) |
| |
| #define | DAC_ID_MODN_Msk (0xffff0000UL) |
| |
| #define | DAC_DAC0CFG0_FREQ_Pos (0UL) |
| |
| #define | DAC_DAC0CFG0_FREQ_Msk (0xfffffUL) |
| |
| #define | DAC_DAC0CFG0_MODE_Pos (20UL) |
| |
| #define | DAC_DAC0CFG0_MODE_Msk (0x700000UL) |
| |
| #define | DAC_DAC0CFG0_SIGN_Pos (23UL) |
| |
| #define | DAC_DAC0CFG0_SIGN_Msk (0x800000UL) |
| |
| #define | DAC_DAC0CFG0_FIFOIND_Pos (24UL) |
| |
| #define | DAC_DAC0CFG0_FIFOIND_Msk (0x3000000UL) |
| |
| #define | DAC_DAC0CFG0_FIFOEMP_Pos (26UL) |
| |
| #define | DAC_DAC0CFG0_FIFOEMP_Msk (0x4000000UL) |
| |
| #define | DAC_DAC0CFG0_FIFOFUL_Pos (27UL) |
| |
| #define | DAC_DAC0CFG0_FIFOFUL_Msk (0x8000000UL) |
| |
| #define | DAC_DAC0CFG0_NEGATE_Pos (28UL) |
| |
| #define | DAC_DAC0CFG0_NEGATE_Msk (0x10000000UL) |
| |
| #define | DAC_DAC0CFG0_SIGNEN_Pos (29UL) |
| |
| #define | DAC_DAC0CFG0_SIGNEN_Msk (0x20000000UL) |
| |
| #define | DAC_DAC0CFG0_SREN_Pos (30UL) |
| |
| #define | DAC_DAC0CFG0_SREN_Msk (0x40000000UL) |
| |
| #define | DAC_DAC0CFG0_RUN_Pos (31UL) |
| |
| #define | DAC_DAC0CFG0_RUN_Msk (0x80000000UL) |
| |
| #define | DAC_DAC0CFG1_SCALE_Pos (0UL) |
| |
| #define | DAC_DAC0CFG1_SCALE_Msk (0x7UL) |
| |
| #define | DAC_DAC0CFG1_MULDIV_Pos (3UL) |
| |
| #define | DAC_DAC0CFG1_MULDIV_Msk (0x8UL) |
| |
| #define | DAC_DAC0CFG1_OFFS_Pos (4UL) |
| |
| #define | DAC_DAC0CFG1_OFFS_Msk (0xff0UL) |
| |
| #define | DAC_DAC0CFG1_TRIGSEL_Pos (12UL) |
| |
| #define | DAC_DAC0CFG1_TRIGSEL_Msk (0x7000UL) |
| |
| #define | DAC_DAC0CFG1_DATMOD_Pos (15UL) |
| |
| #define | DAC_DAC0CFG1_DATMOD_Msk (0x8000UL) |
| |
| #define | DAC_DAC0CFG1_SWTRIG_Pos (16UL) |
| |
| #define | DAC_DAC0CFG1_SWTRIG_Msk (0x10000UL) |
| |
| #define | DAC_DAC0CFG1_TRIGMOD_Pos (17UL) |
| |
| #define | DAC_DAC0CFG1_TRIGMOD_Msk (0x60000UL) |
| |
| #define | DAC_DAC0CFG1_ANACFG_Pos (19UL) |
| |
| #define | DAC_DAC0CFG1_ANACFG_Msk (0xf80000UL) |
| |
| #define | DAC_DAC0CFG1_ANAEN_Pos (24UL) |
| |
| #define | DAC_DAC0CFG1_ANAEN_Msk (0x1000000UL) |
| |
| #define | DAC_DAC0CFG1_REFCFGL_Pos (28UL) |
| |
| #define | DAC_DAC0CFG1_REFCFGL_Msk (0xf0000000UL) |
| |
| #define | DAC_DAC1CFG0_FREQ_Pos (0UL) |
| |
| #define | DAC_DAC1CFG0_FREQ_Msk (0xfffffUL) |
| |
| #define | DAC_DAC1CFG0_MODE_Pos (20UL) |
| |
| #define | DAC_DAC1CFG0_MODE_Msk (0x700000UL) |
| |
| #define | DAC_DAC1CFG0_SIGN_Pos (23UL) |
| |
| #define | DAC_DAC1CFG0_SIGN_Msk (0x800000UL) |
| |
| #define | DAC_DAC1CFG0_FIFOIND_Pos (24UL) |
| |
| #define | DAC_DAC1CFG0_FIFOIND_Msk (0x3000000UL) |
| |
| #define | DAC_DAC1CFG0_FIFOEMP_Pos (26UL) |
| |
| #define | DAC_DAC1CFG0_FIFOEMP_Msk (0x4000000UL) |
| |
| #define | DAC_DAC1CFG0_FIFOFUL_Pos (27UL) |
| |
| #define | DAC_DAC1CFG0_FIFOFUL_Msk (0x8000000UL) |
| |
| #define | DAC_DAC1CFG0_NEGATE_Pos (28UL) |
| |
| #define | DAC_DAC1CFG0_NEGATE_Msk (0x10000000UL) |
| |
| #define | DAC_DAC1CFG0_SIGNEN_Pos (29UL) |
| |
| #define | DAC_DAC1CFG0_SIGNEN_Msk (0x20000000UL) |
| |
| #define | DAC_DAC1CFG0_SREN_Pos (30UL) |
| |
| #define | DAC_DAC1CFG0_SREN_Msk (0x40000000UL) |
| |
| #define | DAC_DAC1CFG0_RUN_Pos (31UL) |
| |
| #define | DAC_DAC1CFG0_RUN_Msk (0x80000000UL) |
| |
| #define | DAC_DAC1CFG1_SCALE_Pos (0UL) |
| |
| #define | DAC_DAC1CFG1_SCALE_Msk (0x7UL) |
| |
| #define | DAC_DAC1CFG1_MULDIV_Pos (3UL) |
| |
| #define | DAC_DAC1CFG1_MULDIV_Msk (0x8UL) |
| |
| #define | DAC_DAC1CFG1_OFFS_Pos (4UL) |
| |
| #define | DAC_DAC1CFG1_OFFS_Msk (0xff0UL) |
| |
| #define | DAC_DAC1CFG1_TRIGSEL_Pos (12UL) |
| |
| #define | DAC_DAC1CFG1_TRIGSEL_Msk (0x7000UL) |
| |
| #define | DAC_DAC1CFG1_SWTRIG_Pos (16UL) |
| |
| #define | DAC_DAC1CFG1_SWTRIG_Msk (0x10000UL) |
| |
| #define | DAC_DAC1CFG1_TRIGMOD_Pos (17UL) |
| |
| #define | DAC_DAC1CFG1_TRIGMOD_Msk (0x60000UL) |
| |
| #define | DAC_DAC1CFG1_ANACFG_Pos (19UL) |
| |
| #define | DAC_DAC1CFG1_ANACFG_Msk (0xf80000UL) |
| |
| #define | DAC_DAC1CFG1_ANAEN_Pos (24UL) |
| |
| #define | DAC_DAC1CFG1_ANAEN_Msk (0x1000000UL) |
| |
| #define | DAC_DAC1CFG1_REFCFGH_Pos (28UL) |
| |
| #define | DAC_DAC1CFG1_REFCFGH_Msk (0xf0000000UL) |
| |
| #define | DAC_DAC0DATA_DATA0_Pos (0UL) |
| |
| #define | DAC_DAC0DATA_DATA0_Msk (0xfffUL) |
| |
| #define | DAC_DAC1DATA_DATA1_Pos (0UL) |
| |
| #define | DAC_DAC1DATA_DATA1_Msk (0xfffUL) |
| |
| #define | DAC_DAC01DATA_DATA0_Pos (0UL) |
| |
| #define | DAC_DAC01DATA_DATA0_Msk (0xfffUL) |
| |
| #define | DAC_DAC01DATA_DATA1_Pos (16UL) |
| |
| #define | DAC_DAC01DATA_DATA1_Msk (0xfff0000UL) |
| |
| #define | DAC_DAC0PATL_PAT0_Pos (0UL) |
| |
| #define | DAC_DAC0PATL_PAT0_Msk (0x1fUL) |
| |
| #define | DAC_DAC0PATL_PAT1_Pos (5UL) |
| |
| #define | DAC_DAC0PATL_PAT1_Msk (0x3e0UL) |
| |
| #define | DAC_DAC0PATL_PAT2_Pos (10UL) |
| |
| #define | DAC_DAC0PATL_PAT2_Msk (0x7c00UL) |
| |
| #define | DAC_DAC0PATL_PAT3_Pos (15UL) |
| |
| #define | DAC_DAC0PATL_PAT3_Msk (0xf8000UL) |
| |
| #define | DAC_DAC0PATL_PAT4_Pos (20UL) |
| |
| #define | DAC_DAC0PATL_PAT4_Msk (0x1f00000UL) |
| |
| #define | DAC_DAC0PATL_PAT5_Pos (25UL) |
| |
| #define | DAC_DAC0PATL_PAT5_Msk (0x3e000000UL) |
| |
| #define | DAC_DAC0PATH_PAT6_Pos (0UL) |
| |
| #define | DAC_DAC0PATH_PAT6_Msk (0x1fUL) |
| |
| #define | DAC_DAC0PATH_PAT7_Pos (5UL) |
| |
| #define | DAC_DAC0PATH_PAT7_Msk (0x3e0UL) |
| |
| #define | DAC_DAC0PATH_PAT8_Pos (10UL) |
| |
| #define | DAC_DAC0PATH_PAT8_Msk (0x7c00UL) |
| |
| #define | DAC_DAC1PATL_PAT0_Pos (0UL) |
| |
| #define | DAC_DAC1PATL_PAT0_Msk (0x1fUL) |
| |
| #define | DAC_DAC1PATL_PAT1_Pos (5UL) |
| |
| #define | DAC_DAC1PATL_PAT1_Msk (0x3e0UL) |
| |
| #define | DAC_DAC1PATL_PAT2_Pos (10UL) |
| |
| #define | DAC_DAC1PATL_PAT2_Msk (0x7c00UL) |
| |
| #define | DAC_DAC1PATL_PAT3_Pos (15UL) |
| |
| #define | DAC_DAC1PATL_PAT3_Msk (0xf8000UL) |
| |
| #define | DAC_DAC1PATL_PAT4_Pos (20UL) |
| |
| #define | DAC_DAC1PATL_PAT4_Msk (0x1f00000UL) |
| |
| #define | DAC_DAC1PATL_PAT5_Pos (25UL) |
| |
| #define | DAC_DAC1PATL_PAT5_Msk (0x3e000000UL) |
| |
| #define | DAC_DAC1PATH_PAT6_Pos (0UL) |
| |
| #define | DAC_DAC1PATH_PAT6_Msk (0x1fUL) |
| |
| #define | DAC_DAC1PATH_PAT7_Pos (5UL) |
| |
| #define | DAC_DAC1PATH_PAT7_Msk (0x3e0UL) |
| |
| #define | DAC_DAC1PATH_PAT8_Pos (10UL) |
| |
| #define | DAC_DAC1PATH_PAT8_Msk (0x7c00UL) |
| |
| #define | CCU4_GCTRL_PRBC_Pos (0UL) |
| |
| #define | CCU4_GCTRL_PRBC_Msk (0x7UL) |
| |
| #define | CCU4_GCTRL_PCIS_Pos (4UL) |
| |
| #define | CCU4_GCTRL_PCIS_Msk (0x30UL) |
| |
| #define | CCU4_GCTRL_SUSCFG_Pos (8UL) |
| |
| #define | CCU4_GCTRL_SUSCFG_Msk (0x300UL) |
| |
| #define | CCU4_GCTRL_MSE0_Pos (10UL) |
| |
| #define | CCU4_GCTRL_MSE0_Msk (0x400UL) |
| |
| #define | CCU4_GCTRL_MSE1_Pos (11UL) |
| |
| #define | CCU4_GCTRL_MSE1_Msk (0x800UL) |
| |
| #define | CCU4_GCTRL_MSE2_Pos (12UL) |
| |
| #define | CCU4_GCTRL_MSE2_Msk (0x1000UL) |
| |
| #define | CCU4_GCTRL_MSE3_Pos (13UL) |
| |
| #define | CCU4_GCTRL_MSE3_Msk (0x2000UL) |
| |
| #define | CCU4_GCTRL_MSDE_Pos (14UL) |
| |
| #define | CCU4_GCTRL_MSDE_Msk (0xc000UL) |
| |
| #define | CCU4_GSTAT_S0I_Pos (0UL) |
| |
| #define | CCU4_GSTAT_S0I_Msk (0x1UL) |
| |
| #define | CCU4_GSTAT_S1I_Pos (1UL) |
| |
| #define | CCU4_GSTAT_S1I_Msk (0x2UL) |
| |
| #define | CCU4_GSTAT_S2I_Pos (2UL) |
| |
| #define | CCU4_GSTAT_S2I_Msk (0x4UL) |
| |
| #define | CCU4_GSTAT_S3I_Pos (3UL) |
| |
| #define | CCU4_GSTAT_S3I_Msk (0x8UL) |
| |
| #define | CCU4_GSTAT_PRB_Pos (8UL) |
| |
| #define | CCU4_GSTAT_PRB_Msk (0x100UL) |
| |
| #define | CCU4_GIDLS_SS0I_Pos (0UL) |
| |
| #define | CCU4_GIDLS_SS0I_Msk (0x1UL) |
| |
| #define | CCU4_GIDLS_SS1I_Pos (1UL) |
| |
| #define | CCU4_GIDLS_SS1I_Msk (0x2UL) |
| |
| #define | CCU4_GIDLS_SS2I_Pos (2UL) |
| |
| #define | CCU4_GIDLS_SS2I_Msk (0x4UL) |
| |
| #define | CCU4_GIDLS_SS3I_Pos (3UL) |
| |
| #define | CCU4_GIDLS_SS3I_Msk (0x8UL) |
| |
| #define | CCU4_GIDLS_CPRB_Pos (8UL) |
| |
| #define | CCU4_GIDLS_CPRB_Msk (0x100UL) |
| |
| #define | CCU4_GIDLS_PSIC_Pos (9UL) |
| |
| #define | CCU4_GIDLS_PSIC_Msk (0x200UL) |
| |
| #define | CCU4_GIDLC_CS0I_Pos (0UL) |
| |
| #define | CCU4_GIDLC_CS0I_Msk (0x1UL) |
| |
| #define | CCU4_GIDLC_CS1I_Pos (1UL) |
| |
| #define | CCU4_GIDLC_CS1I_Msk (0x2UL) |
| |
| #define | CCU4_GIDLC_CS2I_Pos (2UL) |
| |
| #define | CCU4_GIDLC_CS2I_Msk (0x4UL) |
| |
| #define | CCU4_GIDLC_CS3I_Pos (3UL) |
| |
| #define | CCU4_GIDLC_CS3I_Msk (0x8UL) |
| |
| #define | CCU4_GIDLC_SPRB_Pos (8UL) |
| |
| #define | CCU4_GIDLC_SPRB_Msk (0x100UL) |
| |
| #define | CCU4_GCSS_S0SE_Pos (0UL) |
| |
| #define | CCU4_GCSS_S0SE_Msk (0x1UL) |
| |
| #define | CCU4_GCSS_S0DSE_Pos (1UL) |
| |
| #define | CCU4_GCSS_S0DSE_Msk (0x2UL) |
| |
| #define | CCU4_GCSS_S0PSE_Pos (2UL) |
| |
| #define | CCU4_GCSS_S0PSE_Msk (0x4UL) |
| |
| #define | CCU4_GCSS_S1SE_Pos (4UL) |
| |
| #define | CCU4_GCSS_S1SE_Msk (0x10UL) |
| |
| #define | CCU4_GCSS_S1DSE_Pos (5UL) |
| |
| #define | CCU4_GCSS_S1DSE_Msk (0x20UL) |
| |
| #define | CCU4_GCSS_S1PSE_Pos (6UL) |
| |
| #define | CCU4_GCSS_S1PSE_Msk (0x40UL) |
| |
| #define | CCU4_GCSS_S2SE_Pos (8UL) |
| |
| #define | CCU4_GCSS_S2SE_Msk (0x100UL) |
| |
| #define | CCU4_GCSS_S2DSE_Pos (9UL) |
| |
| #define | CCU4_GCSS_S2DSE_Msk (0x200UL) |
| |
| #define | CCU4_GCSS_S2PSE_Pos (10UL) |
| |
| #define | CCU4_GCSS_S2PSE_Msk (0x400UL) |
| |
| #define | CCU4_GCSS_S3SE_Pos (12UL) |
| |
| #define | CCU4_GCSS_S3SE_Msk (0x1000UL) |
| |
| #define | CCU4_GCSS_S3DSE_Pos (13UL) |
| |
| #define | CCU4_GCSS_S3DSE_Msk (0x2000UL) |
| |
| #define | CCU4_GCSS_S3PSE_Pos (14UL) |
| |
| #define | CCU4_GCSS_S3PSE_Msk (0x4000UL) |
| |
| #define | CCU4_GCSS_S0STS_Pos (16UL) |
| |
| #define | CCU4_GCSS_S0STS_Msk (0x10000UL) |
| |
| #define | CCU4_GCSS_S1STS_Pos (17UL) |
| |
| #define | CCU4_GCSS_S1STS_Msk (0x20000UL) |
| |
| #define | CCU4_GCSS_S2STS_Pos (18UL) |
| |
| #define | CCU4_GCSS_S2STS_Msk (0x40000UL) |
| |
| #define | CCU4_GCSS_S3STS_Pos (19UL) |
| |
| #define | CCU4_GCSS_S3STS_Msk (0x80000UL) |
| |
| #define | CCU4_GCSC_S0SC_Pos (0UL) |
| |
| #define | CCU4_GCSC_S0SC_Msk (0x1UL) |
| |
| #define | CCU4_GCSC_S0DSC_Pos (1UL) |
| |
| #define | CCU4_GCSC_S0DSC_Msk (0x2UL) |
| |
| #define | CCU4_GCSC_S0PSC_Pos (2UL) |
| |
| #define | CCU4_GCSC_S0PSC_Msk (0x4UL) |
| |
| #define | CCU4_GCSC_S1SC_Pos (4UL) |
| |
| #define | CCU4_GCSC_S1SC_Msk (0x10UL) |
| |
| #define | CCU4_GCSC_S1DSC_Pos (5UL) |
| |
| #define | CCU4_GCSC_S1DSC_Msk (0x20UL) |
| |
| #define | CCU4_GCSC_S1PSC_Pos (6UL) |
| |
| #define | CCU4_GCSC_S1PSC_Msk (0x40UL) |
| |
| #define | CCU4_GCSC_S2SC_Pos (8UL) |
| |
| #define | CCU4_GCSC_S2SC_Msk (0x100UL) |
| |
| #define | CCU4_GCSC_S2DSC_Pos (9UL) |
| |
| #define | CCU4_GCSC_S2DSC_Msk (0x200UL) |
| |
| #define | CCU4_GCSC_S2PSC_Pos (10UL) |
| |
| #define | CCU4_GCSC_S2PSC_Msk (0x400UL) |
| |
| #define | CCU4_GCSC_S3SC_Pos (12UL) |
| |
| #define | CCU4_GCSC_S3SC_Msk (0x1000UL) |
| |
| #define | CCU4_GCSC_S3DSC_Pos (13UL) |
| |
| #define | CCU4_GCSC_S3DSC_Msk (0x2000UL) |
| |
| #define | CCU4_GCSC_S3PSC_Pos (14UL) |
| |
| #define | CCU4_GCSC_S3PSC_Msk (0x4000UL) |
| |
| #define | CCU4_GCSC_S0STC_Pos (16UL) |
| |
| #define | CCU4_GCSC_S0STC_Msk (0x10000UL) |
| |
| #define | CCU4_GCSC_S1STC_Pos (17UL) |
| |
| #define | CCU4_GCSC_S1STC_Msk (0x20000UL) |
| |
| #define | CCU4_GCSC_S2STC_Pos (18UL) |
| |
| #define | CCU4_GCSC_S2STC_Msk (0x40000UL) |
| |
| #define | CCU4_GCSC_S3STC_Pos (19UL) |
| |
| #define | CCU4_GCSC_S3STC_Msk (0x80000UL) |
| |
| #define | CCU4_GCST_S0SS_Pos (0UL) |
| |
| #define | CCU4_GCST_S0SS_Msk (0x1UL) |
| |
| #define | CCU4_GCST_S0DSS_Pos (1UL) |
| |
| #define | CCU4_GCST_S0DSS_Msk (0x2UL) |
| |
| #define | CCU4_GCST_S0PSS_Pos (2UL) |
| |
| #define | CCU4_GCST_S0PSS_Msk (0x4UL) |
| |
| #define | CCU4_GCST_S1SS_Pos (4UL) |
| |
| #define | CCU4_GCST_S1SS_Msk (0x10UL) |
| |
| #define | CCU4_GCST_S1DSS_Pos (5UL) |
| |
| #define | CCU4_GCST_S1DSS_Msk (0x20UL) |
| |
| #define | CCU4_GCST_S1PSS_Pos (6UL) |
| |
| #define | CCU4_GCST_S1PSS_Msk (0x40UL) |
| |
| #define | CCU4_GCST_S2SS_Pos (8UL) |
| |
| #define | CCU4_GCST_S2SS_Msk (0x100UL) |
| |
| #define | CCU4_GCST_S2DSS_Pos (9UL) |
| |
| #define | CCU4_GCST_S2DSS_Msk (0x200UL) |
| |
| #define | CCU4_GCST_S2PSS_Pos (10UL) |
| |
| #define | CCU4_GCST_S2PSS_Msk (0x400UL) |
| |
| #define | CCU4_GCST_S3SS_Pos (12UL) |
| |
| #define | CCU4_GCST_S3SS_Msk (0x1000UL) |
| |
| #define | CCU4_GCST_S3DSS_Pos (13UL) |
| |
| #define | CCU4_GCST_S3DSS_Msk (0x2000UL) |
| |
| #define | CCU4_GCST_S3PSS_Pos (14UL) |
| |
| #define | CCU4_GCST_S3PSS_Msk (0x4000UL) |
| |
| #define | CCU4_GCST_CC40ST_Pos (16UL) |
| |
| #define | CCU4_GCST_CC40ST_Msk (0x10000UL) |
| |
| #define | CCU4_GCST_CC41ST_Pos (17UL) |
| |
| #define | CCU4_GCST_CC41ST_Msk (0x20000UL) |
| |
| #define | CCU4_GCST_CC42ST_Pos (18UL) |
| |
| #define | CCU4_GCST_CC42ST_Msk (0x40000UL) |
| |
| #define | CCU4_GCST_CC43ST_Pos (19UL) |
| |
| #define | CCU4_GCST_CC43ST_Msk (0x80000UL) |
| |
| #define | CCU4_MIDR_MODR_Pos (0UL) |
| |
| #define | CCU4_MIDR_MODR_Msk (0xffUL) |
| |
| #define | CCU4_MIDR_MODT_Pos (8UL) |
| |
| #define | CCU4_MIDR_MODT_Msk (0xff00UL) |
| |
| #define | CCU4_MIDR_MODN_Pos (16UL) |
| |
| #define | CCU4_MIDR_MODN_Msk (0xffff0000UL) |
| |
| #define | CCU4_CC4_INS_EV0IS_Pos (0UL) |
| |
| #define | CCU4_CC4_INS_EV0IS_Msk (0xfUL) |
| |
| #define | CCU4_CC4_INS_EV1IS_Pos (4UL) |
| |
| #define | CCU4_CC4_INS_EV1IS_Msk (0xf0UL) |
| |
| #define | CCU4_CC4_INS_EV2IS_Pos (8UL) |
| |
| #define | CCU4_CC4_INS_EV2IS_Msk (0xf00UL) |
| |
| #define | CCU4_CC4_INS_EV0EM_Pos (16UL) |
| |
| #define | CCU4_CC4_INS_EV0EM_Msk (0x30000UL) |
| |
| #define | CCU4_CC4_INS_EV1EM_Pos (18UL) |
| |
| #define | CCU4_CC4_INS_EV1EM_Msk (0xc0000UL) |
| |
| #define | CCU4_CC4_INS_EV2EM_Pos (20UL) |
| |
| #define | CCU4_CC4_INS_EV2EM_Msk (0x300000UL) |
| |
| #define | CCU4_CC4_INS_EV0LM_Pos (22UL) |
| |
| #define | CCU4_CC4_INS_EV0LM_Msk (0x400000UL) |
| |
| #define | CCU4_CC4_INS_EV1LM_Pos (23UL) |
| |
| #define | CCU4_CC4_INS_EV1LM_Msk (0x800000UL) |
| |
| #define | CCU4_CC4_INS_EV2LM_Pos (24UL) |
| |
| #define | CCU4_CC4_INS_EV2LM_Msk (0x1000000UL) |
| |
| #define | CCU4_CC4_INS_LPF0M_Pos (25UL) |
| |
| #define | CCU4_CC4_INS_LPF0M_Msk (0x6000000UL) |
| |
| #define | CCU4_CC4_INS_LPF1M_Pos (27UL) |
| |
| #define | CCU4_CC4_INS_LPF1M_Msk (0x18000000UL) |
| |
| #define | CCU4_CC4_INS_LPF2M_Pos (29UL) |
| |
| #define | CCU4_CC4_INS_LPF2M_Msk (0x60000000UL) |
| |
| #define | CCU4_CC4_CMC_STRTS_Pos (0UL) |
| |
| #define | CCU4_CC4_CMC_STRTS_Msk (0x3UL) |
| |
| #define | CCU4_CC4_CMC_ENDS_Pos (2UL) |
| |
| #define | CCU4_CC4_CMC_ENDS_Msk (0xcUL) |
| |
| #define | CCU4_CC4_CMC_CAP0S_Pos (4UL) |
| |
| #define | CCU4_CC4_CMC_CAP0S_Msk (0x30UL) |
| |
| #define | CCU4_CC4_CMC_CAP1S_Pos (6UL) |
| |
| #define | CCU4_CC4_CMC_CAP1S_Msk (0xc0UL) |
| |
| #define | CCU4_CC4_CMC_GATES_Pos (8UL) |
| |
| #define | CCU4_CC4_CMC_GATES_Msk (0x300UL) |
| |
| #define | CCU4_CC4_CMC_UDS_Pos (10UL) |
| |
| #define | CCU4_CC4_CMC_UDS_Msk (0xc00UL) |
| |
| #define | CCU4_CC4_CMC_LDS_Pos (12UL) |
| |
| #define | CCU4_CC4_CMC_LDS_Msk (0x3000UL) |
| |
| #define | CCU4_CC4_CMC_CNTS_Pos (14UL) |
| |
| #define | CCU4_CC4_CMC_CNTS_Msk (0xc000UL) |
| |
| #define | CCU4_CC4_CMC_OFS_Pos (16UL) |
| |
| #define | CCU4_CC4_CMC_OFS_Msk (0x10000UL) |
| |
| #define | CCU4_CC4_CMC_TS_Pos (17UL) |
| |
| #define | CCU4_CC4_CMC_TS_Msk (0x20000UL) |
| |
| #define | CCU4_CC4_CMC_MOS_Pos (18UL) |
| |
| #define | CCU4_CC4_CMC_MOS_Msk (0xc0000UL) |
| |
| #define | CCU4_CC4_CMC_TCE_Pos (20UL) |
| |
| #define | CCU4_CC4_CMC_TCE_Msk (0x100000UL) |
| |
| #define | CCU4_CC4_TCST_TRB_Pos (0UL) |
| |
| #define | CCU4_CC4_TCST_TRB_Msk (0x1UL) |
| |
| #define | CCU4_CC4_TCST_CDIR_Pos (1UL) |
| |
| #define | CCU4_CC4_TCST_CDIR_Msk (0x2UL) |
| |
| #define | CCU4_CC4_TCSET_TRBS_Pos (0UL) |
| |
| #define | CCU4_CC4_TCSET_TRBS_Msk (0x1UL) |
| |
| #define | CCU4_CC4_TCCLR_TRBC_Pos (0UL) |
| |
| #define | CCU4_CC4_TCCLR_TRBC_Msk (0x1UL) |
| |
| #define | CCU4_CC4_TCCLR_TCC_Pos (1UL) |
| |
| #define | CCU4_CC4_TCCLR_TCC_Msk (0x2UL) |
| |
| #define | CCU4_CC4_TCCLR_DITC_Pos (2UL) |
| |
| #define | CCU4_CC4_TCCLR_DITC_Msk (0x4UL) |
| |
| #define | CCU4_CC4_TC_TCM_Pos (0UL) |
| |
| #define | CCU4_CC4_TC_TCM_Msk (0x1UL) |
| |
| #define | CCU4_CC4_TC_TSSM_Pos (1UL) |
| |
| #define | CCU4_CC4_TC_TSSM_Msk (0x2UL) |
| |
| #define | CCU4_CC4_TC_CLST_Pos (2UL) |
| |
| #define | CCU4_CC4_TC_CLST_Msk (0x4UL) |
| |
| #define | CCU4_CC4_TC_CMOD_Pos (3UL) |
| |
| #define | CCU4_CC4_TC_CMOD_Msk (0x8UL) |
| |
| #define | CCU4_CC4_TC_ECM_Pos (4UL) |
| |
| #define | CCU4_CC4_TC_ECM_Msk (0x10UL) |
| |
| #define | CCU4_CC4_TC_CAPC_Pos (5UL) |
| |
| #define | CCU4_CC4_TC_CAPC_Msk (0x60UL) |
| |
| #define | CCU4_CC4_TC_ENDM_Pos (8UL) |
| |
| #define | CCU4_CC4_TC_ENDM_Msk (0x300UL) |
| |
| #define | CCU4_CC4_TC_STRM_Pos (10UL) |
| |
| #define | CCU4_CC4_TC_STRM_Msk (0x400UL) |
| |
| #define | CCU4_CC4_TC_SCE_Pos (11UL) |
| |
| #define | CCU4_CC4_TC_SCE_Msk (0x800UL) |
| |
| #define | CCU4_CC4_TC_CCS_Pos (12UL) |
| |
| #define | CCU4_CC4_TC_CCS_Msk (0x1000UL) |
| |
| #define | CCU4_CC4_TC_DITHE_Pos (13UL) |
| |
| #define | CCU4_CC4_TC_DITHE_Msk (0x6000UL) |
| |
| #define | CCU4_CC4_TC_DIM_Pos (15UL) |
| |
| #define | CCU4_CC4_TC_DIM_Msk (0x8000UL) |
| |
| #define | CCU4_CC4_TC_FPE_Pos (16UL) |
| |
| #define | CCU4_CC4_TC_FPE_Msk (0x10000UL) |
| |
| #define | CCU4_CC4_TC_TRAPE_Pos (17UL) |
| |
| #define | CCU4_CC4_TC_TRAPE_Msk (0x20000UL) |
| |
| #define | CCU4_CC4_TC_TRPSE_Pos (21UL) |
| |
| #define | CCU4_CC4_TC_TRPSE_Msk (0x200000UL) |
| |
| #define | CCU4_CC4_TC_TRPSW_Pos (22UL) |
| |
| #define | CCU4_CC4_TC_TRPSW_Msk (0x400000UL) |
| |
| #define | CCU4_CC4_TC_EMS_Pos (23UL) |
| |
| #define | CCU4_CC4_TC_EMS_Msk (0x800000UL) |
| |
| #define | CCU4_CC4_TC_EMT_Pos (24UL) |
| |
| #define | CCU4_CC4_TC_EMT_Msk (0x1000000UL) |
| |
| #define | CCU4_CC4_TC_MCME_Pos (25UL) |
| |
| #define | CCU4_CC4_TC_MCME_Msk (0x2000000UL) |
| |
| #define | CCU4_CC4_PSL_PSL_Pos (0UL) |
| |
| #define | CCU4_CC4_PSL_PSL_Msk (0x1UL) |
| |
| #define | CCU4_CC4_DIT_DCV_Pos (0UL) |
| |
| #define | CCU4_CC4_DIT_DCV_Msk (0xfUL) |
| |
| #define | CCU4_CC4_DIT_DCNT_Pos (8UL) |
| |
| #define | CCU4_CC4_DIT_DCNT_Msk (0xf00UL) |
| |
| #define | CCU4_CC4_DITS_DCVS_Pos (0UL) |
| |
| #define | CCU4_CC4_DITS_DCVS_Msk (0xfUL) |
| |
| #define | CCU4_CC4_PSC_PSIV_Pos (0UL) |
| |
| #define | CCU4_CC4_PSC_PSIV_Msk (0xfUL) |
| |
| #define | CCU4_CC4_FPC_PCMP_Pos (0UL) |
| |
| #define | CCU4_CC4_FPC_PCMP_Msk (0xfUL) |
| |
| #define | CCU4_CC4_FPC_PVAL_Pos (8UL) |
| |
| #define | CCU4_CC4_FPC_PVAL_Msk (0xf00UL) |
| |
| #define | CCU4_CC4_FPCS_PCMP_Pos (0UL) |
| |
| #define | CCU4_CC4_FPCS_PCMP_Msk (0xfUL) |
| |
| #define | CCU4_CC4_PR_PR_Pos (0UL) |
| |
| #define | CCU4_CC4_PR_PR_Msk (0xffffUL) |
| |
| #define | CCU4_CC4_PRS_PRS_Pos (0UL) |
| |
| #define | CCU4_CC4_PRS_PRS_Msk (0xffffUL) |
| |
| #define | CCU4_CC4_CR_CR_Pos (0UL) |
| |
| #define | CCU4_CC4_CR_CR_Msk (0xffffUL) |
| |
| #define | CCU4_CC4_CRS_CRS_Pos (0UL) |
| |
| #define | CCU4_CC4_CRS_CRS_Msk (0xffffUL) |
| |
| #define | CCU4_CC4_TIMER_TVAL_Pos (0UL) |
| |
| #define | CCU4_CC4_TIMER_TVAL_Msk (0xffffUL) |
| |
| #define | CCU4_CC4_CV_CAPTV_Pos (0UL) |
| |
| #define | CCU4_CC4_CV_CAPTV_Msk (0xffffUL) |
| |
| #define | CCU4_CC4_CV_FPCV_Pos (16UL) |
| |
| #define | CCU4_CC4_CV_FPCV_Msk (0xf0000UL) |
| |
| #define | CCU4_CC4_CV_FFL_Pos (20UL) |
| |
| #define | CCU4_CC4_CV_FFL_Msk (0x100000UL) |
| |
| #define | CCU4_CC4_INTS_PMUS_Pos (0UL) |
| |
| #define | CCU4_CC4_INTS_PMUS_Msk (0x1UL) |
| |
| #define | CCU4_CC4_INTS_OMDS_Pos (1UL) |
| |
| #define | CCU4_CC4_INTS_OMDS_Msk (0x2UL) |
| |
| #define | CCU4_CC4_INTS_CMUS_Pos (2UL) |
| |
| #define | CCU4_CC4_INTS_CMUS_Msk (0x4UL) |
| |
| #define | CCU4_CC4_INTS_CMDS_Pos (3UL) |
| |
| #define | CCU4_CC4_INTS_CMDS_Msk (0x8UL) |
| |
| #define | CCU4_CC4_INTS_E0AS_Pos (8UL) |
| |
| #define | CCU4_CC4_INTS_E0AS_Msk (0x100UL) |
| |
| #define | CCU4_CC4_INTS_E1AS_Pos (9UL) |
| |
| #define | CCU4_CC4_INTS_E1AS_Msk (0x200UL) |
| |
| #define | CCU4_CC4_INTS_E2AS_Pos (10UL) |
| |
| #define | CCU4_CC4_INTS_E2AS_Msk (0x400UL) |
| |
| #define | CCU4_CC4_INTS_TRPF_Pos (11UL) |
| |
| #define | CCU4_CC4_INTS_TRPF_Msk (0x800UL) |
| |
| #define | CCU4_CC4_INTE_PME_Pos (0UL) |
| |
| #define | CCU4_CC4_INTE_PME_Msk (0x1UL) |
| |
| #define | CCU4_CC4_INTE_OME_Pos (1UL) |
| |
| #define | CCU4_CC4_INTE_OME_Msk (0x2UL) |
| |
| #define | CCU4_CC4_INTE_CMUE_Pos (2UL) |
| |
| #define | CCU4_CC4_INTE_CMUE_Msk (0x4UL) |
| |
| #define | CCU4_CC4_INTE_CMDE_Pos (3UL) |
| |
| #define | CCU4_CC4_INTE_CMDE_Msk (0x8UL) |
| |
| #define | CCU4_CC4_INTE_E0AE_Pos (8UL) |
| |
| #define | CCU4_CC4_INTE_E0AE_Msk (0x100UL) |
| |
| #define | CCU4_CC4_INTE_E1AE_Pos (9UL) |
| |
| #define | CCU4_CC4_INTE_E1AE_Msk (0x200UL) |
| |
| #define | CCU4_CC4_INTE_E2AE_Pos (10UL) |
| |
| #define | CCU4_CC4_INTE_E2AE_Msk (0x400UL) |
| |
| #define | CCU4_CC4_SRS_POSR_Pos (0UL) |
| |
| #define | CCU4_CC4_SRS_POSR_Msk (0x3UL) |
| |
| #define | CCU4_CC4_SRS_CMSR_Pos (2UL) |
| |
| #define | CCU4_CC4_SRS_CMSR_Msk (0xcUL) |
| |
| #define | CCU4_CC4_SRS_E0SR_Pos (8UL) |
| |
| #define | CCU4_CC4_SRS_E0SR_Msk (0x300UL) |
| |
| #define | CCU4_CC4_SRS_E1SR_Pos (10UL) |
| |
| #define | CCU4_CC4_SRS_E1SR_Msk (0xc00UL) |
| |
| #define | CCU4_CC4_SRS_E2SR_Pos (12UL) |
| |
| #define | CCU4_CC4_SRS_E2SR_Msk (0x3000UL) |
| |
| #define | CCU4_CC4_SWS_SPM_Pos (0UL) |
| |
| #define | CCU4_CC4_SWS_SPM_Msk (0x1UL) |
| |
| #define | CCU4_CC4_SWS_SOM_Pos (1UL) |
| |
| #define | CCU4_CC4_SWS_SOM_Msk (0x2UL) |
| |
| #define | CCU4_CC4_SWS_SCMU_Pos (2UL) |
| |
| #define | CCU4_CC4_SWS_SCMU_Msk (0x4UL) |
| |
| #define | CCU4_CC4_SWS_SCMD_Pos (3UL) |
| |
| #define | CCU4_CC4_SWS_SCMD_Msk (0x8UL) |
| |
| #define | CCU4_CC4_SWS_SE0A_Pos (8UL) |
| |
| #define | CCU4_CC4_SWS_SE0A_Msk (0x100UL) |
| |
| #define | CCU4_CC4_SWS_SE1A_Pos (9UL) |
| |
| #define | CCU4_CC4_SWS_SE1A_Msk (0x200UL) |
| |
| #define | CCU4_CC4_SWS_SE2A_Pos (10UL) |
| |
| #define | CCU4_CC4_SWS_SE2A_Msk (0x400UL) |
| |
| #define | CCU4_CC4_SWS_STRPF_Pos (11UL) |
| |
| #define | CCU4_CC4_SWS_STRPF_Msk (0x800UL) |
| |
| #define | CCU4_CC4_SWR_RPM_Pos (0UL) |
| |
| #define | CCU4_CC4_SWR_RPM_Msk (0x1UL) |
| |
| #define | CCU4_CC4_SWR_ROM_Pos (1UL) |
| |
| #define | CCU4_CC4_SWR_ROM_Msk (0x2UL) |
| |
| #define | CCU4_CC4_SWR_RCMU_Pos (2UL) |
| |
| #define | CCU4_CC4_SWR_RCMU_Msk (0x4UL) |
| |
| #define | CCU4_CC4_SWR_RCMD_Pos (3UL) |
| |
| #define | CCU4_CC4_SWR_RCMD_Msk (0x8UL) |
| |
| #define | CCU4_CC4_SWR_RE0A_Pos (8UL) |
| |
| #define | CCU4_CC4_SWR_RE0A_Msk (0x100UL) |
| |
| #define | CCU4_CC4_SWR_RE1A_Pos (9UL) |
| |
| #define | CCU4_CC4_SWR_RE1A_Msk (0x200UL) |
| |
| #define | CCU4_CC4_SWR_RE2A_Pos (10UL) |
| |
| #define | CCU4_CC4_SWR_RE2A_Msk (0x400UL) |
| |
| #define | CCU4_CC4_SWR_RTRPF_Pos (11UL) |
| |
| #define | CCU4_CC4_SWR_RTRPF_Msk (0x800UL) |
| |
| #define | CCU4_CC4_ECRD0_CAPV_Pos (0UL) |
| |
| #define | CCU4_CC4_ECRD0_CAPV_Msk (0xffffUL) |
| |
| #define | CCU4_CC4_ECRD0_FPCV_Pos (16UL) |
| |
| #define | CCU4_CC4_ECRD0_FPCV_Msk (0xf0000UL) |
| |
| #define | CCU4_CC4_ECRD0_SPTR_Pos (20UL) |
| |
| #define | CCU4_CC4_ECRD0_SPTR_Msk (0x300000UL) |
| |
| #define | CCU4_CC4_ECRD0_VPTR_Pos (22UL) |
| |
| #define | CCU4_CC4_ECRD0_VPTR_Msk (0xc00000UL) |
| |
| #define | CCU4_CC4_ECRD0_FFL_Pos (24UL) |
| |
| #define | CCU4_CC4_ECRD0_FFL_Msk (0x1000000UL) |
| |
| #define | CCU4_CC4_ECRD0_LCV_Pos (25UL) |
| |
| #define | CCU4_CC4_ECRD0_LCV_Msk (0x2000000UL) |
| |
| #define | CCU4_CC4_ECRD1_CAPV_Pos (0UL) |
| |
| #define | CCU4_CC4_ECRD1_CAPV_Msk (0xffffUL) |
| |
| #define | CCU4_CC4_ECRD1_FPCV_Pos (16UL) |
| |
| #define | CCU4_CC4_ECRD1_FPCV_Msk (0xf0000UL) |
| |
| #define | CCU4_CC4_ECRD1_SPTR_Pos (20UL) |
| |
| #define | CCU4_CC4_ECRD1_SPTR_Msk (0x300000UL) |
| |
| #define | CCU4_CC4_ECRD1_VPTR_Pos (22UL) |
| |
| #define | CCU4_CC4_ECRD1_VPTR_Msk (0xc00000UL) |
| |
| #define | CCU4_CC4_ECRD1_FFL_Pos (24UL) |
| |
| #define | CCU4_CC4_ECRD1_FFL_Msk (0x1000000UL) |
| |
| #define | CCU4_CC4_ECRD1_LCV_Pos (25UL) |
| |
| #define | CCU4_CC4_ECRD1_LCV_Msk (0x2000000UL) |
| |
| #define | CCU8_GCTRL_PRBC_Pos (0UL) |
| |
| #define | CCU8_GCTRL_PRBC_Msk (0x7UL) |
| |
| #define | CCU8_GCTRL_PCIS_Pos (4UL) |
| |
| #define | CCU8_GCTRL_PCIS_Msk (0x30UL) |
| |
| #define | CCU8_GCTRL_SUSCFG_Pos (8UL) |
| |
| #define | CCU8_GCTRL_SUSCFG_Msk (0x300UL) |
| |
| #define | CCU8_GCTRL_MSE0_Pos (10UL) |
| |
| #define | CCU8_GCTRL_MSE0_Msk (0x400UL) |
| |
| #define | CCU8_GCTRL_MSE1_Pos (11UL) |
| |
| #define | CCU8_GCTRL_MSE1_Msk (0x800UL) |
| |
| #define | CCU8_GCTRL_MSE2_Pos (12UL) |
| |
| #define | CCU8_GCTRL_MSE2_Msk (0x1000UL) |
| |
| #define | CCU8_GCTRL_MSE3_Pos (13UL) |
| |
| #define | CCU8_GCTRL_MSE3_Msk (0x2000UL) |
| |
| #define | CCU8_GCTRL_MSDE_Pos (14UL) |
| |
| #define | CCU8_GCTRL_MSDE_Msk (0xc000UL) |
| |
| #define | CCU8_GSTAT_S0I_Pos (0UL) |
| |
| #define | CCU8_GSTAT_S0I_Msk (0x1UL) |
| |
| #define | CCU8_GSTAT_S1I_Pos (1UL) |
| |
| #define | CCU8_GSTAT_S1I_Msk (0x2UL) |
| |
| #define | CCU8_GSTAT_S2I_Pos (2UL) |
| |
| #define | CCU8_GSTAT_S2I_Msk (0x4UL) |
| |
| #define | CCU8_GSTAT_S3I_Pos (3UL) |
| |
| #define | CCU8_GSTAT_S3I_Msk (0x8UL) |
| |
| #define | CCU8_GSTAT_PRB_Pos (8UL) |
| |
| #define | CCU8_GSTAT_PRB_Msk (0x100UL) |
| |
| #define | CCU8_GSTAT_PCRB_Pos (10UL) |
| |
| #define | CCU8_GSTAT_PCRB_Msk (0x400UL) |
| |
| #define | CCU8_GIDLS_SS0I_Pos (0UL) |
| |
| #define | CCU8_GIDLS_SS0I_Msk (0x1UL) |
| |
| #define | CCU8_GIDLS_SS1I_Pos (1UL) |
| |
| #define | CCU8_GIDLS_SS1I_Msk (0x2UL) |
| |
| #define | CCU8_GIDLS_SS2I_Pos (2UL) |
| |
| #define | CCU8_GIDLS_SS2I_Msk (0x4UL) |
| |
| #define | CCU8_GIDLS_SS3I_Pos (3UL) |
| |
| #define | CCU8_GIDLS_SS3I_Msk (0x8UL) |
| |
| #define | CCU8_GIDLS_CPRB_Pos (8UL) |
| |
| #define | CCU8_GIDLS_CPRB_Msk (0x100UL) |
| |
| #define | CCU8_GIDLS_PSIC_Pos (9UL) |
| |
| #define | CCU8_GIDLS_PSIC_Msk (0x200UL) |
| |
| #define | CCU8_GIDLS_CPCH_Pos (10UL) |
| |
| #define | CCU8_GIDLS_CPCH_Msk (0x400UL) |
| |
| #define | CCU8_GIDLC_CS0I_Pos (0UL) |
| |
| #define | CCU8_GIDLC_CS0I_Msk (0x1UL) |
| |
| #define | CCU8_GIDLC_CS1I_Pos (1UL) |
| |
| #define | CCU8_GIDLC_CS1I_Msk (0x2UL) |
| |
| #define | CCU8_GIDLC_CS2I_Pos (2UL) |
| |
| #define | CCU8_GIDLC_CS2I_Msk (0x4UL) |
| |
| #define | CCU8_GIDLC_CS3I_Pos (3UL) |
| |
| #define | CCU8_GIDLC_CS3I_Msk (0x8UL) |
| |
| #define | CCU8_GIDLC_SPRB_Pos (8UL) |
| |
| #define | CCU8_GIDLC_SPRB_Msk (0x100UL) |
| |
| #define | CCU8_GIDLC_SPCH_Pos (10UL) |
| |
| #define | CCU8_GIDLC_SPCH_Msk (0x400UL) |
| |
| #define | CCU8_GCSS_S0SE_Pos (0UL) |
| |
| #define | CCU8_GCSS_S0SE_Msk (0x1UL) |
| |
| #define | CCU8_GCSS_S0DSE_Pos (1UL) |
| |
| #define | CCU8_GCSS_S0DSE_Msk (0x2UL) |
| |
| #define | CCU8_GCSS_S0PSE_Pos (2UL) |
| |
| #define | CCU8_GCSS_S0PSE_Msk (0x4UL) |
| |
| #define | CCU8_GCSS_S1SE_Pos (4UL) |
| |
| #define | CCU8_GCSS_S1SE_Msk (0x10UL) |
| |
| #define | CCU8_GCSS_S1DSE_Pos (5UL) |
| |
| #define | CCU8_GCSS_S1DSE_Msk (0x20UL) |
| |
| #define | CCU8_GCSS_S1PSE_Pos (6UL) |
| |
| #define | CCU8_GCSS_S1PSE_Msk (0x40UL) |
| |
| #define | CCU8_GCSS_S2SE_Pos (8UL) |
| |
| #define | CCU8_GCSS_S2SE_Msk (0x100UL) |
| |
| #define | CCU8_GCSS_S2DSE_Pos (9UL) |
| |
| #define | CCU8_GCSS_S2DSE_Msk (0x200UL) |
| |
| #define | CCU8_GCSS_S2PSE_Pos (10UL) |
| |
| #define | CCU8_GCSS_S2PSE_Msk (0x400UL) |
| |
| #define | CCU8_GCSS_S3SE_Pos (12UL) |
| |
| #define | CCU8_GCSS_S3SE_Msk (0x1000UL) |
| |
| #define | CCU8_GCSS_S3DSE_Pos (13UL) |
| |
| #define | CCU8_GCSS_S3DSE_Msk (0x2000UL) |
| |
| #define | CCU8_GCSS_S3PSE_Pos (14UL) |
| |
| #define | CCU8_GCSS_S3PSE_Msk (0x4000UL) |
| |
| #define | CCU8_GCSS_S0ST1S_Pos (16UL) |
| |
| #define | CCU8_GCSS_S0ST1S_Msk (0x10000UL) |
| |
| #define | CCU8_GCSS_S1ST1S_Pos (17UL) |
| |
| #define | CCU8_GCSS_S1ST1S_Msk (0x20000UL) |
| |
| #define | CCU8_GCSS_S2ST1S_Pos (18UL) |
| |
| #define | CCU8_GCSS_S2ST1S_Msk (0x40000UL) |
| |
| #define | CCU8_GCSS_S3ST1S_Pos (19UL) |
| |
| #define | CCU8_GCSS_S3ST1S_Msk (0x80000UL) |
| |
| #define | CCU8_GCSS_S0ST2S_Pos (20UL) |
| |
| #define | CCU8_GCSS_S0ST2S_Msk (0x100000UL) |
| |
| #define | CCU8_GCSS_S1ST2S_Pos (21UL) |
| |
| #define | CCU8_GCSS_S1ST2S_Msk (0x200000UL) |
| |
| #define | CCU8_GCSS_S2ST2S_Pos (22UL) |
| |
| #define | CCU8_GCSS_S2ST2S_Msk (0x400000UL) |
| |
| #define | CCU8_GCSS_S3ST2S_Pos (23UL) |
| |
| #define | CCU8_GCSS_S3ST2S_Msk (0x800000UL) |
| |
| #define | CCU8_GCSC_S0SC_Pos (0UL) |
| |
| #define | CCU8_GCSC_S0SC_Msk (0x1UL) |
| |
| #define | CCU8_GCSC_S0DSC_Pos (1UL) |
| |
| #define | CCU8_GCSC_S0DSC_Msk (0x2UL) |
| |
| #define | CCU8_GCSC_S0PSC_Pos (2UL) |
| |
| #define | CCU8_GCSC_S0PSC_Msk (0x4UL) |
| |
| #define | CCU8_GCSC_S1SC_Pos (4UL) |
| |
| #define | CCU8_GCSC_S1SC_Msk (0x10UL) |
| |
| #define | CCU8_GCSC_S1DSC_Pos (5UL) |
| |
| #define | CCU8_GCSC_S1DSC_Msk (0x20UL) |
| |
| #define | CCU8_GCSC_S1PSC_Pos (6UL) |
| |
| #define | CCU8_GCSC_S1PSC_Msk (0x40UL) |
| |
| #define | CCU8_GCSC_S2SC_Pos (8UL) |
| |
| #define | CCU8_GCSC_S2SC_Msk (0x100UL) |
| |
| #define | CCU8_GCSC_S2DSC_Pos (9UL) |
| |
| #define | CCU8_GCSC_S2DSC_Msk (0x200UL) |
| |
| #define | CCU8_GCSC_S2PSC_Pos (10UL) |
| |
| #define | CCU8_GCSC_S2PSC_Msk (0x400UL) |
| |
| #define | CCU8_GCSC_S3SC_Pos (12UL) |
| |
| #define | CCU8_GCSC_S3SC_Msk (0x1000UL) |
| |
| #define | CCU8_GCSC_S3DSC_Pos (13UL) |
| |
| #define | CCU8_GCSC_S3DSC_Msk (0x2000UL) |
| |
| #define | CCU8_GCSC_S3PSC_Pos (14UL) |
| |
| #define | CCU8_GCSC_S3PSC_Msk (0x4000UL) |
| |
| #define | CCU8_GCSC_S0ST1C_Pos (16UL) |
| |
| #define | CCU8_GCSC_S0ST1C_Msk (0x10000UL) |
| |
| #define | CCU8_GCSC_S1ST1C_Pos (17UL) |
| |
| #define | CCU8_GCSC_S1ST1C_Msk (0x20000UL) |
| |
| #define | CCU8_GCSC_S2ST1C_Pos (18UL) |
| |
| #define | CCU8_GCSC_S2ST1C_Msk (0x40000UL) |
| |
| #define | CCU8_GCSC_S3ST1C_Pos (19UL) |
| |
| #define | CCU8_GCSC_S3ST1C_Msk (0x80000UL) |
| |
| #define | CCU8_GCSC_S0ST2C_Pos (20UL) |
| |
| #define | CCU8_GCSC_S0ST2C_Msk (0x100000UL) |
| |
| #define | CCU8_GCSC_S1ST2C_Pos (21UL) |
| |
| #define | CCU8_GCSC_S1ST2C_Msk (0x200000UL) |
| |
| #define | CCU8_GCSC_S2ST2C_Pos (22UL) |
| |
| #define | CCU8_GCSC_S2ST2C_Msk (0x400000UL) |
| |
| #define | CCU8_GCSC_S3ST2C_Pos (23UL) |
| |
| #define | CCU8_GCSC_S3ST2C_Msk (0x800000UL) |
| |
| #define | CCU8_GCST_S0SS_Pos (0UL) |
| |
| #define | CCU8_GCST_S0SS_Msk (0x1UL) |
| |
| #define | CCU8_GCST_S0DSS_Pos (1UL) |
| |
| #define | CCU8_GCST_S0DSS_Msk (0x2UL) |
| |
| #define | CCU8_GCST_S0PSS_Pos (2UL) |
| |
| #define | CCU8_GCST_S0PSS_Msk (0x4UL) |
| |
| #define | CCU8_GCST_S1SS_Pos (4UL) |
| |
| #define | CCU8_GCST_S1SS_Msk (0x10UL) |
| |
| #define | CCU8_GCST_S1DSS_Pos (5UL) |
| |
| #define | CCU8_GCST_S1DSS_Msk (0x20UL) |
| |
| #define | CCU8_GCST_S1PSS_Pos (6UL) |
| |
| #define | CCU8_GCST_S1PSS_Msk (0x40UL) |
| |
| #define | CCU8_GCST_S2SS_Pos (8UL) |
| |
| #define | CCU8_GCST_S2SS_Msk (0x100UL) |
| |
| #define | CCU8_GCST_S2DSS_Pos (9UL) |
| |
| #define | CCU8_GCST_S2DSS_Msk (0x200UL) |
| |
| #define | CCU8_GCST_S2PSS_Pos (10UL) |
| |
| #define | CCU8_GCST_S2PSS_Msk (0x400UL) |
| |
| #define | CCU8_GCST_S3SS_Pos (12UL) |
| |
| #define | CCU8_GCST_S3SS_Msk (0x1000UL) |
| |
| #define | CCU8_GCST_S3DSS_Pos (13UL) |
| |
| #define | CCU8_GCST_S3DSS_Msk (0x2000UL) |
| |
| #define | CCU8_GCST_S3PSS_Pos (14UL) |
| |
| #define | CCU8_GCST_S3PSS_Msk (0x4000UL) |
| |
| #define | CCU8_GCST_CC80ST1_Pos (16UL) |
| |
| #define | CCU8_GCST_CC80ST1_Msk (0x10000UL) |
| |
| #define | CCU8_GCST_CC81ST1_Pos (17UL) |
| |
| #define | CCU8_GCST_CC81ST1_Msk (0x20000UL) |
| |
| #define | CCU8_GCST_CC82ST1_Pos (18UL) |
| |
| #define | CCU8_GCST_CC82ST1_Msk (0x40000UL) |
| |
| #define | CCU8_GCST_CC83ST1_Pos (19UL) |
| |
| #define | CCU8_GCST_CC83ST1_Msk (0x80000UL) |
| |
| #define | CCU8_GCST_CC80ST2_Pos (20UL) |
| |
| #define | CCU8_GCST_CC80ST2_Msk (0x100000UL) |
| |
| #define | CCU8_GCST_CC81ST2_Pos (21UL) |
| |
| #define | CCU8_GCST_CC81ST2_Msk (0x200000UL) |
| |
| #define | CCU8_GCST_CC82ST2_Pos (22UL) |
| |
| #define | CCU8_GCST_CC82ST2_Msk (0x400000UL) |
| |
| #define | CCU8_GCST_CC83ST2_Pos (23UL) |
| |
| #define | CCU8_GCST_CC83ST2_Msk (0x800000UL) |
| |
| #define | CCU8_GPCHK_PASE_Pos (0UL) |
| |
| #define | CCU8_GPCHK_PASE_Msk (0x1UL) |
| |
| #define | CCU8_GPCHK_PACS_Pos (1UL) |
| |
| #define | CCU8_GPCHK_PACS_Msk (0x6UL) |
| |
| #define | CCU8_GPCHK_PISEL_Pos (3UL) |
| |
| #define | CCU8_GPCHK_PISEL_Msk (0x18UL) |
| |
| #define | CCU8_GPCHK_PCDS_Pos (5UL) |
| |
| #define | CCU8_GPCHK_PCDS_Msk (0x60UL) |
| |
| #define | CCU8_GPCHK_PCTS_Pos (7UL) |
| |
| #define | CCU8_GPCHK_PCTS_Msk (0x80UL) |
| |
| #define | CCU8_GPCHK_PCST_Pos (15UL) |
| |
| #define | CCU8_GPCHK_PCST_Msk (0x8000UL) |
| |
| #define | CCU8_GPCHK_PCSEL0_Pos (16UL) |
| |
| #define | CCU8_GPCHK_PCSEL0_Msk (0xf0000UL) |
| |
| #define | CCU8_GPCHK_PCSEL1_Pos (20UL) |
| |
| #define | CCU8_GPCHK_PCSEL1_Msk (0xf00000UL) |
| |
| #define | CCU8_GPCHK_PCSEL2_Pos (24UL) |
| |
| #define | CCU8_GPCHK_PCSEL2_Msk (0xf000000UL) |
| |
| #define | CCU8_GPCHK_PCSEL3_Pos (28UL) |
| |
| #define | CCU8_GPCHK_PCSEL3_Msk (0xf0000000UL) |
| |
| #define | CCU8_MIDR_MODR_Pos (0UL) |
| |
| #define | CCU8_MIDR_MODR_Msk (0xffUL) |
| |
| #define | CCU8_MIDR_MODT_Pos (8UL) |
| |
| #define | CCU8_MIDR_MODT_Msk (0xff00UL) |
| |
| #define | CCU8_MIDR_MODN_Pos (16UL) |
| |
| #define | CCU8_MIDR_MODN_Msk (0xffff0000UL) |
| |
| #define | CCU8_CC8_INS_EV0IS_Pos (0UL) |
| |
| #define | CCU8_CC8_INS_EV0IS_Msk (0xfUL) |
| |
| #define | CCU8_CC8_INS_EV1IS_Pos (4UL) |
| |
| #define | CCU8_CC8_INS_EV1IS_Msk (0xf0UL) |
| |
| #define | CCU8_CC8_INS_EV2IS_Pos (8UL) |
| |
| #define | CCU8_CC8_INS_EV2IS_Msk (0xf00UL) |
| |
| #define | CCU8_CC8_INS_EV0EM_Pos (16UL) |
| |
| #define | CCU8_CC8_INS_EV0EM_Msk (0x30000UL) |
| |
| #define | CCU8_CC8_INS_EV1EM_Pos (18UL) |
| |
| #define | CCU8_CC8_INS_EV1EM_Msk (0xc0000UL) |
| |
| #define | CCU8_CC8_INS_EV2EM_Pos (20UL) |
| |
| #define | CCU8_CC8_INS_EV2EM_Msk (0x300000UL) |
| |
| #define | CCU8_CC8_INS_EV0LM_Pos (22UL) |
| |
| #define | CCU8_CC8_INS_EV0LM_Msk (0x400000UL) |
| |
| #define | CCU8_CC8_INS_EV1LM_Pos (23UL) |
| |
| #define | CCU8_CC8_INS_EV1LM_Msk (0x800000UL) |
| |
| #define | CCU8_CC8_INS_EV2LM_Pos (24UL) |
| |
| #define | CCU8_CC8_INS_EV2LM_Msk (0x1000000UL) |
| |
| #define | CCU8_CC8_INS_LPF0M_Pos (25UL) |
| |
| #define | CCU8_CC8_INS_LPF0M_Msk (0x6000000UL) |
| |
| #define | CCU8_CC8_INS_LPF1M_Pos (27UL) |
| |
| #define | CCU8_CC8_INS_LPF1M_Msk (0x18000000UL) |
| |
| #define | CCU8_CC8_INS_LPF2M_Pos (29UL) |
| |
| #define | CCU8_CC8_INS_LPF2M_Msk (0x60000000UL) |
| |
| #define | CCU8_CC8_CMC_STRTS_Pos (0UL) |
| |
| #define | CCU8_CC8_CMC_STRTS_Msk (0x3UL) |
| |
| #define | CCU8_CC8_CMC_ENDS_Pos (2UL) |
| |
| #define | CCU8_CC8_CMC_ENDS_Msk (0xcUL) |
| |
| #define | CCU8_CC8_CMC_CAP0S_Pos (4UL) |
| |
| #define | CCU8_CC8_CMC_CAP0S_Msk (0x30UL) |
| |
| #define | CCU8_CC8_CMC_CAP1S_Pos (6UL) |
| |
| #define | CCU8_CC8_CMC_CAP1S_Msk (0xc0UL) |
| |
| #define | CCU8_CC8_CMC_GATES_Pos (8UL) |
| |
| #define | CCU8_CC8_CMC_GATES_Msk (0x300UL) |
| |
| #define | CCU8_CC8_CMC_UDS_Pos (10UL) |
| |
| #define | CCU8_CC8_CMC_UDS_Msk (0xc00UL) |
| |
| #define | CCU8_CC8_CMC_LDS_Pos (12UL) |
| |
| #define | CCU8_CC8_CMC_LDS_Msk (0x3000UL) |
| |
| #define | CCU8_CC8_CMC_CNTS_Pos (14UL) |
| |
| #define | CCU8_CC8_CMC_CNTS_Msk (0xc000UL) |
| |
| #define | CCU8_CC8_CMC_OFS_Pos (16UL) |
| |
| #define | CCU8_CC8_CMC_OFS_Msk (0x10000UL) |
| |
| #define | CCU8_CC8_CMC_TS_Pos (17UL) |
| |
| #define | CCU8_CC8_CMC_TS_Msk (0x20000UL) |
| |
| #define | CCU8_CC8_CMC_MOS_Pos (18UL) |
| |
| #define | CCU8_CC8_CMC_MOS_Msk (0xc0000UL) |
| |
| #define | CCU8_CC8_CMC_TCE_Pos (20UL) |
| |
| #define | CCU8_CC8_CMC_TCE_Msk (0x100000UL) |
| |
| #define | CCU8_CC8_TCST_TRB_Pos (0UL) |
| |
| #define | CCU8_CC8_TCST_TRB_Msk (0x1UL) |
| |
| #define | CCU8_CC8_TCST_CDIR_Pos (1UL) |
| |
| #define | CCU8_CC8_TCST_CDIR_Msk (0x2UL) |
| |
| #define | CCU8_CC8_TCST_DTR1_Pos (3UL) |
| |
| #define | CCU8_CC8_TCST_DTR1_Msk (0x8UL) |
| |
| #define | CCU8_CC8_TCST_DTR2_Pos (4UL) |
| |
| #define | CCU8_CC8_TCST_DTR2_Msk (0x10UL) |
| |
| #define | CCU8_CC8_TCSET_TRBS_Pos (0UL) |
| |
| #define | CCU8_CC8_TCSET_TRBS_Msk (0x1UL) |
| |
| #define | CCU8_CC8_TCCLR_TRBC_Pos (0UL) |
| |
| #define | CCU8_CC8_TCCLR_TRBC_Msk (0x1UL) |
| |
| #define | CCU8_CC8_TCCLR_TCC_Pos (1UL) |
| |
| #define | CCU8_CC8_TCCLR_TCC_Msk (0x2UL) |
| |
| #define | CCU8_CC8_TCCLR_DITC_Pos (2UL) |
| |
| #define | CCU8_CC8_TCCLR_DITC_Msk (0x4UL) |
| |
| #define | CCU8_CC8_TCCLR_DTC1C_Pos (3UL) |
| |
| #define | CCU8_CC8_TCCLR_DTC1C_Msk (0x8UL) |
| |
| #define | CCU8_CC8_TCCLR_DTC2C_Pos (4UL) |
| |
| #define | CCU8_CC8_TCCLR_DTC2C_Msk (0x10UL) |
| |
| #define | CCU8_CC8_TC_TCM_Pos (0UL) |
| |
| #define | CCU8_CC8_TC_TCM_Msk (0x1UL) |
| |
| #define | CCU8_CC8_TC_TSSM_Pos (1UL) |
| |
| #define | CCU8_CC8_TC_TSSM_Msk (0x2UL) |
| |
| #define | CCU8_CC8_TC_CLST_Pos (2UL) |
| |
| #define | CCU8_CC8_TC_CLST_Msk (0x4UL) |
| |
| #define | CCU8_CC8_TC_CMOD_Pos (3UL) |
| |
| #define | CCU8_CC8_TC_CMOD_Msk (0x8UL) |
| |
| #define | CCU8_CC8_TC_ECM_Pos (4UL) |
| |
| #define | CCU8_CC8_TC_ECM_Msk (0x10UL) |
| |
| #define | CCU8_CC8_TC_CAPC_Pos (5UL) |
| |
| #define | CCU8_CC8_TC_CAPC_Msk (0x60UL) |
| |
| #define | CCU8_CC8_TC_TLS_Pos (7UL) |
| |
| #define | CCU8_CC8_TC_TLS_Msk (0x80UL) |
| |
| #define | CCU8_CC8_TC_ENDM_Pos (8UL) |
| |
| #define | CCU8_CC8_TC_ENDM_Msk (0x300UL) |
| |
| #define | CCU8_CC8_TC_STRM_Pos (10UL) |
| |
| #define | CCU8_CC8_TC_STRM_Msk (0x400UL) |
| |
| #define | CCU8_CC8_TC_SCE_Pos (11UL) |
| |
| #define | CCU8_CC8_TC_SCE_Msk (0x800UL) |
| |
| #define | CCU8_CC8_TC_CCS_Pos (12UL) |
| |
| #define | CCU8_CC8_TC_CCS_Msk (0x1000UL) |
| |
| #define | CCU8_CC8_TC_DITHE_Pos (13UL) |
| |
| #define | CCU8_CC8_TC_DITHE_Msk (0x6000UL) |
| |
| #define | CCU8_CC8_TC_DIM_Pos (15UL) |
| |
| #define | CCU8_CC8_TC_DIM_Msk (0x8000UL) |
| |
| #define | CCU8_CC8_TC_FPE_Pos (16UL) |
| |
| #define | CCU8_CC8_TC_FPE_Msk (0x10000UL) |
| |
| #define | CCU8_CC8_TC_TRAPE0_Pos (17UL) |
| |
| #define | CCU8_CC8_TC_TRAPE0_Msk (0x20000UL) |
| |
| #define | CCU8_CC8_TC_TRAPE1_Pos (18UL) |
| |
| #define | CCU8_CC8_TC_TRAPE1_Msk (0x40000UL) |
| |
| #define | CCU8_CC8_TC_TRAPE2_Pos (19UL) |
| |
| #define | CCU8_CC8_TC_TRAPE2_Msk (0x80000UL) |
| |
| #define | CCU8_CC8_TC_TRAPE3_Pos (20UL) |
| |
| #define | CCU8_CC8_TC_TRAPE3_Msk (0x100000UL) |
| |
| #define | CCU8_CC8_TC_TRPSE_Pos (21UL) |
| |
| #define | CCU8_CC8_TC_TRPSE_Msk (0x200000UL) |
| |
| #define | CCU8_CC8_TC_TRPSW_Pos (22UL) |
| |
| #define | CCU8_CC8_TC_TRPSW_Msk (0x400000UL) |
| |
| #define | CCU8_CC8_TC_EMS_Pos (23UL) |
| |
| #define | CCU8_CC8_TC_EMS_Msk (0x800000UL) |
| |
| #define | CCU8_CC8_TC_EMT_Pos (24UL) |
| |
| #define | CCU8_CC8_TC_EMT_Msk (0x1000000UL) |
| |
| #define | CCU8_CC8_TC_MCME1_Pos (25UL) |
| |
| #define | CCU8_CC8_TC_MCME1_Msk (0x2000000UL) |
| |
| #define | CCU8_CC8_TC_MCME2_Pos (26UL) |
| |
| #define | CCU8_CC8_TC_MCME2_Msk (0x4000000UL) |
| |
| #define | CCU8_CC8_TC_EME_Pos (27UL) |
| |
| #define | CCU8_CC8_TC_EME_Msk (0x18000000UL) |
| |
| #define | CCU8_CC8_TC_STOS_Pos (29UL) |
| |
| #define | CCU8_CC8_TC_STOS_Msk (0x60000000UL) |
| |
| #define | CCU8_CC8_PSL_PSL11_Pos (0UL) |
| |
| #define | CCU8_CC8_PSL_PSL11_Msk (0x1UL) |
| |
| #define | CCU8_CC8_PSL_PSL12_Pos (1UL) |
| |
| #define | CCU8_CC8_PSL_PSL12_Msk (0x2UL) |
| |
| #define | CCU8_CC8_PSL_PSL21_Pos (2UL) |
| |
| #define | CCU8_CC8_PSL_PSL21_Msk (0x4UL) |
| |
| #define | CCU8_CC8_PSL_PSL22_Pos (3UL) |
| |
| #define | CCU8_CC8_PSL_PSL22_Msk (0x8UL) |
| |
| #define | CCU8_CC8_DIT_DCV_Pos (0UL) |
| |
| #define | CCU8_CC8_DIT_DCV_Msk (0xfUL) |
| |
| #define | CCU8_CC8_DIT_DCNT_Pos (8UL) |
| |
| #define | CCU8_CC8_DIT_DCNT_Msk (0xf00UL) |
| |
| #define | CCU8_CC8_DITS_DCVS_Pos (0UL) |
| |
| #define | CCU8_CC8_DITS_DCVS_Msk (0xfUL) |
| |
| #define | CCU8_CC8_PSC_PSIV_Pos (0UL) |
| |
| #define | CCU8_CC8_PSC_PSIV_Msk (0xfUL) |
| |
| #define | CCU8_CC8_FPC_PCMP_Pos (0UL) |
| |
| #define | CCU8_CC8_FPC_PCMP_Msk (0xfUL) |
| |
| #define | CCU8_CC8_FPC_PVAL_Pos (8UL) |
| |
| #define | CCU8_CC8_FPC_PVAL_Msk (0xf00UL) |
| |
| #define | CCU8_CC8_FPCS_PCMP_Pos (0UL) |
| |
| #define | CCU8_CC8_FPCS_PCMP_Msk (0xfUL) |
| |
| #define | CCU8_CC8_PR_PR_Pos (0UL) |
| |
| #define | CCU8_CC8_PR_PR_Msk (0xffffUL) |
| |
| #define | CCU8_CC8_PRS_PRS_Pos (0UL) |
| |
| #define | CCU8_CC8_PRS_PRS_Msk (0xffffUL) |
| |
| #define | CCU8_CC8_CR1_CR1_Pos (0UL) |
| |
| #define | CCU8_CC8_CR1_CR1_Msk (0xffffUL) |
| |
| #define | CCU8_CC8_CR1S_CR1S_Pos (0UL) |
| |
| #define | CCU8_CC8_CR1S_CR1S_Msk (0xffffUL) |
| |
| #define | CCU8_CC8_CR2_CR2_Pos (0UL) |
| |
| #define | CCU8_CC8_CR2_CR2_Msk (0xffffUL) |
| |
| #define | CCU8_CC8_CR2S_CR2S_Pos (0UL) |
| |
| #define | CCU8_CC8_CR2S_CR2S_Msk (0xffffUL) |
| |
| #define | CCU8_CC8_CHC_ASE_Pos (0UL) |
| |
| #define | CCU8_CC8_CHC_ASE_Msk (0x1UL) |
| |
| #define | CCU8_CC8_CHC_OCS1_Pos (1UL) |
| |
| #define | CCU8_CC8_CHC_OCS1_Msk (0x2UL) |
| |
| #define | CCU8_CC8_CHC_OCS2_Pos (2UL) |
| |
| #define | CCU8_CC8_CHC_OCS2_Msk (0x4UL) |
| |
| #define | CCU8_CC8_CHC_OCS3_Pos (3UL) |
| |
| #define | CCU8_CC8_CHC_OCS3_Msk (0x8UL) |
| |
| #define | CCU8_CC8_CHC_OCS4_Pos (4UL) |
| |
| #define | CCU8_CC8_CHC_OCS4_Msk (0x10UL) |
| |
| #define | CCU8_CC8_DTC_DTE1_Pos (0UL) |
| |
| #define | CCU8_CC8_DTC_DTE1_Msk (0x1UL) |
| |
| #define | CCU8_CC8_DTC_DTE2_Pos (1UL) |
| |
| #define | CCU8_CC8_DTC_DTE2_Msk (0x2UL) |
| |
| #define | CCU8_CC8_DTC_DCEN1_Pos (2UL) |
| |
| #define | CCU8_CC8_DTC_DCEN1_Msk (0x4UL) |
| |
| #define | CCU8_CC8_DTC_DCEN2_Pos (3UL) |
| |
| #define | CCU8_CC8_DTC_DCEN2_Msk (0x8UL) |
| |
| #define | CCU8_CC8_DTC_DCEN3_Pos (4UL) |
| |
| #define | CCU8_CC8_DTC_DCEN3_Msk (0x10UL) |
| |
| #define | CCU8_CC8_DTC_DCEN4_Pos (5UL) |
| |
| #define | CCU8_CC8_DTC_DCEN4_Msk (0x20UL) |
| |
| #define | CCU8_CC8_DTC_DTCC_Pos (6UL) |
| |
| #define | CCU8_CC8_DTC_DTCC_Msk (0xc0UL) |
| |
| #define | CCU8_CC8_DC1R_DT1R_Pos (0UL) |
| |
| #define | CCU8_CC8_DC1R_DT1R_Msk (0xffUL) |
| |
| #define | CCU8_CC8_DC1R_DT1F_Pos (8UL) |
| |
| #define | CCU8_CC8_DC1R_DT1F_Msk (0xff00UL) |
| |
| #define | CCU8_CC8_DC2R_DT2R_Pos (0UL) |
| |
| #define | CCU8_CC8_DC2R_DT2R_Msk (0xffUL) |
| |
| #define | CCU8_CC8_DC2R_DT2F_Pos (8UL) |
| |
| #define | CCU8_CC8_DC2R_DT2F_Msk (0xff00UL) |
| |
| #define | CCU8_CC8_TIMER_TVAL_Pos (0UL) |
| |
| #define | CCU8_CC8_TIMER_TVAL_Msk (0xffffUL) |
| |
| #define | CCU8_CC8_CV_CAPTV_Pos (0UL) |
| |
| #define | CCU8_CC8_CV_CAPTV_Msk (0xffffUL) |
| |
| #define | CCU8_CC8_CV_FPCV_Pos (16UL) |
| |
| #define | CCU8_CC8_CV_FPCV_Msk (0xf0000UL) |
| |
| #define | CCU8_CC8_CV_FFL_Pos (20UL) |
| |
| #define | CCU8_CC8_CV_FFL_Msk (0x100000UL) |
| |
| #define | CCU8_CC8_INTS_PMUS_Pos (0UL) |
| |
| #define | CCU8_CC8_INTS_PMUS_Msk (0x1UL) |
| |
| #define | CCU8_CC8_INTS_OMDS_Pos (1UL) |
| |
| #define | CCU8_CC8_INTS_OMDS_Msk (0x2UL) |
| |
| #define | CCU8_CC8_INTS_CMU1S_Pos (2UL) |
| |
| #define | CCU8_CC8_INTS_CMU1S_Msk (0x4UL) |
| |
| #define | CCU8_CC8_INTS_CMD1S_Pos (3UL) |
| |
| #define | CCU8_CC8_INTS_CMD1S_Msk (0x8UL) |
| |
| #define | CCU8_CC8_INTS_CMU2S_Pos (4UL) |
| |
| #define | CCU8_CC8_INTS_CMU2S_Msk (0x10UL) |
| |
| #define | CCU8_CC8_INTS_CMD2S_Pos (5UL) |
| |
| #define | CCU8_CC8_INTS_CMD2S_Msk (0x20UL) |
| |
| #define | CCU8_CC8_INTS_E0AS_Pos (8UL) |
| |
| #define | CCU8_CC8_INTS_E0AS_Msk (0x100UL) |
| |
| #define | CCU8_CC8_INTS_E1AS_Pos (9UL) |
| |
| #define | CCU8_CC8_INTS_E1AS_Msk (0x200UL) |
| |
| #define | CCU8_CC8_INTS_E2AS_Pos (10UL) |
| |
| #define | CCU8_CC8_INTS_E2AS_Msk (0x400UL) |
| |
| #define | CCU8_CC8_INTS_TRPF_Pos (11UL) |
| |
| #define | CCU8_CC8_INTS_TRPF_Msk (0x800UL) |
| |
| #define | CCU8_CC8_INTE_PME_Pos (0UL) |
| |
| #define | CCU8_CC8_INTE_PME_Msk (0x1UL) |
| |
| #define | CCU8_CC8_INTE_OME_Pos (1UL) |
| |
| #define | CCU8_CC8_INTE_OME_Msk (0x2UL) |
| |
| #define | CCU8_CC8_INTE_CMU1E_Pos (2UL) |
| |
| #define | CCU8_CC8_INTE_CMU1E_Msk (0x4UL) |
| |
| #define | CCU8_CC8_INTE_CMD1E_Pos (3UL) |
| |
| #define | CCU8_CC8_INTE_CMD1E_Msk (0x8UL) |
| |
| #define | CCU8_CC8_INTE_CMU2E_Pos (4UL) |
| |
| #define | CCU8_CC8_INTE_CMU2E_Msk (0x10UL) |
| |
| #define | CCU8_CC8_INTE_CMD2E_Pos (5UL) |
| |
| #define | CCU8_CC8_INTE_CMD2E_Msk (0x20UL) |
| |
| #define | CCU8_CC8_INTE_E0AE_Pos (8UL) |
| |
| #define | CCU8_CC8_INTE_E0AE_Msk (0x100UL) |
| |
| #define | CCU8_CC8_INTE_E1AE_Pos (9UL) |
| |
| #define | CCU8_CC8_INTE_E1AE_Msk (0x200UL) |
| |
| #define | CCU8_CC8_INTE_E2AE_Pos (10UL) |
| |
| #define | CCU8_CC8_INTE_E2AE_Msk (0x400UL) |
| |
| #define | CCU8_CC8_SRS_POSR_Pos (0UL) |
| |
| #define | CCU8_CC8_SRS_POSR_Msk (0x3UL) |
| |
| #define | CCU8_CC8_SRS_CM1SR_Pos (2UL) |
| |
| #define | CCU8_CC8_SRS_CM1SR_Msk (0xcUL) |
| |
| #define | CCU8_CC8_SRS_CM2SR_Pos (4UL) |
| |
| #define | CCU8_CC8_SRS_CM2SR_Msk (0x30UL) |
| |
| #define | CCU8_CC8_SRS_E0SR_Pos (8UL) |
| |
| #define | CCU8_CC8_SRS_E0SR_Msk (0x300UL) |
| |
| #define | CCU8_CC8_SRS_E1SR_Pos (10UL) |
| |
| #define | CCU8_CC8_SRS_E1SR_Msk (0xc00UL) |
| |
| #define | CCU8_CC8_SRS_E2SR_Pos (12UL) |
| |
| #define | CCU8_CC8_SRS_E2SR_Msk (0x3000UL) |
| |
| #define | CCU8_CC8_SWS_SPM_Pos (0UL) |
| |
| #define | CCU8_CC8_SWS_SPM_Msk (0x1UL) |
| |
| #define | CCU8_CC8_SWS_SOM_Pos (1UL) |
| |
| #define | CCU8_CC8_SWS_SOM_Msk (0x2UL) |
| |
| #define | CCU8_CC8_SWS_SCM1U_Pos (2UL) |
| |
| #define | CCU8_CC8_SWS_SCM1U_Msk (0x4UL) |
| |
| #define | CCU8_CC8_SWS_SCM1D_Pos (3UL) |
| |
| #define | CCU8_CC8_SWS_SCM1D_Msk (0x8UL) |
| |
| #define | CCU8_CC8_SWS_SCM2U_Pos (4UL) |
| |
| #define | CCU8_CC8_SWS_SCM2U_Msk (0x10UL) |
| |
| #define | CCU8_CC8_SWS_SCM2D_Pos (5UL) |
| |
| #define | CCU8_CC8_SWS_SCM2D_Msk (0x20UL) |
| |
| #define | CCU8_CC8_SWS_SE0A_Pos (8UL) |
| |
| #define | CCU8_CC8_SWS_SE0A_Msk (0x100UL) |
| |
| #define | CCU8_CC8_SWS_SE1A_Pos (9UL) |
| |
| #define | CCU8_CC8_SWS_SE1A_Msk (0x200UL) |
| |
| #define | CCU8_CC8_SWS_SE2A_Pos (10UL) |
| |
| #define | CCU8_CC8_SWS_SE2A_Msk (0x400UL) |
| |
| #define | CCU8_CC8_SWS_STRPF_Pos (11UL) |
| |
| #define | CCU8_CC8_SWS_STRPF_Msk (0x800UL) |
| |
| #define | CCU8_CC8_SWR_RPM_Pos (0UL) |
| |
| #define | CCU8_CC8_SWR_RPM_Msk (0x1UL) |
| |
| #define | CCU8_CC8_SWR_ROM_Pos (1UL) |
| |
| #define | CCU8_CC8_SWR_ROM_Msk (0x2UL) |
| |
| #define | CCU8_CC8_SWR_RCM1U_Pos (2UL) |
| |
| #define | CCU8_CC8_SWR_RCM1U_Msk (0x4UL) |
| |
| #define | CCU8_CC8_SWR_RCM1D_Pos (3UL) |
| |
| #define | CCU8_CC8_SWR_RCM1D_Msk (0x8UL) |
| |
| #define | CCU8_CC8_SWR_RCM2U_Pos (4UL) |
| |
| #define | CCU8_CC8_SWR_RCM2U_Msk (0x10UL) |
| |
| #define | CCU8_CC8_SWR_RCM2D_Pos (5UL) |
| |
| #define | CCU8_CC8_SWR_RCM2D_Msk (0x20UL) |
| |
| #define | CCU8_CC8_SWR_RE0A_Pos (8UL) |
| |
| #define | CCU8_CC8_SWR_RE0A_Msk (0x100UL) |
| |
| #define | CCU8_CC8_SWR_RE1A_Pos (9UL) |
| |
| #define | CCU8_CC8_SWR_RE1A_Msk (0x200UL) |
| |
| #define | CCU8_CC8_SWR_RE2A_Pos (10UL) |
| |
| #define | CCU8_CC8_SWR_RE2A_Msk (0x400UL) |
| |
| #define | CCU8_CC8_SWR_RTRPF_Pos (11UL) |
| |
| #define | CCU8_CC8_SWR_RTRPF_Msk (0x800UL) |
| |
| #define | CCU8_CC8_STC_CSE_Pos (0UL) |
| |
| #define | CCU8_CC8_STC_CSE_Msk (0x1UL) |
| |
| #define | CCU8_CC8_STC_STM_Pos (1UL) |
| |
| #define | CCU8_CC8_STC_STM_Msk (0x6UL) |
| |
| #define | CCU8_CC8_ECRD0_CAPV_Pos (0UL) |
| |
| #define | CCU8_CC8_ECRD0_CAPV_Msk (0xffffUL) |
| |
| #define | CCU8_CC8_ECRD0_FPCV_Pos (16UL) |
| |
| #define | CCU8_CC8_ECRD0_FPCV_Msk (0xf0000UL) |
| |
| #define | CCU8_CC8_ECRD0_SPTR_Pos (20UL) |
| |
| #define | CCU8_CC8_ECRD0_SPTR_Msk (0x300000UL) |
| |
| #define | CCU8_CC8_ECRD0_VPTR_Pos (22UL) |
| |
| #define | CCU8_CC8_ECRD0_VPTR_Msk (0xc00000UL) |
| |
| #define | CCU8_CC8_ECRD0_FFL_Pos (24UL) |
| |
| #define | CCU8_CC8_ECRD0_FFL_Msk (0x1000000UL) |
| |
| #define | CCU8_CC8_ECRD0_LCV_Pos (25UL) |
| |
| #define | CCU8_CC8_ECRD0_LCV_Msk (0x2000000UL) |
| |
| #define | CCU8_CC8_ECRD1_CAPV_Pos (0UL) |
| |
| #define | CCU8_CC8_ECRD1_CAPV_Msk (0xffffUL) |
| |
| #define | CCU8_CC8_ECRD1_FPCV_Pos (16UL) |
| |
| #define | CCU8_CC8_ECRD1_FPCV_Msk (0xf0000UL) |
| |
| #define | CCU8_CC8_ECRD1_SPTR_Pos (20UL) |
| |
| #define | CCU8_CC8_ECRD1_SPTR_Msk (0x300000UL) |
| |
| #define | CCU8_CC8_ECRD1_VPTR_Pos (22UL) |
| |
| #define | CCU8_CC8_ECRD1_VPTR_Msk (0xc00000UL) |
| |
| #define | CCU8_CC8_ECRD1_FFL_Pos (24UL) |
| |
| #define | CCU8_CC8_ECRD1_FFL_Msk (0x1000000UL) |
| |
| #define | CCU8_CC8_ECRD1_LCV_Pos (25UL) |
| |
| #define | CCU8_CC8_ECRD1_LCV_Msk (0x2000000UL) |
| |
| #define | POSIF_PCONF_FSEL_Pos (0UL) |
| |
| #define | POSIF_PCONF_FSEL_Msk (0x3UL) |
| |
| #define | POSIF_PCONF_QDCM_Pos (2UL) |
| |
| #define | POSIF_PCONF_QDCM_Msk (0x4UL) |
| |
| #define | POSIF_PCONF_HIDG_Pos (4UL) |
| |
| #define | POSIF_PCONF_HIDG_Msk (0x10UL) |
| |
| #define | POSIF_PCONF_MCUE_Pos (5UL) |
| |
| #define | POSIF_PCONF_MCUE_Msk (0x20UL) |
| |
| #define | POSIF_PCONF_INSEL0_Pos (8UL) |
| |
| #define | POSIF_PCONF_INSEL0_Msk (0x300UL) |
| |
| #define | POSIF_PCONF_INSEL1_Pos (10UL) |
| |
| #define | POSIF_PCONF_INSEL1_Msk (0xc00UL) |
| |
| #define | POSIF_PCONF_INSEL2_Pos (12UL) |
| |
| #define | POSIF_PCONF_INSEL2_Msk (0x3000UL) |
| |
| #define | POSIF_PCONF_DSEL_Pos (16UL) |
| |
| #define | POSIF_PCONF_DSEL_Msk (0x10000UL) |
| |
| #define | POSIF_PCONF_SPES_Pos (17UL) |
| |
| #define | POSIF_PCONF_SPES_Msk (0x20000UL) |
| |
| #define | POSIF_PCONF_MSETS_Pos (18UL) |
| |
| #define | POSIF_PCONF_MSETS_Msk (0x1c0000UL) |
| |
| #define | POSIF_PCONF_MSES_Pos (21UL) |
| |
| #define | POSIF_PCONF_MSES_Msk (0x200000UL) |
| |
| #define | POSIF_PCONF_MSYNS_Pos (22UL) |
| |
| #define | POSIF_PCONF_MSYNS_Msk (0xc00000UL) |
| |
| #define | POSIF_PCONF_EWIS_Pos (24UL) |
| |
| #define | POSIF_PCONF_EWIS_Msk (0x3000000UL) |
| |
| #define | POSIF_PCONF_EWIE_Pos (26UL) |
| |
| #define | POSIF_PCONF_EWIE_Msk (0x4000000UL) |
| |
| #define | POSIF_PCONF_EWIL_Pos (27UL) |
| |
| #define | POSIF_PCONF_EWIL_Msk (0x8000000UL) |
| |
| #define | POSIF_PCONF_LPC_Pos (28UL) |
| |
| #define | POSIF_PCONF_LPC_Msk (0x70000000UL) |
| |
| #define | POSIF_PSUS_QSUS_Pos (0UL) |
| |
| #define | POSIF_PSUS_QSUS_Msk (0x3UL) |
| |
| #define | POSIF_PSUS_MSUS_Pos (2UL) |
| |
| #define | POSIF_PSUS_MSUS_Msk (0xcUL) |
| |
| #define | POSIF_PRUNS_SRB_Pos (0UL) |
| |
| #define | POSIF_PRUNS_SRB_Msk (0x1UL) |
| |
| #define | POSIF_PRUNC_CRB_Pos (0UL) |
| |
| #define | POSIF_PRUNC_CRB_Msk (0x1UL) |
| |
| #define | POSIF_PRUNC_CSM_Pos (1UL) |
| |
| #define | POSIF_PRUNC_CSM_Msk (0x2UL) |
| |
| #define | POSIF_PRUN_RB_Pos (0UL) |
| |
| #define | POSIF_PRUN_RB_Msk (0x1UL) |
| |
| #define | POSIF_MIDR_MODR_Pos (0UL) |
| |
| #define | POSIF_MIDR_MODR_Msk (0xffUL) |
| |
| #define | POSIF_MIDR_MODT_Pos (8UL) |
| |
| #define | POSIF_MIDR_MODT_Msk (0xff00UL) |
| |
| #define | POSIF_MIDR_MODN_Pos (16UL) |
| |
| #define | POSIF_MIDR_MODN_Msk (0xffff0000UL) |
| |
| #define | POSIF_HALP_HCP_Pos (0UL) |
| |
| #define | POSIF_HALP_HCP_Msk (0x7UL) |
| |
| #define | POSIF_HALP_HEP_Pos (3UL) |
| |
| #define | POSIF_HALP_HEP_Msk (0x38UL) |
| |
| #define | POSIF_HALPS_HCPS_Pos (0UL) |
| |
| #define | POSIF_HALPS_HCPS_Msk (0x7UL) |
| |
| #define | POSIF_HALPS_HEPS_Pos (3UL) |
| |
| #define | POSIF_HALPS_HEPS_Msk (0x38UL) |
| |
| #define | POSIF_MCM_MCMP_Pos (0UL) |
| |
| #define | POSIF_MCM_MCMP_Msk (0xffffUL) |
| |
| #define | POSIF_MCSM_MCMPS_Pos (0UL) |
| |
| #define | POSIF_MCSM_MCMPS_Msk (0xffffUL) |
| |
| #define | POSIF_MCMS_MNPS_Pos (0UL) |
| |
| #define | POSIF_MCMS_MNPS_Msk (0x1UL) |
| |
| #define | POSIF_MCMS_STHR_Pos (1UL) |
| |
| #define | POSIF_MCMS_STHR_Msk (0x2UL) |
| |
| #define | POSIF_MCMS_STMR_Pos (2UL) |
| |
| #define | POSIF_MCMS_STMR_Msk (0x4UL) |
| |
| #define | POSIF_MCMC_MNPC_Pos (0UL) |
| |
| #define | POSIF_MCMC_MNPC_Msk (0x1UL) |
| |
| #define | POSIF_MCMC_MPC_Pos (1UL) |
| |
| #define | POSIF_MCMC_MPC_Msk (0x2UL) |
| |
| #define | POSIF_MCMF_MSS_Pos (0UL) |
| |
| #define | POSIF_MCMF_MSS_Msk (0x1UL) |
| |
| #define | POSIF_QDC_PALS_Pos (0UL) |
| |
| #define | POSIF_QDC_PALS_Msk (0x1UL) |
| |
| #define | POSIF_QDC_PBLS_Pos (1UL) |
| |
| #define | POSIF_QDC_PBLS_Msk (0x2UL) |
| |
| #define | POSIF_QDC_PHS_Pos (2UL) |
| |
| #define | POSIF_QDC_PHS_Msk (0x4UL) |
| |
| #define | POSIF_QDC_ICM_Pos (4UL) |
| |
| #define | POSIF_QDC_ICM_Msk (0x30UL) |
| |
| #define | POSIF_QDC_DVAL_Pos (8UL) |
| |
| #define | POSIF_QDC_DVAL_Msk (0x100UL) |
| |
| #define | POSIF_PFLG_CHES_Pos (0UL) |
| |
| #define | POSIF_PFLG_CHES_Msk (0x1UL) |
| |
| #define | POSIF_PFLG_WHES_Pos (1UL) |
| |
| #define | POSIF_PFLG_WHES_Msk (0x2UL) |
| |
| #define | POSIF_PFLG_HIES_Pos (2UL) |
| |
| #define | POSIF_PFLG_HIES_Msk (0x4UL) |
| |
| #define | POSIF_PFLG_MSTS_Pos (4UL) |
| |
| #define | POSIF_PFLG_MSTS_Msk (0x10UL) |
| |
| #define | POSIF_PFLG_INDXS_Pos (8UL) |
| |
| #define | POSIF_PFLG_INDXS_Msk (0x100UL) |
| |
| #define | POSIF_PFLG_ERRS_Pos (9UL) |
| |
| #define | POSIF_PFLG_ERRS_Msk (0x200UL) |
| |
| #define | POSIF_PFLG_CNTS_Pos (10UL) |
| |
| #define | POSIF_PFLG_CNTS_Msk (0x400UL) |
| |
| #define | POSIF_PFLG_DIRS_Pos (11UL) |
| |
| #define | POSIF_PFLG_DIRS_Msk (0x800UL) |
| |
| #define | POSIF_PFLG_PCLKS_Pos (12UL) |
| |
| #define | POSIF_PFLG_PCLKS_Msk (0x1000UL) |
| |
| #define | POSIF_PFLGE_ECHE_Pos (0UL) |
| |
| #define | POSIF_PFLGE_ECHE_Msk (0x1UL) |
| |
| #define | POSIF_PFLGE_EWHE_Pos (1UL) |
| |
| #define | POSIF_PFLGE_EWHE_Msk (0x2UL) |
| |
| #define | POSIF_PFLGE_EHIE_Pos (2UL) |
| |
| #define | POSIF_PFLGE_EHIE_Msk (0x4UL) |
| |
| #define | POSIF_PFLGE_EMST_Pos (4UL) |
| |
| #define | POSIF_PFLGE_EMST_Msk (0x10UL) |
| |
| #define | POSIF_PFLGE_EINDX_Pos (8UL) |
| |
| #define | POSIF_PFLGE_EINDX_Msk (0x100UL) |
| |
| #define | POSIF_PFLGE_EERR_Pos (9UL) |
| |
| #define | POSIF_PFLGE_EERR_Msk (0x200UL) |
| |
| #define | POSIF_PFLGE_ECNT_Pos (10UL) |
| |
| #define | POSIF_PFLGE_ECNT_Msk (0x400UL) |
| |
| #define | POSIF_PFLGE_EDIR_Pos (11UL) |
| |
| #define | POSIF_PFLGE_EDIR_Msk (0x800UL) |
| |
| #define | POSIF_PFLGE_EPCLK_Pos (12UL) |
| |
| #define | POSIF_PFLGE_EPCLK_Msk (0x1000UL) |
| |
| #define | POSIF_PFLGE_CHESEL_Pos (16UL) |
| |
| #define | POSIF_PFLGE_CHESEL_Msk (0x10000UL) |
| |
| #define | POSIF_PFLGE_WHESEL_Pos (17UL) |
| |
| #define | POSIF_PFLGE_WHESEL_Msk (0x20000UL) |
| |
| #define | POSIF_PFLGE_HIESEL_Pos (18UL) |
| |
| #define | POSIF_PFLGE_HIESEL_Msk (0x40000UL) |
| |
| #define | POSIF_PFLGE_MSTSEL_Pos (20UL) |
| |
| #define | POSIF_PFLGE_MSTSEL_Msk (0x100000UL) |
| |
| #define | POSIF_PFLGE_INDSEL_Pos (24UL) |
| |
| #define | POSIF_PFLGE_INDSEL_Msk (0x1000000UL) |
| |
| #define | POSIF_PFLGE_ERRSEL_Pos (25UL) |
| |
| #define | POSIF_PFLGE_ERRSEL_Msk (0x2000000UL) |
| |
| #define | POSIF_PFLGE_CNTSEL_Pos (26UL) |
| |
| #define | POSIF_PFLGE_CNTSEL_Msk (0x4000000UL) |
| |
| #define | POSIF_PFLGE_DIRSEL_Pos (27UL) |
| |
| #define | POSIF_PFLGE_DIRSEL_Msk (0x8000000UL) |
| |
| #define | POSIF_PFLGE_PCLSEL_Pos (28UL) |
| |
| #define | POSIF_PFLGE_PCLSEL_Msk (0x10000000UL) |
| |
| #define | POSIF_SPFLG_SCHE_Pos (0UL) |
| |
| #define | POSIF_SPFLG_SCHE_Msk (0x1UL) |
| |
| #define | POSIF_SPFLG_SWHE_Pos (1UL) |
| |
| #define | POSIF_SPFLG_SWHE_Msk (0x2UL) |
| |
| #define | POSIF_SPFLG_SHIE_Pos (2UL) |
| |
| #define | POSIF_SPFLG_SHIE_Msk (0x4UL) |
| |
| #define | POSIF_SPFLG_SMST_Pos (4UL) |
| |
| #define | POSIF_SPFLG_SMST_Msk (0x10UL) |
| |
| #define | POSIF_SPFLG_SINDX_Pos (8UL) |
| |
| #define | POSIF_SPFLG_SINDX_Msk (0x100UL) |
| |
| #define | POSIF_SPFLG_SERR_Pos (9UL) |
| |
| #define | POSIF_SPFLG_SERR_Msk (0x200UL) |
| |
| #define | POSIF_SPFLG_SCNT_Pos (10UL) |
| |
| #define | POSIF_SPFLG_SCNT_Msk (0x400UL) |
| |
| #define | POSIF_SPFLG_SDIR_Pos (11UL) |
| |
| #define | POSIF_SPFLG_SDIR_Msk (0x800UL) |
| |
| #define | POSIF_SPFLG_SPCLK_Pos (12UL) |
| |
| #define | POSIF_SPFLG_SPCLK_Msk (0x1000UL) |
| |
| #define | POSIF_RPFLG_RCHE_Pos (0UL) |
| |
| #define | POSIF_RPFLG_RCHE_Msk (0x1UL) |
| |
| #define | POSIF_RPFLG_RWHE_Pos (1UL) |
| |
| #define | POSIF_RPFLG_RWHE_Msk (0x2UL) |
| |
| #define | POSIF_RPFLG_RHIE_Pos (2UL) |
| |
| #define | POSIF_RPFLG_RHIE_Msk (0x4UL) |
| |
| #define | POSIF_RPFLG_RMST_Pos (4UL) |
| |
| #define | POSIF_RPFLG_RMST_Msk (0x10UL) |
| |
| #define | POSIF_RPFLG_RINDX_Pos (8UL) |
| |
| #define | POSIF_RPFLG_RINDX_Msk (0x100UL) |
| |
| #define | POSIF_RPFLG_RERR_Pos (9UL) |
| |
| #define | POSIF_RPFLG_RERR_Msk (0x200UL) |
| |
| #define | POSIF_RPFLG_RCNT_Pos (10UL) |
| |
| #define | POSIF_RPFLG_RCNT_Msk (0x400UL) |
| |
| #define | POSIF_RPFLG_RDIR_Pos (11UL) |
| |
| #define | POSIF_RPFLG_RDIR_Msk (0x800UL) |
| |
| #define | POSIF_RPFLG_RPCLK_Pos (12UL) |
| |
| #define | POSIF_RPFLG_RPCLK_Msk (0x1000UL) |
| |
| #define | POSIF_PDBG_QCSV_Pos (0UL) |
| |
| #define | POSIF_PDBG_QCSV_Msk (0x3UL) |
| |
| #define | POSIF_PDBG_QPSV_Pos (2UL) |
| |
| #define | POSIF_PDBG_QPSV_Msk (0xcUL) |
| |
| #define | POSIF_PDBG_IVAL_Pos (4UL) |
| |
| #define | POSIF_PDBG_IVAL_Msk (0x10UL) |
| |
| #define | POSIF_PDBG_HSP_Pos (5UL) |
| |
| #define | POSIF_PDBG_HSP_Msk (0xe0UL) |
| |
| #define | POSIF_PDBG_LPP0_Pos (8UL) |
| |
| #define | POSIF_PDBG_LPP0_Msk (0x3f00UL) |
| |
| #define | POSIF_PDBG_LPP1_Pos (16UL) |
| |
| #define | POSIF_PDBG_LPP1_Msk (0x3f0000UL) |
| |
| #define | POSIF_PDBG_LPP2_Pos (22UL) |
| |
| #define | POSIF_PDBG_LPP2_Msk (0xfc00000UL) |
| |
| #define | PORT0_OUT_P0_Pos (0UL) |
| |
| #define | PORT0_OUT_P0_Msk (0x1UL) |
| |
| #define | PORT0_OUT_P1_Pos (1UL) |
| |
| #define | PORT0_OUT_P1_Msk (0x2UL) |
| |
| #define | PORT0_OUT_P2_Pos (2UL) |
| |
| #define | PORT0_OUT_P2_Msk (0x4UL) |
| |
| #define | PORT0_OUT_P3_Pos (3UL) |
| |
| #define | PORT0_OUT_P3_Msk (0x8UL) |
| |
| #define | PORT0_OUT_P4_Pos (4UL) |
| |
| #define | PORT0_OUT_P4_Msk (0x10UL) |
| |
| #define | PORT0_OUT_P5_Pos (5UL) |
| |
| #define | PORT0_OUT_P5_Msk (0x20UL) |
| |
| #define | PORT0_OUT_P6_Pos (6UL) |
| |
| #define | PORT0_OUT_P6_Msk (0x40UL) |
| |
| #define | PORT0_OUT_P7_Pos (7UL) |
| |
| #define | PORT0_OUT_P7_Msk (0x80UL) |
| |
| #define | PORT0_OUT_P8_Pos (8UL) |
| |
| #define | PORT0_OUT_P8_Msk (0x100UL) |
| |
| #define | PORT0_OUT_P9_Pos (9UL) |
| |
| #define | PORT0_OUT_P9_Msk (0x200UL) |
| |
| #define | PORT0_OUT_P10_Pos (10UL) |
| |
| #define | PORT0_OUT_P10_Msk (0x400UL) |
| |
| #define | PORT0_OUT_P11_Pos (11UL) |
| |
| #define | PORT0_OUT_P11_Msk (0x800UL) |
| |
| #define | PORT0_OUT_P12_Pos (12UL) |
| |
| #define | PORT0_OUT_P12_Msk (0x1000UL) |
| |
| #define | PORT0_OUT_P13_Pos (13UL) |
| |
| #define | PORT0_OUT_P13_Msk (0x2000UL) |
| |
| #define | PORT0_OUT_P14_Pos (14UL) |
| |
| #define | PORT0_OUT_P14_Msk (0x4000UL) |
| |
| #define | PORT0_OUT_P15_Pos (15UL) |
| |
| #define | PORT0_OUT_P15_Msk (0x8000UL) |
| |
| #define | PORT0_OMR_PS0_Pos (0UL) |
| |
| #define | PORT0_OMR_PS0_Msk (0x1UL) |
| |
| #define | PORT0_OMR_PS1_Pos (1UL) |
| |
| #define | PORT0_OMR_PS1_Msk (0x2UL) |
| |
| #define | PORT0_OMR_PS2_Pos (2UL) |
| |
| #define | PORT0_OMR_PS2_Msk (0x4UL) |
| |
| #define | PORT0_OMR_PS3_Pos (3UL) |
| |
| #define | PORT0_OMR_PS3_Msk (0x8UL) |
| |
| #define | PORT0_OMR_PS4_Pos (4UL) |
| |
| #define | PORT0_OMR_PS4_Msk (0x10UL) |
| |
| #define | PORT0_OMR_PS5_Pos (5UL) |
| |
| #define | PORT0_OMR_PS5_Msk (0x20UL) |
| |
| #define | PORT0_OMR_PS6_Pos (6UL) |
| |
| #define | PORT0_OMR_PS6_Msk (0x40UL) |
| |
| #define | PORT0_OMR_PS7_Pos (7UL) |
| |
| #define | PORT0_OMR_PS7_Msk (0x80UL) |
| |
| #define | PORT0_OMR_PS8_Pos (8UL) |
| |
| #define | PORT0_OMR_PS8_Msk (0x100UL) |
| |
| #define | PORT0_OMR_PS9_Pos (9UL) |
| |
| #define | PORT0_OMR_PS9_Msk (0x200UL) |
| |
| #define | PORT0_OMR_PS10_Pos (10UL) |
| |
| #define | PORT0_OMR_PS10_Msk (0x400UL) |
| |
| #define | PORT0_OMR_PS11_Pos (11UL) |
| |
| #define | PORT0_OMR_PS11_Msk (0x800UL) |
| |
| #define | PORT0_OMR_PS12_Pos (12UL) |
| |
| #define | PORT0_OMR_PS12_Msk (0x1000UL) |
| |
| #define | PORT0_OMR_PS13_Pos (13UL) |
| |
| #define | PORT0_OMR_PS13_Msk (0x2000UL) |
| |
| #define | PORT0_OMR_PS14_Pos (14UL) |
| |
| #define | PORT0_OMR_PS14_Msk (0x4000UL) |
| |
| #define | PORT0_OMR_PS15_Pos (15UL) |
| |
| #define | PORT0_OMR_PS15_Msk (0x8000UL) |
| |
| #define | PORT0_OMR_PR0_Pos (16UL) |
| |
| #define | PORT0_OMR_PR0_Msk (0x10000UL) |
| |
| #define | PORT0_OMR_PR1_Pos (17UL) |
| |
| #define | PORT0_OMR_PR1_Msk (0x20000UL) |
| |
| #define | PORT0_OMR_PR2_Pos (18UL) |
| |
| #define | PORT0_OMR_PR2_Msk (0x40000UL) |
| |
| #define | PORT0_OMR_PR3_Pos (19UL) |
| |
| #define | PORT0_OMR_PR3_Msk (0x80000UL) |
| |
| #define | PORT0_OMR_PR4_Pos (20UL) |
| |
| #define | PORT0_OMR_PR4_Msk (0x100000UL) |
| |
| #define | PORT0_OMR_PR5_Pos (21UL) |
| |
| #define | PORT0_OMR_PR5_Msk (0x200000UL) |
| |
| #define | PORT0_OMR_PR6_Pos (22UL) |
| |
| #define | PORT0_OMR_PR6_Msk (0x400000UL) |
| |
| #define | PORT0_OMR_PR7_Pos (23UL) |
| |
| #define | PORT0_OMR_PR7_Msk (0x800000UL) |
| |
| #define | PORT0_OMR_PR8_Pos (24UL) |
| |
| #define | PORT0_OMR_PR8_Msk (0x1000000UL) |
| |
| #define | PORT0_OMR_PR9_Pos (25UL) |
| |
| #define | PORT0_OMR_PR9_Msk (0x2000000UL) |
| |
| #define | PORT0_OMR_PR10_Pos (26UL) |
| |
| #define | PORT0_OMR_PR10_Msk (0x4000000UL) |
| |
| #define | PORT0_OMR_PR11_Pos (27UL) |
| |
| #define | PORT0_OMR_PR11_Msk (0x8000000UL) |
| |
| #define | PORT0_OMR_PR12_Pos (28UL) |
| |
| #define | PORT0_OMR_PR12_Msk (0x10000000UL) |
| |
| #define | PORT0_OMR_PR13_Pos (29UL) |
| |
| #define | PORT0_OMR_PR13_Msk (0x20000000UL) |
| |
| #define | PORT0_OMR_PR14_Pos (30UL) |
| |
| #define | PORT0_OMR_PR14_Msk (0x40000000UL) |
| |
| #define | PORT0_OMR_PR15_Pos (31UL) |
| |
| #define | PORT0_OMR_PR15_Msk (0x80000000UL) |
| |
| #define | PORT0_IOCR0_PC0_Pos (3UL) |
| |
| #define | PORT0_IOCR0_PC0_Msk (0xf8UL) |
| |
| #define | PORT0_IOCR0_PC1_Pos (11UL) |
| |
| #define | PORT0_IOCR0_PC1_Msk (0xf800UL) |
| |
| #define | PORT0_IOCR0_PC2_Pos (19UL) |
| |
| #define | PORT0_IOCR0_PC2_Msk (0xf80000UL) |
| |
| #define | PORT0_IOCR0_PC3_Pos (27UL) |
| |
| #define | PORT0_IOCR0_PC3_Msk (0xf8000000UL) |
| |
| #define | PORT0_IOCR4_PC4_Pos (3UL) |
| |
| #define | PORT0_IOCR4_PC4_Msk (0xf8UL) |
| |
| #define | PORT0_IOCR4_PC5_Pos (11UL) |
| |
| #define | PORT0_IOCR4_PC5_Msk (0xf800UL) |
| |
| #define | PORT0_IOCR4_PC6_Pos (19UL) |
| |
| #define | PORT0_IOCR4_PC6_Msk (0xf80000UL) |
| |
| #define | PORT0_IOCR4_PC7_Pos (27UL) |
| |
| #define | PORT0_IOCR4_PC7_Msk (0xf8000000UL) |
| |
| #define | PORT0_IOCR8_PC8_Pos (3UL) |
| |
| #define | PORT0_IOCR8_PC8_Msk (0xf8UL) |
| |
| #define | PORT0_IOCR8_PC9_Pos (11UL) |
| |
| #define | PORT0_IOCR8_PC9_Msk (0xf800UL) |
| |
| #define | PORT0_IOCR8_PC10_Pos (19UL) |
| |
| #define | PORT0_IOCR8_PC10_Msk (0xf80000UL) |
| |
| #define | PORT0_IOCR8_PC11_Pos (27UL) |
| |
| #define | PORT0_IOCR8_PC11_Msk (0xf8000000UL) |
| |
| #define | PORT0_IOCR12_PC12_Pos (3UL) |
| |
| #define | PORT0_IOCR12_PC12_Msk (0xf8UL) |
| |
| #define | PORT0_IOCR12_PC13_Pos (11UL) |
| |
| #define | PORT0_IOCR12_PC13_Msk (0xf800UL) |
| |
| #define | PORT0_IOCR12_PC14_Pos (19UL) |
| |
| #define | PORT0_IOCR12_PC14_Msk (0xf80000UL) |
| |
| #define | PORT0_IOCR12_PC15_Pos (27UL) |
| |
| #define | PORT0_IOCR12_PC15_Msk (0xf8000000UL) |
| |
| #define | PORT0_IN_P0_Pos (0UL) |
| |
| #define | PORT0_IN_P0_Msk (0x1UL) |
| |
| #define | PORT0_IN_P1_Pos (1UL) |
| |
| #define | PORT0_IN_P1_Msk (0x2UL) |
| |
| #define | PORT0_IN_P2_Pos (2UL) |
| |
| #define | PORT0_IN_P2_Msk (0x4UL) |
| |
| #define | PORT0_IN_P3_Pos (3UL) |
| |
| #define | PORT0_IN_P3_Msk (0x8UL) |
| |
| #define | PORT0_IN_P4_Pos (4UL) |
| |
| #define | PORT0_IN_P4_Msk (0x10UL) |
| |
| #define | PORT0_IN_P5_Pos (5UL) |
| |
| #define | PORT0_IN_P5_Msk (0x20UL) |
| |
| #define | PORT0_IN_P6_Pos (6UL) |
| |
| #define | PORT0_IN_P6_Msk (0x40UL) |
| |
| #define | PORT0_IN_P7_Pos (7UL) |
| |
| #define | PORT0_IN_P7_Msk (0x80UL) |
| |
| #define | PORT0_IN_P8_Pos (8UL) |
| |
| #define | PORT0_IN_P8_Msk (0x100UL) |
| |
| #define | PORT0_IN_P9_Pos (9UL) |
| |
| #define | PORT0_IN_P9_Msk (0x200UL) |
| |
| #define | PORT0_IN_P10_Pos (10UL) |
| |
| #define | PORT0_IN_P10_Msk (0x400UL) |
| |
| #define | PORT0_IN_P11_Pos (11UL) |
| |
| #define | PORT0_IN_P11_Msk (0x800UL) |
| |
| #define | PORT0_IN_P12_Pos (12UL) |
| |
| #define | PORT0_IN_P12_Msk (0x1000UL) |
| |
| #define | PORT0_IN_P13_Pos (13UL) |
| |
| #define | PORT0_IN_P13_Msk (0x2000UL) |
| |
| #define | PORT0_IN_P14_Pos (14UL) |
| |
| #define | PORT0_IN_P14_Msk (0x4000UL) |
| |
| #define | PORT0_IN_P15_Pos (15UL) |
| |
| #define | PORT0_IN_P15_Msk (0x8000UL) |
| |
| #define | PORT0_PDR0_PD0_Pos (0UL) |
| |
| #define | PORT0_PDR0_PD0_Msk (0x7UL) |
| |
| #define | PORT0_PDR0_PD1_Pos (4UL) |
| |
| #define | PORT0_PDR0_PD1_Msk (0x70UL) |
| |
| #define | PORT0_PDR0_PD2_Pos (8UL) |
| |
| #define | PORT0_PDR0_PD2_Msk (0x700UL) |
| |
| #define | PORT0_PDR0_PD3_Pos (12UL) |
| |
| #define | PORT0_PDR0_PD3_Msk (0x7000UL) |
| |
| #define | PORT0_PDR0_PD4_Pos (16UL) |
| |
| #define | PORT0_PDR0_PD4_Msk (0x70000UL) |
| |
| #define | PORT0_PDR0_PD5_Pos (20UL) |
| |
| #define | PORT0_PDR0_PD5_Msk (0x700000UL) |
| |
| #define | PORT0_PDR0_PD6_Pos (24UL) |
| |
| #define | PORT0_PDR0_PD6_Msk (0x7000000UL) |
| |
| #define | PORT0_PDR0_PD7_Pos (28UL) |
| |
| #define | PORT0_PDR0_PD7_Msk (0x70000000UL) |
| |
| #define | PORT0_PDR1_PD8_Pos (0UL) |
| |
| #define | PORT0_PDR1_PD8_Msk (0x7UL) |
| |
| #define | PORT0_PDR1_PD9_Pos (4UL) |
| |
| #define | PORT0_PDR1_PD9_Msk (0x70UL) |
| |
| #define | PORT0_PDR1_PD10_Pos (8UL) |
| |
| #define | PORT0_PDR1_PD10_Msk (0x700UL) |
| |
| #define | PORT0_PDR1_PD11_Pos (12UL) |
| |
| #define | PORT0_PDR1_PD11_Msk (0x7000UL) |
| |
| #define | PORT0_PDR1_PD12_Pos (16UL) |
| |
| #define | PORT0_PDR1_PD12_Msk (0x70000UL) |
| |
| #define | PORT0_PDR1_PD13_Pos (20UL) |
| |
| #define | PORT0_PDR1_PD13_Msk (0x700000UL) |
| |
| #define | PORT0_PDR1_PD14_Pos (24UL) |
| |
| #define | PORT0_PDR1_PD14_Msk (0x7000000UL) |
| |
| #define | PORT0_PDR1_PD15_Pos (28UL) |
| |
| #define | PORT0_PDR1_PD15_Msk (0x70000000UL) |
| |
| #define | PORT0_PDISC_PDIS0_Pos (0UL) |
| |
| #define | PORT0_PDISC_PDIS0_Msk (0x1UL) |
| |
| #define | PORT0_PDISC_PDIS1_Pos (1UL) |
| |
| #define | PORT0_PDISC_PDIS1_Msk (0x2UL) |
| |
| #define | PORT0_PDISC_PDIS2_Pos (2UL) |
| |
| #define | PORT0_PDISC_PDIS2_Msk (0x4UL) |
| |
| #define | PORT0_PDISC_PDIS3_Pos (3UL) |
| |
| #define | PORT0_PDISC_PDIS3_Msk (0x8UL) |
| |
| #define | PORT0_PDISC_PDIS4_Pos (4UL) |
| |
| #define | PORT0_PDISC_PDIS4_Msk (0x10UL) |
| |
| #define | PORT0_PDISC_PDIS5_Pos (5UL) |
| |
| #define | PORT0_PDISC_PDIS5_Msk (0x20UL) |
| |
| #define | PORT0_PDISC_PDIS6_Pos (6UL) |
| |
| #define | PORT0_PDISC_PDIS6_Msk (0x40UL) |
| |
| #define | PORT0_PDISC_PDIS7_Pos (7UL) |
| |
| #define | PORT0_PDISC_PDIS7_Msk (0x80UL) |
| |
| #define | PORT0_PDISC_PDIS8_Pos (8UL) |
| |
| #define | PORT0_PDISC_PDIS8_Msk (0x100UL) |
| |
| #define | PORT0_PDISC_PDIS9_Pos (9UL) |
| |
| #define | PORT0_PDISC_PDIS9_Msk (0x200UL) |
| |
| #define | PORT0_PDISC_PDIS10_Pos (10UL) |
| |
| #define | PORT0_PDISC_PDIS10_Msk (0x400UL) |
| |
| #define | PORT0_PDISC_PDIS11_Pos (11UL) |
| |
| #define | PORT0_PDISC_PDIS11_Msk (0x800UL) |
| |
| #define | PORT0_PDISC_PDIS12_Pos (12UL) |
| |
| #define | PORT0_PDISC_PDIS12_Msk (0x1000UL) |
| |
| #define | PORT0_PDISC_PDIS13_Pos (13UL) |
| |
| #define | PORT0_PDISC_PDIS13_Msk (0x2000UL) |
| |
| #define | PORT0_PDISC_PDIS14_Pos (14UL) |
| |
| #define | PORT0_PDISC_PDIS14_Msk (0x4000UL) |
| |
| #define | PORT0_PDISC_PDIS15_Pos (15UL) |
| |
| #define | PORT0_PDISC_PDIS15_Msk (0x8000UL) |
| |
| #define | PORT0_PPS_PPS0_Pos (0UL) |
| |
| #define | PORT0_PPS_PPS0_Msk (0x1UL) |
| |
| #define | PORT0_PPS_PPS1_Pos (1UL) |
| |
| #define | PORT0_PPS_PPS1_Msk (0x2UL) |
| |
| #define | PORT0_PPS_PPS2_Pos (2UL) |
| |
| #define | PORT0_PPS_PPS2_Msk (0x4UL) |
| |
| #define | PORT0_PPS_PPS3_Pos (3UL) |
| |
| #define | PORT0_PPS_PPS3_Msk (0x8UL) |
| |
| #define | PORT0_PPS_PPS4_Pos (4UL) |
| |
| #define | PORT0_PPS_PPS4_Msk (0x10UL) |
| |
| #define | PORT0_PPS_PPS5_Pos (5UL) |
| |
| #define | PORT0_PPS_PPS5_Msk (0x20UL) |
| |
| #define | PORT0_PPS_PPS6_Pos (6UL) |
| |
| #define | PORT0_PPS_PPS6_Msk (0x40UL) |
| |
| #define | PORT0_PPS_PPS7_Pos (7UL) |
| |
| #define | PORT0_PPS_PPS7_Msk (0x80UL) |
| |
| #define | PORT0_PPS_PPS8_Pos (8UL) |
| |
| #define | PORT0_PPS_PPS8_Msk (0x100UL) |
| |
| #define | PORT0_PPS_PPS9_Pos (9UL) |
| |
| #define | PORT0_PPS_PPS9_Msk (0x200UL) |
| |
| #define | PORT0_PPS_PPS10_Pos (10UL) |
| |
| #define | PORT0_PPS_PPS10_Msk (0x400UL) |
| |
| #define | PORT0_PPS_PPS11_Pos (11UL) |
| |
| #define | PORT0_PPS_PPS11_Msk (0x800UL) |
| |
| #define | PORT0_PPS_PPS12_Pos (12UL) |
| |
| #define | PORT0_PPS_PPS12_Msk (0x1000UL) |
| |
| #define | PORT0_PPS_PPS13_Pos (13UL) |
| |
| #define | PORT0_PPS_PPS13_Msk (0x2000UL) |
| |
| #define | PORT0_PPS_PPS14_Pos (14UL) |
| |
| #define | PORT0_PPS_PPS14_Msk (0x4000UL) |
| |
| #define | PORT0_PPS_PPS15_Pos (15UL) |
| |
| #define | PORT0_PPS_PPS15_Msk (0x8000UL) |
| |
| #define | PORT0_HWSEL_HW0_Pos (0UL) |
| |
| #define | PORT0_HWSEL_HW0_Msk (0x3UL) |
| |
| #define | PORT0_HWSEL_HW1_Pos (2UL) |
| |
| #define | PORT0_HWSEL_HW1_Msk (0xcUL) |
| |
| #define | PORT0_HWSEL_HW2_Pos (4UL) |
| |
| #define | PORT0_HWSEL_HW2_Msk (0x30UL) |
| |
| #define | PORT0_HWSEL_HW3_Pos (6UL) |
| |
| #define | PORT0_HWSEL_HW3_Msk (0xc0UL) |
| |
| #define | PORT0_HWSEL_HW4_Pos (8UL) |
| |
| #define | PORT0_HWSEL_HW4_Msk (0x300UL) |
| |
| #define | PORT0_HWSEL_HW5_Pos (10UL) |
| |
| #define | PORT0_HWSEL_HW5_Msk (0xc00UL) |
| |
| #define | PORT0_HWSEL_HW6_Pos (12UL) |
| |
| #define | PORT0_HWSEL_HW6_Msk (0x3000UL) |
| |
| #define | PORT0_HWSEL_HW7_Pos (14UL) |
| |
| #define | PORT0_HWSEL_HW7_Msk (0xc000UL) |
| |
| #define | PORT0_HWSEL_HW8_Pos (16UL) |
| |
| #define | PORT0_HWSEL_HW8_Msk (0x30000UL) |
| |
| #define | PORT0_HWSEL_HW9_Pos (18UL) |
| |
| #define | PORT0_HWSEL_HW9_Msk (0xc0000UL) |
| |
| #define | PORT0_HWSEL_HW10_Pos (20UL) |
| |
| #define | PORT0_HWSEL_HW10_Msk (0x300000UL) |
| |
| #define | PORT0_HWSEL_HW11_Pos (22UL) |
| |
| #define | PORT0_HWSEL_HW11_Msk (0xc00000UL) |
| |
| #define | PORT0_HWSEL_HW12_Pos (24UL) |
| |
| #define | PORT0_HWSEL_HW12_Msk (0x3000000UL) |
| |
| #define | PORT0_HWSEL_HW13_Pos (26UL) |
| |
| #define | PORT0_HWSEL_HW13_Msk (0xc000000UL) |
| |
| #define | PORT0_HWSEL_HW14_Pos (28UL) |
| |
| #define | PORT0_HWSEL_HW14_Msk (0x30000000UL) |
| |
| #define | PORT0_HWSEL_HW15_Pos (30UL) |
| |
| #define | PORT0_HWSEL_HW15_Msk (0xc0000000UL) |
| |
| #define | PORT1_OUT_P0_Pos (0UL) |
| |
| #define | PORT1_OUT_P0_Msk (0x1UL) |
| |
| #define | PORT1_OUT_P1_Pos (1UL) |
| |
| #define | PORT1_OUT_P1_Msk (0x2UL) |
| |
| #define | PORT1_OUT_P2_Pos (2UL) |
| |
| #define | PORT1_OUT_P2_Msk (0x4UL) |
| |
| #define | PORT1_OUT_P3_Pos (3UL) |
| |
| #define | PORT1_OUT_P3_Msk (0x8UL) |
| |
| #define | PORT1_OUT_P4_Pos (4UL) |
| |
| #define | PORT1_OUT_P4_Msk (0x10UL) |
| |
| #define | PORT1_OUT_P5_Pos (5UL) |
| |
| #define | PORT1_OUT_P5_Msk (0x20UL) |
| |
| #define | PORT1_OUT_P6_Pos (6UL) |
| |
| #define | PORT1_OUT_P6_Msk (0x40UL) |
| |
| #define | PORT1_OUT_P7_Pos (7UL) |
| |
| #define | PORT1_OUT_P7_Msk (0x80UL) |
| |
| #define | PORT1_OUT_P8_Pos (8UL) |
| |
| #define | PORT1_OUT_P8_Msk (0x100UL) |
| |
| #define | PORT1_OUT_P9_Pos (9UL) |
| |
| #define | PORT1_OUT_P9_Msk (0x200UL) |
| |
| #define | PORT1_OUT_P10_Pos (10UL) |
| |
| #define | PORT1_OUT_P10_Msk (0x400UL) |
| |
| #define | PORT1_OUT_P11_Pos (11UL) |
| |
| #define | PORT1_OUT_P11_Msk (0x800UL) |
| |
| #define | PORT1_OUT_P12_Pos (12UL) |
| |
| #define | PORT1_OUT_P12_Msk (0x1000UL) |
| |
| #define | PORT1_OUT_P13_Pos (13UL) |
| |
| #define | PORT1_OUT_P13_Msk (0x2000UL) |
| |
| #define | PORT1_OUT_P14_Pos (14UL) |
| |
| #define | PORT1_OUT_P14_Msk (0x4000UL) |
| |
| #define | PORT1_OUT_P15_Pos (15UL) |
| |
| #define | PORT1_OUT_P15_Msk (0x8000UL) |
| |
| #define | PORT1_OMR_PS0_Pos (0UL) |
| |
| #define | PORT1_OMR_PS0_Msk (0x1UL) |
| |
| #define | PORT1_OMR_PS1_Pos (1UL) |
| |
| #define | PORT1_OMR_PS1_Msk (0x2UL) |
| |
| #define | PORT1_OMR_PS2_Pos (2UL) |
| |
| #define | PORT1_OMR_PS2_Msk (0x4UL) |
| |
| #define | PORT1_OMR_PS3_Pos (3UL) |
| |
| #define | PORT1_OMR_PS3_Msk (0x8UL) |
| |
| #define | PORT1_OMR_PS4_Pos (4UL) |
| |
| #define | PORT1_OMR_PS4_Msk (0x10UL) |
| |
| #define | PORT1_OMR_PS5_Pos (5UL) |
| |
| #define | PORT1_OMR_PS5_Msk (0x20UL) |
| |
| #define | PORT1_OMR_PS6_Pos (6UL) |
| |
| #define | PORT1_OMR_PS6_Msk (0x40UL) |
| |
| #define | PORT1_OMR_PS7_Pos (7UL) |
| |
| #define | PORT1_OMR_PS7_Msk (0x80UL) |
| |
| #define | PORT1_OMR_PS8_Pos (8UL) |
| |
| #define | PORT1_OMR_PS8_Msk (0x100UL) |
| |
| #define | PORT1_OMR_PS9_Pos (9UL) |
| |
| #define | PORT1_OMR_PS9_Msk (0x200UL) |
| |
| #define | PORT1_OMR_PS10_Pos (10UL) |
| |
| #define | PORT1_OMR_PS10_Msk (0x400UL) |
| |
| #define | PORT1_OMR_PS11_Pos (11UL) |
| |
| #define | PORT1_OMR_PS11_Msk (0x800UL) |
| |
| #define | PORT1_OMR_PS12_Pos (12UL) |
| |
| #define | PORT1_OMR_PS12_Msk (0x1000UL) |
| |
| #define | PORT1_OMR_PS13_Pos (13UL) |
| |
| #define | PORT1_OMR_PS13_Msk (0x2000UL) |
| |
| #define | PORT1_OMR_PS14_Pos (14UL) |
| |
| #define | PORT1_OMR_PS14_Msk (0x4000UL) |
| |
| #define | PORT1_OMR_PS15_Pos (15UL) |
| |
| #define | PORT1_OMR_PS15_Msk (0x8000UL) |
| |
| #define | PORT1_OMR_PR0_Pos (16UL) |
| |
| #define | PORT1_OMR_PR0_Msk (0x10000UL) |
| |
| #define | PORT1_OMR_PR1_Pos (17UL) |
| |
| #define | PORT1_OMR_PR1_Msk (0x20000UL) |
| |
| #define | PORT1_OMR_PR2_Pos (18UL) |
| |
| #define | PORT1_OMR_PR2_Msk (0x40000UL) |
| |
| #define | PORT1_OMR_PR3_Pos (19UL) |
| |
| #define | PORT1_OMR_PR3_Msk (0x80000UL) |
| |
| #define | PORT1_OMR_PR4_Pos (20UL) |
| |
| #define | PORT1_OMR_PR4_Msk (0x100000UL) |
| |
| #define | PORT1_OMR_PR5_Pos (21UL) |
| |
| #define | PORT1_OMR_PR5_Msk (0x200000UL) |
| |
| #define | PORT1_OMR_PR6_Pos (22UL) |
| |
| #define | PORT1_OMR_PR6_Msk (0x400000UL) |
| |
| #define | PORT1_OMR_PR7_Pos (23UL) |
| |
| #define | PORT1_OMR_PR7_Msk (0x800000UL) |
| |
| #define | PORT1_OMR_PR8_Pos (24UL) |
| |
| #define | PORT1_OMR_PR8_Msk (0x1000000UL) |
| |
| #define | PORT1_OMR_PR9_Pos (25UL) |
| |
| #define | PORT1_OMR_PR9_Msk (0x2000000UL) |
| |
| #define | PORT1_OMR_PR10_Pos (26UL) |
| |
| #define | PORT1_OMR_PR10_Msk (0x4000000UL) |
| |
| #define | PORT1_OMR_PR11_Pos (27UL) |
| |
| #define | PORT1_OMR_PR11_Msk (0x8000000UL) |
| |
| #define | PORT1_OMR_PR12_Pos (28UL) |
| |
| #define | PORT1_OMR_PR12_Msk (0x10000000UL) |
| |
| #define | PORT1_OMR_PR13_Pos (29UL) |
| |
| #define | PORT1_OMR_PR13_Msk (0x20000000UL) |
| |
| #define | PORT1_OMR_PR14_Pos (30UL) |
| |
| #define | PORT1_OMR_PR14_Msk (0x40000000UL) |
| |
| #define | PORT1_OMR_PR15_Pos (31UL) |
| |
| #define | PORT1_OMR_PR15_Msk (0x80000000UL) |
| |
| #define | PORT1_IOCR0_PC0_Pos (3UL) |
| |
| #define | PORT1_IOCR0_PC0_Msk (0xf8UL) |
| |
| #define | PORT1_IOCR0_PC1_Pos (11UL) |
| |
| #define | PORT1_IOCR0_PC1_Msk (0xf800UL) |
| |
| #define | PORT1_IOCR0_PC2_Pos (19UL) |
| |
| #define | PORT1_IOCR0_PC2_Msk (0xf80000UL) |
| |
| #define | PORT1_IOCR0_PC3_Pos (27UL) |
| |
| #define | PORT1_IOCR0_PC3_Msk (0xf8000000UL) |
| |
| #define | PORT1_IOCR4_PC4_Pos (3UL) |
| |
| #define | PORT1_IOCR4_PC4_Msk (0xf8UL) |
| |
| #define | PORT1_IOCR4_PC5_Pos (11UL) |
| |
| #define | PORT1_IOCR4_PC5_Msk (0xf800UL) |
| |
| #define | PORT1_IOCR4_PC6_Pos (19UL) |
| |
| #define | PORT1_IOCR4_PC6_Msk (0xf80000UL) |
| |
| #define | PORT1_IOCR4_PC7_Pos (27UL) |
| |
| #define | PORT1_IOCR4_PC7_Msk (0xf8000000UL) |
| |
| #define | PORT1_IOCR8_PC8_Pos (3UL) |
| |
| #define | PORT1_IOCR8_PC8_Msk (0xf8UL) |
| |
| #define | PORT1_IOCR8_PC9_Pos (11UL) |
| |
| #define | PORT1_IOCR8_PC9_Msk (0xf800UL) |
| |
| #define | PORT1_IOCR8_PC10_Pos (19UL) |
| |
| #define | PORT1_IOCR8_PC10_Msk (0xf80000UL) |
| |
| #define | PORT1_IOCR8_PC11_Pos (27UL) |
| |
| #define | PORT1_IOCR8_PC11_Msk (0xf8000000UL) |
| |
| #define | PORT1_IOCR12_PC12_Pos (3UL) |
| |
| #define | PORT1_IOCR12_PC12_Msk (0xf8UL) |
| |
| #define | PORT1_IOCR12_PC13_Pos (11UL) |
| |
| #define | PORT1_IOCR12_PC13_Msk (0xf800UL) |
| |
| #define | PORT1_IOCR12_PC14_Pos (19UL) |
| |
| #define | PORT1_IOCR12_PC14_Msk (0xf80000UL) |
| |
| #define | PORT1_IOCR12_PC15_Pos (27UL) |
| |
| #define | PORT1_IOCR12_PC15_Msk (0xf8000000UL) |
| |
| #define | PORT1_IN_P0_Pos (0UL) |
| |
| #define | PORT1_IN_P0_Msk (0x1UL) |
| |
| #define | PORT1_IN_P1_Pos (1UL) |
| |
| #define | PORT1_IN_P1_Msk (0x2UL) |
| |
| #define | PORT1_IN_P2_Pos (2UL) |
| |
| #define | PORT1_IN_P2_Msk (0x4UL) |
| |
| #define | PORT1_IN_P3_Pos (3UL) |
| |
| #define | PORT1_IN_P3_Msk (0x8UL) |
| |
| #define | PORT1_IN_P4_Pos (4UL) |
| |
| #define | PORT1_IN_P4_Msk (0x10UL) |
| |
| #define | PORT1_IN_P5_Pos (5UL) |
| |
| #define | PORT1_IN_P5_Msk (0x20UL) |
| |
| #define | PORT1_IN_P6_Pos (6UL) |
| |
| #define | PORT1_IN_P6_Msk (0x40UL) |
| |
| #define | PORT1_IN_P7_Pos (7UL) |
| |
| #define | PORT1_IN_P7_Msk (0x80UL) |
| |
| #define | PORT1_IN_P8_Pos (8UL) |
| |
| #define | PORT1_IN_P8_Msk (0x100UL) |
| |
| #define | PORT1_IN_P9_Pos (9UL) |
| |
| #define | PORT1_IN_P9_Msk (0x200UL) |
| |
| #define | PORT1_IN_P10_Pos (10UL) |
| |
| #define | PORT1_IN_P10_Msk (0x400UL) |
| |
| #define | PORT1_IN_P11_Pos (11UL) |
| |
| #define | PORT1_IN_P11_Msk (0x800UL) |
| |
| #define | PORT1_IN_P12_Pos (12UL) |
| |
| #define | PORT1_IN_P12_Msk (0x1000UL) |
| |
| #define | PORT1_IN_P13_Pos (13UL) |
| |
| #define | PORT1_IN_P13_Msk (0x2000UL) |
| |
| #define | PORT1_IN_P14_Pos (14UL) |
| |
| #define | PORT1_IN_P14_Msk (0x4000UL) |
| |
| #define | PORT1_IN_P15_Pos (15UL) |
| |
| #define | PORT1_IN_P15_Msk (0x8000UL) |
| |
| #define | PORT1_PDR0_PD0_Pos (0UL) |
| |
| #define | PORT1_PDR0_PD0_Msk (0x7UL) |
| |
| #define | PORT1_PDR0_PD1_Pos (4UL) |
| |
| #define | PORT1_PDR0_PD1_Msk (0x70UL) |
| |
| #define | PORT1_PDR0_PD2_Pos (8UL) |
| |
| #define | PORT1_PDR0_PD2_Msk (0x700UL) |
| |
| #define | PORT1_PDR0_PD3_Pos (12UL) |
| |
| #define | PORT1_PDR0_PD3_Msk (0x7000UL) |
| |
| #define | PORT1_PDR0_PD4_Pos (16UL) |
| |
| #define | PORT1_PDR0_PD4_Msk (0x70000UL) |
| |
| #define | PORT1_PDR0_PD5_Pos (20UL) |
| |
| #define | PORT1_PDR0_PD5_Msk (0x700000UL) |
| |
| #define | PORT1_PDR0_PD6_Pos (24UL) |
| |
| #define | PORT1_PDR0_PD6_Msk (0x7000000UL) |
| |
| #define | PORT1_PDR0_PD7_Pos (28UL) |
| |
| #define | PORT1_PDR0_PD7_Msk (0x70000000UL) |
| |
| #define | PORT1_PDR1_PD8_Pos (0UL) |
| |
| #define | PORT1_PDR1_PD8_Msk (0x7UL) |
| |
| #define | PORT1_PDR1_PD9_Pos (4UL) |
| |
| #define | PORT1_PDR1_PD9_Msk (0x70UL) |
| |
| #define | PORT1_PDR1_PD10_Pos (8UL) |
| |
| #define | PORT1_PDR1_PD10_Msk (0x700UL) |
| |
| #define | PORT1_PDR1_PD11_Pos (12UL) |
| |
| #define | PORT1_PDR1_PD11_Msk (0x7000UL) |
| |
| #define | PORT1_PDR1_PD12_Pos (16UL) |
| |
| #define | PORT1_PDR1_PD12_Msk (0x70000UL) |
| |
| #define | PORT1_PDR1_PD13_Pos (20UL) |
| |
| #define | PORT1_PDR1_PD13_Msk (0x700000UL) |
| |
| #define | PORT1_PDR1_PD14_Pos (24UL) |
| |
| #define | PORT1_PDR1_PD14_Msk (0x7000000UL) |
| |
| #define | PORT1_PDR1_PD15_Pos (28UL) |
| |
| #define | PORT1_PDR1_PD15_Msk (0x70000000UL) |
| |
| #define | PORT1_PDISC_PDIS0_Pos (0UL) |
| |
| #define | PORT1_PDISC_PDIS0_Msk (0x1UL) |
| |
| #define | PORT1_PDISC_PDIS1_Pos (1UL) |
| |
| #define | PORT1_PDISC_PDIS1_Msk (0x2UL) |
| |
| #define | PORT1_PDISC_PDIS2_Pos (2UL) |
| |
| #define | PORT1_PDISC_PDIS2_Msk (0x4UL) |
| |
| #define | PORT1_PDISC_PDIS3_Pos (3UL) |
| |
| #define | PORT1_PDISC_PDIS3_Msk (0x8UL) |
| |
| #define | PORT1_PDISC_PDIS4_Pos (4UL) |
| |
| #define | PORT1_PDISC_PDIS4_Msk (0x10UL) |
| |
| #define | PORT1_PDISC_PDIS5_Pos (5UL) |
| |
| #define | PORT1_PDISC_PDIS5_Msk (0x20UL) |
| |
| #define | PORT1_PDISC_PDIS6_Pos (6UL) |
| |
| #define | PORT1_PDISC_PDIS6_Msk (0x40UL) |
| |
| #define | PORT1_PDISC_PDIS7_Pos (7UL) |
| |
| #define | PORT1_PDISC_PDIS7_Msk (0x80UL) |
| |
| #define | PORT1_PDISC_PDIS8_Pos (8UL) |
| |
| #define | PORT1_PDISC_PDIS8_Msk (0x100UL) |
| |
| #define | PORT1_PDISC_PDIS9_Pos (9UL) |
| |
| #define | PORT1_PDISC_PDIS9_Msk (0x200UL) |
| |
| #define | PORT1_PDISC_PDIS10_Pos (10UL) |
| |
| #define | PORT1_PDISC_PDIS10_Msk (0x400UL) |
| |
| #define | PORT1_PDISC_PDIS11_Pos (11UL) |
| |
| #define | PORT1_PDISC_PDIS11_Msk (0x800UL) |
| |
| #define | PORT1_PDISC_PDIS12_Pos (12UL) |
| |
| #define | PORT1_PDISC_PDIS12_Msk (0x1000UL) |
| |
| #define | PORT1_PDISC_PDIS13_Pos (13UL) |
| |
| #define | PORT1_PDISC_PDIS13_Msk (0x2000UL) |
| |
| #define | PORT1_PDISC_PDIS14_Pos (14UL) |
| |
| #define | PORT1_PDISC_PDIS14_Msk (0x4000UL) |
| |
| #define | PORT1_PDISC_PDIS15_Pos (15UL) |
| |
| #define | PORT1_PDISC_PDIS15_Msk (0x8000UL) |
| |
| #define | PORT1_PPS_PPS0_Pos (0UL) |
| |
| #define | PORT1_PPS_PPS0_Msk (0x1UL) |
| |
| #define | PORT1_PPS_PPS1_Pos (1UL) |
| |
| #define | PORT1_PPS_PPS1_Msk (0x2UL) |
| |
| #define | PORT1_PPS_PPS2_Pos (2UL) |
| |
| #define | PORT1_PPS_PPS2_Msk (0x4UL) |
| |
| #define | PORT1_PPS_PPS3_Pos (3UL) |
| |
| #define | PORT1_PPS_PPS3_Msk (0x8UL) |
| |
| #define | PORT1_PPS_PPS4_Pos (4UL) |
| |
| #define | PORT1_PPS_PPS4_Msk (0x10UL) |
| |
| #define | PORT1_PPS_PPS5_Pos (5UL) |
| |
| #define | PORT1_PPS_PPS5_Msk (0x20UL) |
| |
| #define | PORT1_PPS_PPS6_Pos (6UL) |
| |
| #define | PORT1_PPS_PPS6_Msk (0x40UL) |
| |
| #define | PORT1_PPS_PPS7_Pos (7UL) |
| |
| #define | PORT1_PPS_PPS7_Msk (0x80UL) |
| |
| #define | PORT1_PPS_PPS8_Pos (8UL) |
| |
| #define | PORT1_PPS_PPS8_Msk (0x100UL) |
| |
| #define | PORT1_PPS_PPS9_Pos (9UL) |
| |
| #define | PORT1_PPS_PPS9_Msk (0x200UL) |
| |
| #define | PORT1_PPS_PPS10_Pos (10UL) |
| |
| #define | PORT1_PPS_PPS10_Msk (0x400UL) |
| |
| #define | PORT1_PPS_PPS11_Pos (11UL) |
| |
| #define | PORT1_PPS_PPS11_Msk (0x800UL) |
| |
| #define | PORT1_PPS_PPS12_Pos (12UL) |
| |
| #define | PORT1_PPS_PPS12_Msk (0x1000UL) |
| |
| #define | PORT1_PPS_PPS13_Pos (13UL) |
| |
| #define | PORT1_PPS_PPS13_Msk (0x2000UL) |
| |
| #define | PORT1_PPS_PPS14_Pos (14UL) |
| |
| #define | PORT1_PPS_PPS14_Msk (0x4000UL) |
| |
| #define | PORT1_PPS_PPS15_Pos (15UL) |
| |
| #define | PORT1_PPS_PPS15_Msk (0x8000UL) |
| |
| #define | PORT1_HWSEL_HW0_Pos (0UL) |
| |
| #define | PORT1_HWSEL_HW0_Msk (0x3UL) |
| |
| #define | PORT1_HWSEL_HW1_Pos (2UL) |
| |
| #define | PORT1_HWSEL_HW1_Msk (0xcUL) |
| |
| #define | PORT1_HWSEL_HW2_Pos (4UL) |
| |
| #define | PORT1_HWSEL_HW2_Msk (0x30UL) |
| |
| #define | PORT1_HWSEL_HW3_Pos (6UL) |
| |
| #define | PORT1_HWSEL_HW3_Msk (0xc0UL) |
| |
| #define | PORT1_HWSEL_HW4_Pos (8UL) |
| |
| #define | PORT1_HWSEL_HW4_Msk (0x300UL) |
| |
| #define | PORT1_HWSEL_HW5_Pos (10UL) |
| |
| #define | PORT1_HWSEL_HW5_Msk (0xc00UL) |
| |
| #define | PORT1_HWSEL_HW6_Pos (12UL) |
| |
| #define | PORT1_HWSEL_HW6_Msk (0x3000UL) |
| |
| #define | PORT1_HWSEL_HW7_Pos (14UL) |
| |
| #define | PORT1_HWSEL_HW7_Msk (0xc000UL) |
| |
| #define | PORT1_HWSEL_HW8_Pos (16UL) |
| |
| #define | PORT1_HWSEL_HW8_Msk (0x30000UL) |
| |
| #define | PORT1_HWSEL_HW9_Pos (18UL) |
| |
| #define | PORT1_HWSEL_HW9_Msk (0xc0000UL) |
| |
| #define | PORT1_HWSEL_HW10_Pos (20UL) |
| |
| #define | PORT1_HWSEL_HW10_Msk (0x300000UL) |
| |
| #define | PORT1_HWSEL_HW11_Pos (22UL) |
| |
| #define | PORT1_HWSEL_HW11_Msk (0xc00000UL) |
| |
| #define | PORT1_HWSEL_HW12_Pos (24UL) |
| |
| #define | PORT1_HWSEL_HW12_Msk (0x3000000UL) |
| |
| #define | PORT1_HWSEL_HW13_Pos (26UL) |
| |
| #define | PORT1_HWSEL_HW13_Msk (0xc000000UL) |
| |
| #define | PORT1_HWSEL_HW14_Pos (28UL) |
| |
| #define | PORT1_HWSEL_HW14_Msk (0x30000000UL) |
| |
| #define | PORT1_HWSEL_HW15_Pos (30UL) |
| |
| #define | PORT1_HWSEL_HW15_Msk (0xc0000000UL) |
| |
| #define | PORT2_OUT_P0_Pos (0UL) |
| |
| #define | PORT2_OUT_P0_Msk (0x1UL) |
| |
| #define | PORT2_OUT_P1_Pos (1UL) |
| |
| #define | PORT2_OUT_P1_Msk (0x2UL) |
| |
| #define | PORT2_OUT_P2_Pos (2UL) |
| |
| #define | PORT2_OUT_P2_Msk (0x4UL) |
| |
| #define | PORT2_OUT_P3_Pos (3UL) |
| |
| #define | PORT2_OUT_P3_Msk (0x8UL) |
| |
| #define | PORT2_OUT_P4_Pos (4UL) |
| |
| #define | PORT2_OUT_P4_Msk (0x10UL) |
| |
| #define | PORT2_OUT_P5_Pos (5UL) |
| |
| #define | PORT2_OUT_P5_Msk (0x20UL) |
| |
| #define | PORT2_OUT_P6_Pos (6UL) |
| |
| #define | PORT2_OUT_P6_Msk (0x40UL) |
| |
| #define | PORT2_OUT_P7_Pos (7UL) |
| |
| #define | PORT2_OUT_P7_Msk (0x80UL) |
| |
| #define | PORT2_OUT_P8_Pos (8UL) |
| |
| #define | PORT2_OUT_P8_Msk (0x100UL) |
| |
| #define | PORT2_OUT_P9_Pos (9UL) |
| |
| #define | PORT2_OUT_P9_Msk (0x200UL) |
| |
| #define | PORT2_OUT_P10_Pos (10UL) |
| |
| #define | PORT2_OUT_P10_Msk (0x400UL) |
| |
| #define | PORT2_OUT_P11_Pos (11UL) |
| |
| #define | PORT2_OUT_P11_Msk (0x800UL) |
| |
| #define | PORT2_OUT_P12_Pos (12UL) |
| |
| #define | PORT2_OUT_P12_Msk (0x1000UL) |
| |
| #define | PORT2_OUT_P13_Pos (13UL) |
| |
| #define | PORT2_OUT_P13_Msk (0x2000UL) |
| |
| #define | PORT2_OUT_P14_Pos (14UL) |
| |
| #define | PORT2_OUT_P14_Msk (0x4000UL) |
| |
| #define | PORT2_OUT_P15_Pos (15UL) |
| |
| #define | PORT2_OUT_P15_Msk (0x8000UL) |
| |
| #define | PORT2_OMR_PS0_Pos (0UL) |
| |
| #define | PORT2_OMR_PS0_Msk (0x1UL) |
| |
| #define | PORT2_OMR_PS1_Pos (1UL) |
| |
| #define | PORT2_OMR_PS1_Msk (0x2UL) |
| |
| #define | PORT2_OMR_PS2_Pos (2UL) |
| |
| #define | PORT2_OMR_PS2_Msk (0x4UL) |
| |
| #define | PORT2_OMR_PS3_Pos (3UL) |
| |
| #define | PORT2_OMR_PS3_Msk (0x8UL) |
| |
| #define | PORT2_OMR_PS4_Pos (4UL) |
| |
| #define | PORT2_OMR_PS4_Msk (0x10UL) |
| |
| #define | PORT2_OMR_PS5_Pos (5UL) |
| |
| #define | PORT2_OMR_PS5_Msk (0x20UL) |
| |
| #define | PORT2_OMR_PS6_Pos (6UL) |
| |
| #define | PORT2_OMR_PS6_Msk (0x40UL) |
| |
| #define | PORT2_OMR_PS7_Pos (7UL) |
| |
| #define | PORT2_OMR_PS7_Msk (0x80UL) |
| |
| #define | PORT2_OMR_PS8_Pos (8UL) |
| |
| #define | PORT2_OMR_PS8_Msk (0x100UL) |
| |
| #define | PORT2_OMR_PS9_Pos (9UL) |
| |
| #define | PORT2_OMR_PS9_Msk (0x200UL) |
| |
| #define | PORT2_OMR_PS10_Pos (10UL) |
| |
| #define | PORT2_OMR_PS10_Msk (0x400UL) |
| |
| #define | PORT2_OMR_PS11_Pos (11UL) |
| |
| #define | PORT2_OMR_PS11_Msk (0x800UL) |
| |
| #define | PORT2_OMR_PS12_Pos (12UL) |
| |
| #define | PORT2_OMR_PS12_Msk (0x1000UL) |
| |
| #define | PORT2_OMR_PS13_Pos (13UL) |
| |
| #define | PORT2_OMR_PS13_Msk (0x2000UL) |
| |
| #define | PORT2_OMR_PS14_Pos (14UL) |
| |
| #define | PORT2_OMR_PS14_Msk (0x4000UL) |
| |
| #define | PORT2_OMR_PS15_Pos (15UL) |
| |
| #define | PORT2_OMR_PS15_Msk (0x8000UL) |
| |
| #define | PORT2_OMR_PR0_Pos (16UL) |
| |
| #define | PORT2_OMR_PR0_Msk (0x10000UL) |
| |
| #define | PORT2_OMR_PR1_Pos (17UL) |
| |
| #define | PORT2_OMR_PR1_Msk (0x20000UL) |
| |
| #define | PORT2_OMR_PR2_Pos (18UL) |
| |
| #define | PORT2_OMR_PR2_Msk (0x40000UL) |
| |
| #define | PORT2_OMR_PR3_Pos (19UL) |
| |
| #define | PORT2_OMR_PR3_Msk (0x80000UL) |
| |
| #define | PORT2_OMR_PR4_Pos (20UL) |
| |
| #define | PORT2_OMR_PR4_Msk (0x100000UL) |
| |
| #define | PORT2_OMR_PR5_Pos (21UL) |
| |
| #define | PORT2_OMR_PR5_Msk (0x200000UL) |
| |
| #define | PORT2_OMR_PR6_Pos (22UL) |
| |
| #define | PORT2_OMR_PR6_Msk (0x400000UL) |
| |
| #define | PORT2_OMR_PR7_Pos (23UL) |
| |
| #define | PORT2_OMR_PR7_Msk (0x800000UL) |
| |
| #define | PORT2_OMR_PR8_Pos (24UL) |
| |
| #define | PORT2_OMR_PR8_Msk (0x1000000UL) |
| |
| #define | PORT2_OMR_PR9_Pos (25UL) |
| |
| #define | PORT2_OMR_PR9_Msk (0x2000000UL) |
| |
| #define | PORT2_OMR_PR10_Pos (26UL) |
| |
| #define | PORT2_OMR_PR10_Msk (0x4000000UL) |
| |
| #define | PORT2_OMR_PR11_Pos (27UL) |
| |
| #define | PORT2_OMR_PR11_Msk (0x8000000UL) |
| |
| #define | PORT2_OMR_PR12_Pos (28UL) |
| |
| #define | PORT2_OMR_PR12_Msk (0x10000000UL) |
| |
| #define | PORT2_OMR_PR13_Pos (29UL) |
| |
| #define | PORT2_OMR_PR13_Msk (0x20000000UL) |
| |
| #define | PORT2_OMR_PR14_Pos (30UL) |
| |
| #define | PORT2_OMR_PR14_Msk (0x40000000UL) |
| |
| #define | PORT2_OMR_PR15_Pos (31UL) |
| |
| #define | PORT2_OMR_PR15_Msk (0x80000000UL) |
| |
| #define | PORT2_IOCR0_PC0_Pos (3UL) |
| |
| #define | PORT2_IOCR0_PC0_Msk (0xf8UL) |
| |
| #define | PORT2_IOCR0_PC1_Pos (11UL) |
| |
| #define | PORT2_IOCR0_PC1_Msk (0xf800UL) |
| |
| #define | PORT2_IOCR0_PC2_Pos (19UL) |
| |
| #define | PORT2_IOCR0_PC2_Msk (0xf80000UL) |
| |
| #define | PORT2_IOCR0_PC3_Pos (27UL) |
| |
| #define | PORT2_IOCR0_PC3_Msk (0xf8000000UL) |
| |
| #define | PORT2_IOCR4_PC4_Pos (3UL) |
| |
| #define | PORT2_IOCR4_PC4_Msk (0xf8UL) |
| |
| #define | PORT2_IOCR4_PC5_Pos (11UL) |
| |
| #define | PORT2_IOCR4_PC5_Msk (0xf800UL) |
| |
| #define | PORT2_IOCR4_PC6_Pos (19UL) |
| |
| #define | PORT2_IOCR4_PC6_Msk (0xf80000UL) |
| |
| #define | PORT2_IOCR4_PC7_Pos (27UL) |
| |
| #define | PORT2_IOCR4_PC7_Msk (0xf8000000UL) |
| |
| #define | PORT2_IOCR8_PC8_Pos (3UL) |
| |
| #define | PORT2_IOCR8_PC8_Msk (0xf8UL) |
| |
| #define | PORT2_IOCR8_PC9_Pos (11UL) |
| |
| #define | PORT2_IOCR8_PC9_Msk (0xf800UL) |
| |
| #define | PORT2_IOCR8_PC10_Pos (19UL) |
| |
| #define | PORT2_IOCR8_PC10_Msk (0xf80000UL) |
| |
| #define | PORT2_IOCR8_PC11_Pos (27UL) |
| |
| #define | PORT2_IOCR8_PC11_Msk (0xf8000000UL) |
| |
| #define | PORT2_IOCR12_PC12_Pos (3UL) |
| |
| #define | PORT2_IOCR12_PC12_Msk (0xf8UL) |
| |
| #define | PORT2_IOCR12_PC13_Pos (11UL) |
| |
| #define | PORT2_IOCR12_PC13_Msk (0xf800UL) |
| |
| #define | PORT2_IOCR12_PC14_Pos (19UL) |
| |
| #define | PORT2_IOCR12_PC14_Msk (0xf80000UL) |
| |
| #define | PORT2_IOCR12_PC15_Pos (27UL) |
| |
| #define | PORT2_IOCR12_PC15_Msk (0xf8000000UL) |
| |
| #define | PORT2_IN_P0_Pos (0UL) |
| |
| #define | PORT2_IN_P0_Msk (0x1UL) |
| |
| #define | PORT2_IN_P1_Pos (1UL) |
| |
| #define | PORT2_IN_P1_Msk (0x2UL) |
| |
| #define | PORT2_IN_P2_Pos (2UL) |
| |
| #define | PORT2_IN_P2_Msk (0x4UL) |
| |
| #define | PORT2_IN_P3_Pos (3UL) |
| |
| #define | PORT2_IN_P3_Msk (0x8UL) |
| |
| #define | PORT2_IN_P4_Pos (4UL) |
| |
| #define | PORT2_IN_P4_Msk (0x10UL) |
| |
| #define | PORT2_IN_P5_Pos (5UL) |
| |
| #define | PORT2_IN_P5_Msk (0x20UL) |
| |
| #define | PORT2_IN_P6_Pos (6UL) |
| |
| #define | PORT2_IN_P6_Msk (0x40UL) |
| |
| #define | PORT2_IN_P7_Pos (7UL) |
| |
| #define | PORT2_IN_P7_Msk (0x80UL) |
| |
| #define | PORT2_IN_P8_Pos (8UL) |
| |
| #define | PORT2_IN_P8_Msk (0x100UL) |
| |
| #define | PORT2_IN_P9_Pos (9UL) |
| |
| #define | PORT2_IN_P9_Msk (0x200UL) |
| |
| #define | PORT2_IN_P10_Pos (10UL) |
| |
| #define | PORT2_IN_P10_Msk (0x400UL) |
| |
| #define | PORT2_IN_P11_Pos (11UL) |
| |
| #define | PORT2_IN_P11_Msk (0x800UL) |
| |
| #define | PORT2_IN_P12_Pos (12UL) |
| |
| #define | PORT2_IN_P12_Msk (0x1000UL) |
| |
| #define | PORT2_IN_P13_Pos (13UL) |
| |
| #define | PORT2_IN_P13_Msk (0x2000UL) |
| |
| #define | PORT2_IN_P14_Pos (14UL) |
| |
| #define | PORT2_IN_P14_Msk (0x4000UL) |
| |
| #define | PORT2_IN_P15_Pos (15UL) |
| |
| #define | PORT2_IN_P15_Msk (0x8000UL) |
| |
| #define | PORT2_PDR0_PD0_Pos (0UL) |
| |
| #define | PORT2_PDR0_PD0_Msk (0x7UL) |
| |
| #define | PORT2_PDR0_PD1_Pos (4UL) |
| |
| #define | PORT2_PDR0_PD1_Msk (0x70UL) |
| |
| #define | PORT2_PDR0_PD2_Pos (8UL) |
| |
| #define | PORT2_PDR0_PD2_Msk (0x700UL) |
| |
| #define | PORT2_PDR0_PD3_Pos (12UL) |
| |
| #define | PORT2_PDR0_PD3_Msk (0x7000UL) |
| |
| #define | PORT2_PDR0_PD4_Pos (16UL) |
| |
| #define | PORT2_PDR0_PD4_Msk (0x70000UL) |
| |
| #define | PORT2_PDR0_PD5_Pos (20UL) |
| |
| #define | PORT2_PDR0_PD5_Msk (0x700000UL) |
| |
| #define | PORT2_PDR0_PD6_Pos (24UL) |
| |
| #define | PORT2_PDR0_PD6_Msk (0x7000000UL) |
| |
| #define | PORT2_PDR0_PD7_Pos (28UL) |
| |
| #define | PORT2_PDR0_PD7_Msk (0x70000000UL) |
| |
| #define | PORT2_PDR1_PD8_Pos (0UL) |
| |
| #define | PORT2_PDR1_PD8_Msk (0x7UL) |
| |
| #define | PORT2_PDR1_PD9_Pos (4UL) |
| |
| #define | PORT2_PDR1_PD9_Msk (0x70UL) |
| |
| #define | PORT2_PDR1_PD10_Pos (8UL) |
| |
| #define | PORT2_PDR1_PD10_Msk (0x700UL) |
| |
| #define | PORT2_PDR1_PD11_Pos (12UL) |
| |
| #define | PORT2_PDR1_PD11_Msk (0x7000UL) |
| |
| #define | PORT2_PDR1_PD12_Pos (16UL) |
| |
| #define | PORT2_PDR1_PD12_Msk (0x70000UL) |
| |
| #define | PORT2_PDR1_PD13_Pos (20UL) |
| |
| #define | PORT2_PDR1_PD13_Msk (0x700000UL) |
| |
| #define | PORT2_PDR1_PD14_Pos (24UL) |
| |
| #define | PORT2_PDR1_PD14_Msk (0x7000000UL) |
| |
| #define | PORT2_PDR1_PD15_Pos (28UL) |
| |
| #define | PORT2_PDR1_PD15_Msk (0x70000000UL) |
| |
| #define | PORT2_PDISC_PDIS0_Pos (0UL) |
| |
| #define | PORT2_PDISC_PDIS0_Msk (0x1UL) |
| |
| #define | PORT2_PDISC_PDIS1_Pos (1UL) |
| |
| #define | PORT2_PDISC_PDIS1_Msk (0x2UL) |
| |
| #define | PORT2_PDISC_PDIS2_Pos (2UL) |
| |
| #define | PORT2_PDISC_PDIS2_Msk (0x4UL) |
| |
| #define | PORT2_PDISC_PDIS3_Pos (3UL) |
| |
| #define | PORT2_PDISC_PDIS3_Msk (0x8UL) |
| |
| #define | PORT2_PDISC_PDIS4_Pos (4UL) |
| |
| #define | PORT2_PDISC_PDIS4_Msk (0x10UL) |
| |
| #define | PORT2_PDISC_PDIS5_Pos (5UL) |
| |
| #define | PORT2_PDISC_PDIS5_Msk (0x20UL) |
| |
| #define | PORT2_PDISC_PDIS6_Pos (6UL) |
| |
| #define | PORT2_PDISC_PDIS6_Msk (0x40UL) |
| |
| #define | PORT2_PDISC_PDIS7_Pos (7UL) |
| |
| #define | PORT2_PDISC_PDIS7_Msk (0x80UL) |
| |
| #define | PORT2_PDISC_PDIS8_Pos (8UL) |
| |
| #define | PORT2_PDISC_PDIS8_Msk (0x100UL) |
| |
| #define | PORT2_PDISC_PDIS9_Pos (9UL) |
| |
| #define | PORT2_PDISC_PDIS9_Msk (0x200UL) |
| |
| #define | PORT2_PDISC_PDIS10_Pos (10UL) |
| |
| #define | PORT2_PDISC_PDIS10_Msk (0x400UL) |
| |
| #define | PORT2_PDISC_PDIS11_Pos (11UL) |
| |
| #define | PORT2_PDISC_PDIS11_Msk (0x800UL) |
| |
| #define | PORT2_PDISC_PDIS12_Pos (12UL) |
| |
| #define | PORT2_PDISC_PDIS12_Msk (0x1000UL) |
| |
| #define | PORT2_PDISC_PDIS13_Pos (13UL) |
| |
| #define | PORT2_PDISC_PDIS13_Msk (0x2000UL) |
| |
| #define | PORT2_PDISC_PDIS14_Pos (14UL) |
| |
| #define | PORT2_PDISC_PDIS14_Msk (0x4000UL) |
| |
| #define | PORT2_PDISC_PDIS15_Pos (15UL) |
| |
| #define | PORT2_PDISC_PDIS15_Msk (0x8000UL) |
| |
| #define | PORT2_PPS_PPS0_Pos (0UL) |
| |
| #define | PORT2_PPS_PPS0_Msk (0x1UL) |
| |
| #define | PORT2_PPS_PPS1_Pos (1UL) |
| |
| #define | PORT2_PPS_PPS1_Msk (0x2UL) |
| |
| #define | PORT2_PPS_PPS2_Pos (2UL) |
| |
| #define | PORT2_PPS_PPS2_Msk (0x4UL) |
| |
| #define | PORT2_PPS_PPS3_Pos (3UL) |
| |
| #define | PORT2_PPS_PPS3_Msk (0x8UL) |
| |
| #define | PORT2_PPS_PPS4_Pos (4UL) |
| |
| #define | PORT2_PPS_PPS4_Msk (0x10UL) |
| |
| #define | PORT2_PPS_PPS5_Pos (5UL) |
| |
| #define | PORT2_PPS_PPS5_Msk (0x20UL) |
| |
| #define | PORT2_PPS_PPS6_Pos (6UL) |
| |
| #define | PORT2_PPS_PPS6_Msk (0x40UL) |
| |
| #define | PORT2_PPS_PPS7_Pos (7UL) |
| |
| #define | PORT2_PPS_PPS7_Msk (0x80UL) |
| |
| #define | PORT2_PPS_PPS8_Pos (8UL) |
| |
| #define | PORT2_PPS_PPS8_Msk (0x100UL) |
| |
| #define | PORT2_PPS_PPS9_Pos (9UL) |
| |
| #define | PORT2_PPS_PPS9_Msk (0x200UL) |
| |
| #define | PORT2_PPS_PPS10_Pos (10UL) |
| |
| #define | PORT2_PPS_PPS10_Msk (0x400UL) |
| |
| #define | PORT2_PPS_PPS11_Pos (11UL) |
| |
| #define | PORT2_PPS_PPS11_Msk (0x800UL) |
| |
| #define | PORT2_PPS_PPS12_Pos (12UL) |
| |
| #define | PORT2_PPS_PPS12_Msk (0x1000UL) |
| |
| #define | PORT2_PPS_PPS13_Pos (13UL) |
| |
| #define | PORT2_PPS_PPS13_Msk (0x2000UL) |
| |
| #define | PORT2_PPS_PPS14_Pos (14UL) |
| |
| #define | PORT2_PPS_PPS14_Msk (0x4000UL) |
| |
| #define | PORT2_PPS_PPS15_Pos (15UL) |
| |
| #define | PORT2_PPS_PPS15_Msk (0x8000UL) |
| |
| #define | PORT2_HWSEL_HW0_Pos (0UL) |
| |
| #define | PORT2_HWSEL_HW0_Msk (0x3UL) |
| |
| #define | PORT2_HWSEL_HW1_Pos (2UL) |
| |
| #define | PORT2_HWSEL_HW1_Msk (0xcUL) |
| |
| #define | PORT2_HWSEL_HW2_Pos (4UL) |
| |
| #define | PORT2_HWSEL_HW2_Msk (0x30UL) |
| |
| #define | PORT2_HWSEL_HW3_Pos (6UL) |
| |
| #define | PORT2_HWSEL_HW3_Msk (0xc0UL) |
| |
| #define | PORT2_HWSEL_HW4_Pos (8UL) |
| |
| #define | PORT2_HWSEL_HW4_Msk (0x300UL) |
| |
| #define | PORT2_HWSEL_HW5_Pos (10UL) |
| |
| #define | PORT2_HWSEL_HW5_Msk (0xc00UL) |
| |
| #define | PORT2_HWSEL_HW6_Pos (12UL) |
| |
| #define | PORT2_HWSEL_HW6_Msk (0x3000UL) |
| |
| #define | PORT2_HWSEL_HW7_Pos (14UL) |
| |
| #define | PORT2_HWSEL_HW7_Msk (0xc000UL) |
| |
| #define | PORT2_HWSEL_HW8_Pos (16UL) |
| |
| #define | PORT2_HWSEL_HW8_Msk (0x30000UL) |
| |
| #define | PORT2_HWSEL_HW9_Pos (18UL) |
| |
| #define | PORT2_HWSEL_HW9_Msk (0xc0000UL) |
| |
| #define | PORT2_HWSEL_HW10_Pos (20UL) |
| |
| #define | PORT2_HWSEL_HW10_Msk (0x300000UL) |
| |
| #define | PORT2_HWSEL_HW11_Pos (22UL) |
| |
| #define | PORT2_HWSEL_HW11_Msk (0xc00000UL) |
| |
| #define | PORT2_HWSEL_HW12_Pos (24UL) |
| |
| #define | PORT2_HWSEL_HW12_Msk (0x3000000UL) |
| |
| #define | PORT2_HWSEL_HW13_Pos (26UL) |
| |
| #define | PORT2_HWSEL_HW13_Msk (0xc000000UL) |
| |
| #define | PORT2_HWSEL_HW14_Pos (28UL) |
| |
| #define | PORT2_HWSEL_HW14_Msk (0x30000000UL) |
| |
| #define | PORT2_HWSEL_HW15_Pos (30UL) |
| |
| #define | PORT2_HWSEL_HW15_Msk (0xc0000000UL) |
| |
| #define | PORT3_OUT_P0_Pos (0UL) |
| |
| #define | PORT3_OUT_P0_Msk (0x1UL) |
| |
| #define | PORT3_OUT_P1_Pos (1UL) |
| |
| #define | PORT3_OUT_P1_Msk (0x2UL) |
| |
| #define | PORT3_OUT_P2_Pos (2UL) |
| |
| #define | PORT3_OUT_P2_Msk (0x4UL) |
| |
| #define | PORT3_OUT_P3_Pos (3UL) |
| |
| #define | PORT3_OUT_P3_Msk (0x8UL) |
| |
| #define | PORT3_OUT_P4_Pos (4UL) |
| |
| #define | PORT3_OUT_P4_Msk (0x10UL) |
| |
| #define | PORT3_OUT_P5_Pos (5UL) |
| |
| #define | PORT3_OUT_P5_Msk (0x20UL) |
| |
| #define | PORT3_OUT_P6_Pos (6UL) |
| |
| #define | PORT3_OUT_P6_Msk (0x40UL) |
| |
| #define | PORT3_OUT_P7_Pos (7UL) |
| |
| #define | PORT3_OUT_P7_Msk (0x80UL) |
| |
| #define | PORT3_OUT_P8_Pos (8UL) |
| |
| #define | PORT3_OUT_P8_Msk (0x100UL) |
| |
| #define | PORT3_OUT_P9_Pos (9UL) |
| |
| #define | PORT3_OUT_P9_Msk (0x200UL) |
| |
| #define | PORT3_OUT_P10_Pos (10UL) |
| |
| #define | PORT3_OUT_P10_Msk (0x400UL) |
| |
| #define | PORT3_OUT_P11_Pos (11UL) |
| |
| #define | PORT3_OUT_P11_Msk (0x800UL) |
| |
| #define | PORT3_OUT_P12_Pos (12UL) |
| |
| #define | PORT3_OUT_P12_Msk (0x1000UL) |
| |
| #define | PORT3_OUT_P13_Pos (13UL) |
| |
| #define | PORT3_OUT_P13_Msk (0x2000UL) |
| |
| #define | PORT3_OUT_P14_Pos (14UL) |
| |
| #define | PORT3_OUT_P14_Msk (0x4000UL) |
| |
| #define | PORT3_OUT_P15_Pos (15UL) |
| |
| #define | PORT3_OUT_P15_Msk (0x8000UL) |
| |
| #define | PORT3_OMR_PS0_Pos (0UL) |
| |
| #define | PORT3_OMR_PS0_Msk (0x1UL) |
| |
| #define | PORT3_OMR_PS1_Pos (1UL) |
| |
| #define | PORT3_OMR_PS1_Msk (0x2UL) |
| |
| #define | PORT3_OMR_PS2_Pos (2UL) |
| |
| #define | PORT3_OMR_PS2_Msk (0x4UL) |
| |
| #define | PORT3_OMR_PS3_Pos (3UL) |
| |
| #define | PORT3_OMR_PS3_Msk (0x8UL) |
| |
| #define | PORT3_OMR_PS4_Pos (4UL) |
| |
| #define | PORT3_OMR_PS4_Msk (0x10UL) |
| |
| #define | PORT3_OMR_PS5_Pos (5UL) |
| |
| #define | PORT3_OMR_PS5_Msk (0x20UL) |
| |
| #define | PORT3_OMR_PS6_Pos (6UL) |
| |
| #define | PORT3_OMR_PS6_Msk (0x40UL) |
| |
| #define | PORT3_OMR_PS7_Pos (7UL) |
| |
| #define | PORT3_OMR_PS7_Msk (0x80UL) |
| |
| #define | PORT3_OMR_PS8_Pos (8UL) |
| |
| #define | PORT3_OMR_PS8_Msk (0x100UL) |
| |
| #define | PORT3_OMR_PS9_Pos (9UL) |
| |
| #define | PORT3_OMR_PS9_Msk (0x200UL) |
| |
| #define | PORT3_OMR_PS10_Pos (10UL) |
| |
| #define | PORT3_OMR_PS10_Msk (0x400UL) |
| |
| #define | PORT3_OMR_PS11_Pos (11UL) |
| |
| #define | PORT3_OMR_PS11_Msk (0x800UL) |
| |
| #define | PORT3_OMR_PS12_Pos (12UL) |
| |
| #define | PORT3_OMR_PS12_Msk (0x1000UL) |
| |
| #define | PORT3_OMR_PS13_Pos (13UL) |
| |
| #define | PORT3_OMR_PS13_Msk (0x2000UL) |
| |
| #define | PORT3_OMR_PS14_Pos (14UL) |
| |
| #define | PORT3_OMR_PS14_Msk (0x4000UL) |
| |
| #define | PORT3_OMR_PS15_Pos (15UL) |
| |
| #define | PORT3_OMR_PS15_Msk (0x8000UL) |
| |
| #define | PORT3_OMR_PR0_Pos (16UL) |
| |
| #define | PORT3_OMR_PR0_Msk (0x10000UL) |
| |
| #define | PORT3_OMR_PR1_Pos (17UL) |
| |
| #define | PORT3_OMR_PR1_Msk (0x20000UL) |
| |
| #define | PORT3_OMR_PR2_Pos (18UL) |
| |
| #define | PORT3_OMR_PR2_Msk (0x40000UL) |
| |
| #define | PORT3_OMR_PR3_Pos (19UL) |
| |
| #define | PORT3_OMR_PR3_Msk (0x80000UL) |
| |
| #define | PORT3_OMR_PR4_Pos (20UL) |
| |
| #define | PORT3_OMR_PR4_Msk (0x100000UL) |
| |
| #define | PORT3_OMR_PR5_Pos (21UL) |
| |
| #define | PORT3_OMR_PR5_Msk (0x200000UL) |
| |
| #define | PORT3_OMR_PR6_Pos (22UL) |
| |
| #define | PORT3_OMR_PR6_Msk (0x400000UL) |
| |
| #define | PORT3_OMR_PR7_Pos (23UL) |
| |
| #define | PORT3_OMR_PR7_Msk (0x800000UL) |
| |
| #define | PORT3_OMR_PR8_Pos (24UL) |
| |
| #define | PORT3_OMR_PR8_Msk (0x1000000UL) |
| |
| #define | PORT3_OMR_PR9_Pos (25UL) |
| |
| #define | PORT3_OMR_PR9_Msk (0x2000000UL) |
| |
| #define | PORT3_OMR_PR10_Pos (26UL) |
| |
| #define | PORT3_OMR_PR10_Msk (0x4000000UL) |
| |
| #define | PORT3_OMR_PR11_Pos (27UL) |
| |
| #define | PORT3_OMR_PR11_Msk (0x8000000UL) |
| |
| #define | PORT3_OMR_PR12_Pos (28UL) |
| |
| #define | PORT3_OMR_PR12_Msk (0x10000000UL) |
| |
| #define | PORT3_OMR_PR13_Pos (29UL) |
| |
| #define | PORT3_OMR_PR13_Msk (0x20000000UL) |
| |
| #define | PORT3_OMR_PR14_Pos (30UL) |
| |
| #define | PORT3_OMR_PR14_Msk (0x40000000UL) |
| |
| #define | PORT3_OMR_PR15_Pos (31UL) |
| |
| #define | PORT3_OMR_PR15_Msk (0x80000000UL) |
| |
| #define | PORT3_IOCR0_PC0_Pos (3UL) |
| |
| #define | PORT3_IOCR0_PC0_Msk (0xf8UL) |
| |
| #define | PORT3_IOCR0_PC1_Pos (11UL) |
| |
| #define | PORT3_IOCR0_PC1_Msk (0xf800UL) |
| |
| #define | PORT3_IOCR0_PC2_Pos (19UL) |
| |
| #define | PORT3_IOCR0_PC2_Msk (0xf80000UL) |
| |
| #define | PORT3_IOCR0_PC3_Pos (27UL) |
| |
| #define | PORT3_IOCR0_PC3_Msk (0xf8000000UL) |
| |
| #define | PORT3_IOCR4_PC4_Pos (3UL) |
| |
| #define | PORT3_IOCR4_PC4_Msk (0xf8UL) |
| |
| #define | PORT3_IOCR4_PC5_Pos (11UL) |
| |
| #define | PORT3_IOCR4_PC5_Msk (0xf800UL) |
| |
| #define | PORT3_IOCR4_PC6_Pos (19UL) |
| |
| #define | PORT3_IOCR4_PC6_Msk (0xf80000UL) |
| |
| #define | PORT3_IOCR4_PC7_Pos (27UL) |
| |
| #define | PORT3_IOCR4_PC7_Msk (0xf8000000UL) |
| |
| #define | PORT3_IOCR8_PC8_Pos (3UL) |
| |
| #define | PORT3_IOCR8_PC8_Msk (0xf8UL) |
| |
| #define | PORT3_IOCR8_PC9_Pos (11UL) |
| |
| #define | PORT3_IOCR8_PC9_Msk (0xf800UL) |
| |
| #define | PORT3_IOCR8_PC10_Pos (19UL) |
| |
| #define | PORT3_IOCR8_PC10_Msk (0xf80000UL) |
| |
| #define | PORT3_IOCR8_PC11_Pos (27UL) |
| |
| #define | PORT3_IOCR8_PC11_Msk (0xf8000000UL) |
| |
| #define | PORT3_IOCR12_PC12_Pos (3UL) |
| |
| #define | PORT3_IOCR12_PC12_Msk (0xf8UL) |
| |
| #define | PORT3_IOCR12_PC13_Pos (11UL) |
| |
| #define | PORT3_IOCR12_PC13_Msk (0xf800UL) |
| |
| #define | PORT3_IOCR12_PC14_Pos (19UL) |
| |
| #define | PORT3_IOCR12_PC14_Msk (0xf80000UL) |
| |
| #define | PORT3_IOCR12_PC15_Pos (27UL) |
| |
| #define | PORT3_IOCR12_PC15_Msk (0xf8000000UL) |
| |
| #define | PORT3_IN_P0_Pos (0UL) |
| |
| #define | PORT3_IN_P0_Msk (0x1UL) |
| |
| #define | PORT3_IN_P1_Pos (1UL) |
| |
| #define | PORT3_IN_P1_Msk (0x2UL) |
| |
| #define | PORT3_IN_P2_Pos (2UL) |
| |
| #define | PORT3_IN_P2_Msk (0x4UL) |
| |
| #define | PORT3_IN_P3_Pos (3UL) |
| |
| #define | PORT3_IN_P3_Msk (0x8UL) |
| |
| #define | PORT3_IN_P4_Pos (4UL) |
| |
| #define | PORT3_IN_P4_Msk (0x10UL) |
| |
| #define | PORT3_IN_P5_Pos (5UL) |
| |
| #define | PORT3_IN_P5_Msk (0x20UL) |
| |
| #define | PORT3_IN_P6_Pos (6UL) |
| |
| #define | PORT3_IN_P6_Msk (0x40UL) |
| |
| #define | PORT3_IN_P7_Pos (7UL) |
| |
| #define | PORT3_IN_P7_Msk (0x80UL) |
| |
| #define | PORT3_IN_P8_Pos (8UL) |
| |
| #define | PORT3_IN_P8_Msk (0x100UL) |
| |
| #define | PORT3_IN_P9_Pos (9UL) |
| |
| #define | PORT3_IN_P9_Msk (0x200UL) |
| |
| #define | PORT3_IN_P10_Pos (10UL) |
| |
| #define | PORT3_IN_P10_Msk (0x400UL) |
| |
| #define | PORT3_IN_P11_Pos (11UL) |
| |
| #define | PORT3_IN_P11_Msk (0x800UL) |
| |
| #define | PORT3_IN_P12_Pos (12UL) |
| |
| #define | PORT3_IN_P12_Msk (0x1000UL) |
| |
| #define | PORT3_IN_P13_Pos (13UL) |
| |
| #define | PORT3_IN_P13_Msk (0x2000UL) |
| |
| #define | PORT3_IN_P14_Pos (14UL) |
| |
| #define | PORT3_IN_P14_Msk (0x4000UL) |
| |
| #define | PORT3_IN_P15_Pos (15UL) |
| |
| #define | PORT3_IN_P15_Msk (0x8000UL) |
| |
| #define | PORT3_PDR0_PD0_Pos (0UL) |
| |
| #define | PORT3_PDR0_PD0_Msk (0x7UL) |
| |
| #define | PORT3_PDR0_PD1_Pos (4UL) |
| |
| #define | PORT3_PDR0_PD1_Msk (0x70UL) |
| |
| #define | PORT3_PDR0_PD2_Pos (8UL) |
| |
| #define | PORT3_PDR0_PD2_Msk (0x700UL) |
| |
| #define | PORT3_PDR0_PD3_Pos (12UL) |
| |
| #define | PORT3_PDR0_PD3_Msk (0x7000UL) |
| |
| #define | PORT3_PDR0_PD4_Pos (16UL) |
| |
| #define | PORT3_PDR0_PD4_Msk (0x70000UL) |
| |
| #define | PORT3_PDR0_PD5_Pos (20UL) |
| |
| #define | PORT3_PDR0_PD5_Msk (0x700000UL) |
| |
| #define | PORT3_PDR0_PD6_Pos (24UL) |
| |
| #define | PORT3_PDR0_PD6_Msk (0x7000000UL) |
| |
| #define | PORT3_PDR0_PD7_Pos (28UL) |
| |
| #define | PORT3_PDR0_PD7_Msk (0x70000000UL) |
| |
| #define | PORT3_PDR1_PD8_Pos (0UL) |
| |
| #define | PORT3_PDR1_PD8_Msk (0x7UL) |
| |
| #define | PORT3_PDR1_PD9_Pos (4UL) |
| |
| #define | PORT3_PDR1_PD9_Msk (0x70UL) |
| |
| #define | PORT3_PDR1_PD10_Pos (8UL) |
| |
| #define | PORT3_PDR1_PD10_Msk (0x700UL) |
| |
| #define | PORT3_PDR1_PD11_Pos (12UL) |
| |
| #define | PORT3_PDR1_PD11_Msk (0x7000UL) |
| |
| #define | PORT3_PDR1_PD12_Pos (16UL) |
| |
| #define | PORT3_PDR1_PD12_Msk (0x70000UL) |
| |
| #define | PORT3_PDR1_PD13_Pos (20UL) |
| |
| #define | PORT3_PDR1_PD13_Msk (0x700000UL) |
| |
| #define | PORT3_PDR1_PD14_Pos (24UL) |
| |
| #define | PORT3_PDR1_PD14_Msk (0x7000000UL) |
| |
| #define | PORT3_PDR1_PD15_Pos (28UL) |
| |
| #define | PORT3_PDR1_PD15_Msk (0x70000000UL) |
| |
| #define | PORT3_PDISC_PDIS0_Pos (0UL) |
| |
| #define | PORT3_PDISC_PDIS0_Msk (0x1UL) |
| |
| #define | PORT3_PDISC_PDIS1_Pos (1UL) |
| |
| #define | PORT3_PDISC_PDIS1_Msk (0x2UL) |
| |
| #define | PORT3_PDISC_PDIS2_Pos (2UL) |
| |
| #define | PORT3_PDISC_PDIS2_Msk (0x4UL) |
| |
| #define | PORT3_PDISC_PDIS3_Pos (3UL) |
| |
| #define | PORT3_PDISC_PDIS3_Msk (0x8UL) |
| |
| #define | PORT3_PDISC_PDIS4_Pos (4UL) |
| |
| #define | PORT3_PDISC_PDIS4_Msk (0x10UL) |
| |
| #define | PORT3_PDISC_PDIS5_Pos (5UL) |
| |
| #define | PORT3_PDISC_PDIS5_Msk (0x20UL) |
| |
| #define | PORT3_PDISC_PDIS6_Pos (6UL) |
| |
| #define | PORT3_PDISC_PDIS6_Msk (0x40UL) |
| |
| #define | PORT3_PDISC_PDIS7_Pos (7UL) |
| |
| #define | PORT3_PDISC_PDIS7_Msk (0x80UL) |
| |
| #define | PORT3_PDISC_PDIS8_Pos (8UL) |
| |
| #define | PORT3_PDISC_PDIS8_Msk (0x100UL) |
| |
| #define | PORT3_PDISC_PDIS9_Pos (9UL) |
| |
| #define | PORT3_PDISC_PDIS9_Msk (0x200UL) |
| |
| #define | PORT3_PDISC_PDIS10_Pos (10UL) |
| |
| #define | PORT3_PDISC_PDIS10_Msk (0x400UL) |
| |
| #define | PORT3_PDISC_PDIS11_Pos (11UL) |
| |
| #define | PORT3_PDISC_PDIS11_Msk (0x800UL) |
| |
| #define | PORT3_PDISC_PDIS12_Pos (12UL) |
| |
| #define | PORT3_PDISC_PDIS12_Msk (0x1000UL) |
| |
| #define | PORT3_PDISC_PDIS13_Pos (13UL) |
| |
| #define | PORT3_PDISC_PDIS13_Msk (0x2000UL) |
| |
| #define | PORT3_PDISC_PDIS14_Pos (14UL) |
| |
| #define | PORT3_PDISC_PDIS14_Msk (0x4000UL) |
| |
| #define | PORT3_PDISC_PDIS15_Pos (15UL) |
| |
| #define | PORT3_PDISC_PDIS15_Msk (0x8000UL) |
| |
| #define | PORT3_PPS_PPS0_Pos (0UL) |
| |
| #define | PORT3_PPS_PPS0_Msk (0x1UL) |
| |
| #define | PORT3_PPS_PPS1_Pos (1UL) |
| |
| #define | PORT3_PPS_PPS1_Msk (0x2UL) |
| |
| #define | PORT3_PPS_PPS2_Pos (2UL) |
| |
| #define | PORT3_PPS_PPS2_Msk (0x4UL) |
| |
| #define | PORT3_PPS_PPS3_Pos (3UL) |
| |
| #define | PORT3_PPS_PPS3_Msk (0x8UL) |
| |
| #define | PORT3_PPS_PPS4_Pos (4UL) |
| |
| #define | PORT3_PPS_PPS4_Msk (0x10UL) |
| |
| #define | PORT3_PPS_PPS5_Pos (5UL) |
| |
| #define | PORT3_PPS_PPS5_Msk (0x20UL) |
| |
| #define | PORT3_PPS_PPS6_Pos (6UL) |
| |
| #define | PORT3_PPS_PPS6_Msk (0x40UL) |
| |
| #define | PORT3_PPS_PPS7_Pos (7UL) |
| |
| #define | PORT3_PPS_PPS7_Msk (0x80UL) |
| |
| #define | PORT3_PPS_PPS8_Pos (8UL) |
| |
| #define | PORT3_PPS_PPS8_Msk (0x100UL) |
| |
| #define | PORT3_PPS_PPS9_Pos (9UL) |
| |
| #define | PORT3_PPS_PPS9_Msk (0x200UL) |
| |
| #define | PORT3_PPS_PPS10_Pos (10UL) |
| |
| #define | PORT3_PPS_PPS10_Msk (0x400UL) |
| |
| #define | PORT3_PPS_PPS11_Pos (11UL) |
| |
| #define | PORT3_PPS_PPS11_Msk (0x800UL) |
| |
| #define | PORT3_PPS_PPS12_Pos (12UL) |
| |
| #define | PORT3_PPS_PPS12_Msk (0x1000UL) |
| |
| #define | PORT3_PPS_PPS13_Pos (13UL) |
| |
| #define | PORT3_PPS_PPS13_Msk (0x2000UL) |
| |
| #define | PORT3_PPS_PPS14_Pos (14UL) |
| |
| #define | PORT3_PPS_PPS14_Msk (0x4000UL) |
| |
| #define | PORT3_PPS_PPS15_Pos (15UL) |
| |
| #define | PORT3_PPS_PPS15_Msk (0x8000UL) |
| |
| #define | PORT3_HWSEL_HW0_Pos (0UL) |
| |
| #define | PORT3_HWSEL_HW0_Msk (0x3UL) |
| |
| #define | PORT3_HWSEL_HW1_Pos (2UL) |
| |
| #define | PORT3_HWSEL_HW1_Msk (0xcUL) |
| |
| #define | PORT3_HWSEL_HW2_Pos (4UL) |
| |
| #define | PORT3_HWSEL_HW2_Msk (0x30UL) |
| |
| #define | PORT3_HWSEL_HW3_Pos (6UL) |
| |
| #define | PORT3_HWSEL_HW3_Msk (0xc0UL) |
| |
| #define | PORT3_HWSEL_HW4_Pos (8UL) |
| |
| #define | PORT3_HWSEL_HW4_Msk (0x300UL) |
| |
| #define | PORT3_HWSEL_HW5_Pos (10UL) |
| |
| #define | PORT3_HWSEL_HW5_Msk (0xc00UL) |
| |
| #define | PORT3_HWSEL_HW6_Pos (12UL) |
| |
| #define | PORT3_HWSEL_HW6_Msk (0x3000UL) |
| |
| #define | PORT3_HWSEL_HW7_Pos (14UL) |
| |
| #define | PORT3_HWSEL_HW7_Msk (0xc000UL) |
| |
| #define | PORT3_HWSEL_HW8_Pos (16UL) |
| |
| #define | PORT3_HWSEL_HW8_Msk (0x30000UL) |
| |
| #define | PORT3_HWSEL_HW9_Pos (18UL) |
| |
| #define | PORT3_HWSEL_HW9_Msk (0xc0000UL) |
| |
| #define | PORT3_HWSEL_HW10_Pos (20UL) |
| |
| #define | PORT3_HWSEL_HW10_Msk (0x300000UL) |
| |
| #define | PORT3_HWSEL_HW11_Pos (22UL) |
| |
| #define | PORT3_HWSEL_HW11_Msk (0xc00000UL) |
| |
| #define | PORT3_HWSEL_HW12_Pos (24UL) |
| |
| #define | PORT3_HWSEL_HW12_Msk (0x3000000UL) |
| |
| #define | PORT3_HWSEL_HW13_Pos (26UL) |
| |
| #define | PORT3_HWSEL_HW13_Msk (0xc000000UL) |
| |
| #define | PORT3_HWSEL_HW14_Pos (28UL) |
| |
| #define | PORT3_HWSEL_HW14_Msk (0x30000000UL) |
| |
| #define | PORT3_HWSEL_HW15_Pos (30UL) |
| |
| #define | PORT3_HWSEL_HW15_Msk (0xc0000000UL) |
| |
| #define | PORT4_OUT_P0_Pos (0UL) |
| |
| #define | PORT4_OUT_P0_Msk (0x1UL) |
| |
| #define | PORT4_OUT_P1_Pos (1UL) |
| |
| #define | PORT4_OUT_P1_Msk (0x2UL) |
| |
| #define | PORT4_OUT_P2_Pos (2UL) |
| |
| #define | PORT4_OUT_P2_Msk (0x4UL) |
| |
| #define | PORT4_OUT_P3_Pos (3UL) |
| |
| #define | PORT4_OUT_P3_Msk (0x8UL) |
| |
| #define | PORT4_OUT_P4_Pos (4UL) |
| |
| #define | PORT4_OUT_P4_Msk (0x10UL) |
| |
| #define | PORT4_OUT_P5_Pos (5UL) |
| |
| #define | PORT4_OUT_P5_Msk (0x20UL) |
| |
| #define | PORT4_OUT_P6_Pos (6UL) |
| |
| #define | PORT4_OUT_P6_Msk (0x40UL) |
| |
| #define | PORT4_OUT_P7_Pos (7UL) |
| |
| #define | PORT4_OUT_P7_Msk (0x80UL) |
| |
| #define | PORT4_OUT_P8_Pos (8UL) |
| |
| #define | PORT4_OUT_P8_Msk (0x100UL) |
| |
| #define | PORT4_OUT_P9_Pos (9UL) |
| |
| #define | PORT4_OUT_P9_Msk (0x200UL) |
| |
| #define | PORT4_OUT_P10_Pos (10UL) |
| |
| #define | PORT4_OUT_P10_Msk (0x400UL) |
| |
| #define | PORT4_OUT_P11_Pos (11UL) |
| |
| #define | PORT4_OUT_P11_Msk (0x800UL) |
| |
| #define | PORT4_OUT_P12_Pos (12UL) |
| |
| #define | PORT4_OUT_P12_Msk (0x1000UL) |
| |
| #define | PORT4_OUT_P13_Pos (13UL) |
| |
| #define | PORT4_OUT_P13_Msk (0x2000UL) |
| |
| #define | PORT4_OUT_P14_Pos (14UL) |
| |
| #define | PORT4_OUT_P14_Msk (0x4000UL) |
| |
| #define | PORT4_OUT_P15_Pos (15UL) |
| |
| #define | PORT4_OUT_P15_Msk (0x8000UL) |
| |
| #define | PORT4_OMR_PS0_Pos (0UL) |
| |
| #define | PORT4_OMR_PS0_Msk (0x1UL) |
| |
| #define | PORT4_OMR_PS1_Pos (1UL) |
| |
| #define | PORT4_OMR_PS1_Msk (0x2UL) |
| |
| #define | PORT4_OMR_PS2_Pos (2UL) |
| |
| #define | PORT4_OMR_PS2_Msk (0x4UL) |
| |
| #define | PORT4_OMR_PS3_Pos (3UL) |
| |
| #define | PORT4_OMR_PS3_Msk (0x8UL) |
| |
| #define | PORT4_OMR_PS4_Pos (4UL) |
| |
| #define | PORT4_OMR_PS4_Msk (0x10UL) |
| |
| #define | PORT4_OMR_PS5_Pos (5UL) |
| |
| #define | PORT4_OMR_PS5_Msk (0x20UL) |
| |
| #define | PORT4_OMR_PS6_Pos (6UL) |
| |
| #define | PORT4_OMR_PS6_Msk (0x40UL) |
| |
| #define | PORT4_OMR_PS7_Pos (7UL) |
| |
| #define | PORT4_OMR_PS7_Msk (0x80UL) |
| |
| #define | PORT4_OMR_PS8_Pos (8UL) |
| |
| #define | PORT4_OMR_PS8_Msk (0x100UL) |
| |
| #define | PORT4_OMR_PS9_Pos (9UL) |
| |
| #define | PORT4_OMR_PS9_Msk (0x200UL) |
| |
| #define | PORT4_OMR_PS10_Pos (10UL) |
| |
| #define | PORT4_OMR_PS10_Msk (0x400UL) |
| |
| #define | PORT4_OMR_PS11_Pos (11UL) |
| |
| #define | PORT4_OMR_PS11_Msk (0x800UL) |
| |
| #define | PORT4_OMR_PS12_Pos (12UL) |
| |
| #define | PORT4_OMR_PS12_Msk (0x1000UL) |
| |
| #define | PORT4_OMR_PS13_Pos (13UL) |
| |
| #define | PORT4_OMR_PS13_Msk (0x2000UL) |
| |
| #define | PORT4_OMR_PS14_Pos (14UL) |
| |
| #define | PORT4_OMR_PS14_Msk (0x4000UL) |
| |
| #define | PORT4_OMR_PS15_Pos (15UL) |
| |
| #define | PORT4_OMR_PS15_Msk (0x8000UL) |
| |
| #define | PORT4_OMR_PR0_Pos (16UL) |
| |
| #define | PORT4_OMR_PR0_Msk (0x10000UL) |
| |
| #define | PORT4_OMR_PR1_Pos (17UL) |
| |
| #define | PORT4_OMR_PR1_Msk (0x20000UL) |
| |
| #define | PORT4_OMR_PR2_Pos (18UL) |
| |
| #define | PORT4_OMR_PR2_Msk (0x40000UL) |
| |
| #define | PORT4_OMR_PR3_Pos (19UL) |
| |
| #define | PORT4_OMR_PR3_Msk (0x80000UL) |
| |
| #define | PORT4_OMR_PR4_Pos (20UL) |
| |
| #define | PORT4_OMR_PR4_Msk (0x100000UL) |
| |
| #define | PORT4_OMR_PR5_Pos (21UL) |
| |
| #define | PORT4_OMR_PR5_Msk (0x200000UL) |
| |
| #define | PORT4_OMR_PR6_Pos (22UL) |
| |
| #define | PORT4_OMR_PR6_Msk (0x400000UL) |
| |
| #define | PORT4_OMR_PR7_Pos (23UL) |
| |
| #define | PORT4_OMR_PR7_Msk (0x800000UL) |
| |
| #define | PORT4_OMR_PR8_Pos (24UL) |
| |
| #define | PORT4_OMR_PR8_Msk (0x1000000UL) |
| |
| #define | PORT4_OMR_PR9_Pos (25UL) |
| |
| #define | PORT4_OMR_PR9_Msk (0x2000000UL) |
| |
| #define | PORT4_OMR_PR10_Pos (26UL) |
| |
| #define | PORT4_OMR_PR10_Msk (0x4000000UL) |
| |
| #define | PORT4_OMR_PR11_Pos (27UL) |
| |
| #define | PORT4_OMR_PR11_Msk (0x8000000UL) |
| |
| #define | PORT4_OMR_PR12_Pos (28UL) |
| |
| #define | PORT4_OMR_PR12_Msk (0x10000000UL) |
| |
| #define | PORT4_OMR_PR13_Pos (29UL) |
| |
| #define | PORT4_OMR_PR13_Msk (0x20000000UL) |
| |
| #define | PORT4_OMR_PR14_Pos (30UL) |
| |
| #define | PORT4_OMR_PR14_Msk (0x40000000UL) |
| |
| #define | PORT4_OMR_PR15_Pos (31UL) |
| |
| #define | PORT4_OMR_PR15_Msk (0x80000000UL) |
| |
| #define | PORT4_IOCR0_PC0_Pos (3UL) |
| |
| #define | PORT4_IOCR0_PC0_Msk (0xf8UL) |
| |
| #define | PORT4_IOCR0_PC1_Pos (11UL) |
| |
| #define | PORT4_IOCR0_PC1_Msk (0xf800UL) |
| |
| #define | PORT4_IOCR0_PC2_Pos (19UL) |
| |
| #define | PORT4_IOCR0_PC2_Msk (0xf80000UL) |
| |
| #define | PORT4_IOCR0_PC3_Pos (27UL) |
| |
| #define | PORT4_IOCR0_PC3_Msk (0xf8000000UL) |
| |
| #define | PORT4_IOCR4_PC4_Pos (3UL) |
| |
| #define | PORT4_IOCR4_PC4_Msk (0xf8UL) |
| |
| #define | PORT4_IOCR4_PC5_Pos (11UL) |
| |
| #define | PORT4_IOCR4_PC5_Msk (0xf800UL) |
| |
| #define | PORT4_IOCR4_PC6_Pos (19UL) |
| |
| #define | PORT4_IOCR4_PC6_Msk (0xf80000UL) |
| |
| #define | PORT4_IOCR4_PC7_Pos (27UL) |
| |
| #define | PORT4_IOCR4_PC7_Msk (0xf8000000UL) |
| |
| #define | PORT4_IN_P0_Pos (0UL) |
| |
| #define | PORT4_IN_P0_Msk (0x1UL) |
| |
| #define | PORT4_IN_P1_Pos (1UL) |
| |
| #define | PORT4_IN_P1_Msk (0x2UL) |
| |
| #define | PORT4_IN_P2_Pos (2UL) |
| |
| #define | PORT4_IN_P2_Msk (0x4UL) |
| |
| #define | PORT4_IN_P3_Pos (3UL) |
| |
| #define | PORT4_IN_P3_Msk (0x8UL) |
| |
| #define | PORT4_IN_P4_Pos (4UL) |
| |
| #define | PORT4_IN_P4_Msk (0x10UL) |
| |
| #define | PORT4_IN_P5_Pos (5UL) |
| |
| #define | PORT4_IN_P5_Msk (0x20UL) |
| |
| #define | PORT4_IN_P6_Pos (6UL) |
| |
| #define | PORT4_IN_P6_Msk (0x40UL) |
| |
| #define | PORT4_IN_P7_Pos (7UL) |
| |
| #define | PORT4_IN_P7_Msk (0x80UL) |
| |
| #define | PORT4_IN_P8_Pos (8UL) |
| |
| #define | PORT4_IN_P8_Msk (0x100UL) |
| |
| #define | PORT4_IN_P9_Pos (9UL) |
| |
| #define | PORT4_IN_P9_Msk (0x200UL) |
| |
| #define | PORT4_IN_P10_Pos (10UL) |
| |
| #define | PORT4_IN_P10_Msk (0x400UL) |
| |
| #define | PORT4_IN_P11_Pos (11UL) |
| |
| #define | PORT4_IN_P11_Msk (0x800UL) |
| |
| #define | PORT4_IN_P12_Pos (12UL) |
| |
| #define | PORT4_IN_P12_Msk (0x1000UL) |
| |
| #define | PORT4_IN_P13_Pos (13UL) |
| |
| #define | PORT4_IN_P13_Msk (0x2000UL) |
| |
| #define | PORT4_IN_P14_Pos (14UL) |
| |
| #define | PORT4_IN_P14_Msk (0x4000UL) |
| |
| #define | PORT4_IN_P15_Pos (15UL) |
| |
| #define | PORT4_IN_P15_Msk (0x8000UL) |
| |
| #define | PORT4_PDR0_PD0_Pos (0UL) |
| |
| #define | PORT4_PDR0_PD0_Msk (0x7UL) |
| |
| #define | PORT4_PDR0_PD1_Pos (4UL) |
| |
| #define | PORT4_PDR0_PD1_Msk (0x70UL) |
| |
| #define | PORT4_PDR0_PD2_Pos (8UL) |
| |
| #define | PORT4_PDR0_PD2_Msk (0x700UL) |
| |
| #define | PORT4_PDR0_PD3_Pos (12UL) |
| |
| #define | PORT4_PDR0_PD3_Msk (0x7000UL) |
| |
| #define | PORT4_PDR0_PD4_Pos (16UL) |
| |
| #define | PORT4_PDR0_PD4_Msk (0x70000UL) |
| |
| #define | PORT4_PDR0_PD5_Pos (20UL) |
| |
| #define | PORT4_PDR0_PD5_Msk (0x700000UL) |
| |
| #define | PORT4_PDR0_PD6_Pos (24UL) |
| |
| #define | PORT4_PDR0_PD6_Msk (0x7000000UL) |
| |
| #define | PORT4_PDR0_PD7_Pos (28UL) |
| |
| #define | PORT4_PDR0_PD7_Msk (0x70000000UL) |
| |
| #define | PORT4_PDISC_PDIS0_Pos (0UL) |
| |
| #define | PORT4_PDISC_PDIS0_Msk (0x1UL) |
| |
| #define | PORT4_PDISC_PDIS1_Pos (1UL) |
| |
| #define | PORT4_PDISC_PDIS1_Msk (0x2UL) |
| |
| #define | PORT4_PDISC_PDIS2_Pos (2UL) |
| |
| #define | PORT4_PDISC_PDIS2_Msk (0x4UL) |
| |
| #define | PORT4_PDISC_PDIS3_Pos (3UL) |
| |
| #define | PORT4_PDISC_PDIS3_Msk (0x8UL) |
| |
| #define | PORT4_PDISC_PDIS4_Pos (4UL) |
| |
| #define | PORT4_PDISC_PDIS4_Msk (0x10UL) |
| |
| #define | PORT4_PDISC_PDIS5_Pos (5UL) |
| |
| #define | PORT4_PDISC_PDIS5_Msk (0x20UL) |
| |
| #define | PORT4_PDISC_PDIS6_Pos (6UL) |
| |
| #define | PORT4_PDISC_PDIS6_Msk (0x40UL) |
| |
| #define | PORT4_PDISC_PDIS7_Pos (7UL) |
| |
| #define | PORT4_PDISC_PDIS7_Msk (0x80UL) |
| |
| #define | PORT4_PDISC_PDIS8_Pos (8UL) |
| |
| #define | PORT4_PDISC_PDIS8_Msk (0x100UL) |
| |
| #define | PORT4_PDISC_PDIS9_Pos (9UL) |
| |
| #define | PORT4_PDISC_PDIS9_Msk (0x200UL) |
| |
| #define | PORT4_PDISC_PDIS10_Pos (10UL) |
| |
| #define | PORT4_PDISC_PDIS10_Msk (0x400UL) |
| |
| #define | PORT4_PDISC_PDIS11_Pos (11UL) |
| |
| #define | PORT4_PDISC_PDIS11_Msk (0x800UL) |
| |
| #define | PORT4_PDISC_PDIS12_Pos (12UL) |
| |
| #define | PORT4_PDISC_PDIS12_Msk (0x1000UL) |
| |
| #define | PORT4_PDISC_PDIS13_Pos (13UL) |
| |
| #define | PORT4_PDISC_PDIS13_Msk (0x2000UL) |
| |
| #define | PORT4_PDISC_PDIS14_Pos (14UL) |
| |
| #define | PORT4_PDISC_PDIS14_Msk (0x4000UL) |
| |
| #define | PORT4_PDISC_PDIS15_Pos (15UL) |
| |
| #define | PORT4_PDISC_PDIS15_Msk (0x8000UL) |
| |
| #define | PORT4_PPS_PPS0_Pos (0UL) |
| |
| #define | PORT4_PPS_PPS0_Msk (0x1UL) |
| |
| #define | PORT4_PPS_PPS1_Pos (1UL) |
| |
| #define | PORT4_PPS_PPS1_Msk (0x2UL) |
| |
| #define | PORT4_PPS_PPS2_Pos (2UL) |
| |
| #define | PORT4_PPS_PPS2_Msk (0x4UL) |
| |
| #define | PORT4_PPS_PPS3_Pos (3UL) |
| |
| #define | PORT4_PPS_PPS3_Msk (0x8UL) |
| |
| #define | PORT4_PPS_PPS4_Pos (4UL) |
| |
| #define | PORT4_PPS_PPS4_Msk (0x10UL) |
| |
| #define | PORT4_PPS_PPS5_Pos (5UL) |
| |
| #define | PORT4_PPS_PPS5_Msk (0x20UL) |
| |
| #define | PORT4_PPS_PPS6_Pos (6UL) |
| |
| #define | PORT4_PPS_PPS6_Msk (0x40UL) |
| |
| #define | PORT4_PPS_PPS7_Pos (7UL) |
| |
| #define | PORT4_PPS_PPS7_Msk (0x80UL) |
| |
| #define | PORT4_PPS_PPS8_Pos (8UL) |
| |
| #define | PORT4_PPS_PPS8_Msk (0x100UL) |
| |
| #define | PORT4_PPS_PPS9_Pos (9UL) |
| |
| #define | PORT4_PPS_PPS9_Msk (0x200UL) |
| |
| #define | PORT4_PPS_PPS10_Pos (10UL) |
| |
| #define | PORT4_PPS_PPS10_Msk (0x400UL) |
| |
| #define | PORT4_PPS_PPS11_Pos (11UL) |
| |
| #define | PORT4_PPS_PPS11_Msk (0x800UL) |
| |
| #define | PORT4_PPS_PPS12_Pos (12UL) |
| |
| #define | PORT4_PPS_PPS12_Msk (0x1000UL) |
| |
| #define | PORT4_PPS_PPS13_Pos (13UL) |
| |
| #define | PORT4_PPS_PPS13_Msk (0x2000UL) |
| |
| #define | PORT4_PPS_PPS14_Pos (14UL) |
| |
| #define | PORT4_PPS_PPS14_Msk (0x4000UL) |
| |
| #define | PORT4_PPS_PPS15_Pos (15UL) |
| |
| #define | PORT4_PPS_PPS15_Msk (0x8000UL) |
| |
| #define | PORT4_HWSEL_HW0_Pos (0UL) |
| |
| #define | PORT4_HWSEL_HW0_Msk (0x3UL) |
| |
| #define | PORT4_HWSEL_HW1_Pos (2UL) |
| |
| #define | PORT4_HWSEL_HW1_Msk (0xcUL) |
| |
| #define | PORT4_HWSEL_HW2_Pos (4UL) |
| |
| #define | PORT4_HWSEL_HW2_Msk (0x30UL) |
| |
| #define | PORT4_HWSEL_HW3_Pos (6UL) |
| |
| #define | PORT4_HWSEL_HW3_Msk (0xc0UL) |
| |
| #define | PORT4_HWSEL_HW4_Pos (8UL) |
| |
| #define | PORT4_HWSEL_HW4_Msk (0x300UL) |
| |
| #define | PORT4_HWSEL_HW5_Pos (10UL) |
| |
| #define | PORT4_HWSEL_HW5_Msk (0xc00UL) |
| |
| #define | PORT4_HWSEL_HW6_Pos (12UL) |
| |
| #define | PORT4_HWSEL_HW6_Msk (0x3000UL) |
| |
| #define | PORT4_HWSEL_HW7_Pos (14UL) |
| |
| #define | PORT4_HWSEL_HW7_Msk (0xc000UL) |
| |
| #define | PORT4_HWSEL_HW8_Pos (16UL) |
| |
| #define | PORT4_HWSEL_HW8_Msk (0x30000UL) |
| |
| #define | PORT4_HWSEL_HW9_Pos (18UL) |
| |
| #define | PORT4_HWSEL_HW9_Msk (0xc0000UL) |
| |
| #define | PORT4_HWSEL_HW10_Pos (20UL) |
| |
| #define | PORT4_HWSEL_HW10_Msk (0x300000UL) |
| |
| #define | PORT4_HWSEL_HW11_Pos (22UL) |
| |
| #define | PORT4_HWSEL_HW11_Msk (0xc00000UL) |
| |
| #define | PORT4_HWSEL_HW12_Pos (24UL) |
| |
| #define | PORT4_HWSEL_HW12_Msk (0x3000000UL) |
| |
| #define | PORT4_HWSEL_HW13_Pos (26UL) |
| |
| #define | PORT4_HWSEL_HW13_Msk (0xc000000UL) |
| |
| #define | PORT4_HWSEL_HW14_Pos (28UL) |
| |
| #define | PORT4_HWSEL_HW14_Msk (0x30000000UL) |
| |
| #define | PORT4_HWSEL_HW15_Pos (30UL) |
| |
| #define | PORT4_HWSEL_HW15_Msk (0xc0000000UL) |
| |
| #define | PORT5_OUT_P0_Pos (0UL) |
| |
| #define | PORT5_OUT_P0_Msk (0x1UL) |
| |
| #define | PORT5_OUT_P1_Pos (1UL) |
| |
| #define | PORT5_OUT_P1_Msk (0x2UL) |
| |
| #define | PORT5_OUT_P2_Pos (2UL) |
| |
| #define | PORT5_OUT_P2_Msk (0x4UL) |
| |
| #define | PORT5_OUT_P3_Pos (3UL) |
| |
| #define | PORT5_OUT_P3_Msk (0x8UL) |
| |
| #define | PORT5_OUT_P4_Pos (4UL) |
| |
| #define | PORT5_OUT_P4_Msk (0x10UL) |
| |
| #define | PORT5_OUT_P5_Pos (5UL) |
| |
| #define | PORT5_OUT_P5_Msk (0x20UL) |
| |
| #define | PORT5_OUT_P6_Pos (6UL) |
| |
| #define | PORT5_OUT_P6_Msk (0x40UL) |
| |
| #define | PORT5_OUT_P7_Pos (7UL) |
| |
| #define | PORT5_OUT_P7_Msk (0x80UL) |
| |
| #define | PORT5_OUT_P8_Pos (8UL) |
| |
| #define | PORT5_OUT_P8_Msk (0x100UL) |
| |
| #define | PORT5_OUT_P9_Pos (9UL) |
| |
| #define | PORT5_OUT_P9_Msk (0x200UL) |
| |
| #define | PORT5_OUT_P10_Pos (10UL) |
| |
| #define | PORT5_OUT_P10_Msk (0x400UL) |
| |
| #define | PORT5_OUT_P11_Pos (11UL) |
| |
| #define | PORT5_OUT_P11_Msk (0x800UL) |
| |
| #define | PORT5_OUT_P12_Pos (12UL) |
| |
| #define | PORT5_OUT_P12_Msk (0x1000UL) |
| |
| #define | PORT5_OUT_P13_Pos (13UL) |
| |
| #define | PORT5_OUT_P13_Msk (0x2000UL) |
| |
| #define | PORT5_OUT_P14_Pos (14UL) |
| |
| #define | PORT5_OUT_P14_Msk (0x4000UL) |
| |
| #define | PORT5_OUT_P15_Pos (15UL) |
| |
| #define | PORT5_OUT_P15_Msk (0x8000UL) |
| |
| #define | PORT5_OMR_PS0_Pos (0UL) |
| |
| #define | PORT5_OMR_PS0_Msk (0x1UL) |
| |
| #define | PORT5_OMR_PS1_Pos (1UL) |
| |
| #define | PORT5_OMR_PS1_Msk (0x2UL) |
| |
| #define | PORT5_OMR_PS2_Pos (2UL) |
| |
| #define | PORT5_OMR_PS2_Msk (0x4UL) |
| |
| #define | PORT5_OMR_PS3_Pos (3UL) |
| |
| #define | PORT5_OMR_PS3_Msk (0x8UL) |
| |
| #define | PORT5_OMR_PS4_Pos (4UL) |
| |
| #define | PORT5_OMR_PS4_Msk (0x10UL) |
| |
| #define | PORT5_OMR_PS5_Pos (5UL) |
| |
| #define | PORT5_OMR_PS5_Msk (0x20UL) |
| |
| #define | PORT5_OMR_PS6_Pos (6UL) |
| |
| #define | PORT5_OMR_PS6_Msk (0x40UL) |
| |
| #define | PORT5_OMR_PS7_Pos (7UL) |
| |
| #define | PORT5_OMR_PS7_Msk (0x80UL) |
| |
| #define | PORT5_OMR_PS8_Pos (8UL) |
| |
| #define | PORT5_OMR_PS8_Msk (0x100UL) |
| |
| #define | PORT5_OMR_PS9_Pos (9UL) |
| |
| #define | PORT5_OMR_PS9_Msk (0x200UL) |
| |
| #define | PORT5_OMR_PS10_Pos (10UL) |
| |
| #define | PORT5_OMR_PS10_Msk (0x400UL) |
| |
| #define | PORT5_OMR_PS11_Pos (11UL) |
| |
| #define | PORT5_OMR_PS11_Msk (0x800UL) |
| |
| #define | PORT5_OMR_PS12_Pos (12UL) |
| |
| #define | PORT5_OMR_PS12_Msk (0x1000UL) |
| |
| #define | PORT5_OMR_PS13_Pos (13UL) |
| |
| #define | PORT5_OMR_PS13_Msk (0x2000UL) |
| |
| #define | PORT5_OMR_PS14_Pos (14UL) |
| |
| #define | PORT5_OMR_PS14_Msk (0x4000UL) |
| |
| #define | PORT5_OMR_PS15_Pos (15UL) |
| |
| #define | PORT5_OMR_PS15_Msk (0x8000UL) |
| |
| #define | PORT5_OMR_PR0_Pos (16UL) |
| |
| #define | PORT5_OMR_PR0_Msk (0x10000UL) |
| |
| #define | PORT5_OMR_PR1_Pos (17UL) |
| |
| #define | PORT5_OMR_PR1_Msk (0x20000UL) |
| |
| #define | PORT5_OMR_PR2_Pos (18UL) |
| |
| #define | PORT5_OMR_PR2_Msk (0x40000UL) |
| |
| #define | PORT5_OMR_PR3_Pos (19UL) |
| |
| #define | PORT5_OMR_PR3_Msk (0x80000UL) |
| |
| #define | PORT5_OMR_PR4_Pos (20UL) |
| |
| #define | PORT5_OMR_PR4_Msk (0x100000UL) |
| |
| #define | PORT5_OMR_PR5_Pos (21UL) |
| |
| #define | PORT5_OMR_PR5_Msk (0x200000UL) |
| |
| #define | PORT5_OMR_PR6_Pos (22UL) |
| |
| #define | PORT5_OMR_PR6_Msk (0x400000UL) |
| |
| #define | PORT5_OMR_PR7_Pos (23UL) |
| |
| #define | PORT5_OMR_PR7_Msk (0x800000UL) |
| |
| #define | PORT5_OMR_PR8_Pos (24UL) |
| |
| #define | PORT5_OMR_PR8_Msk (0x1000000UL) |
| |
| #define | PORT5_OMR_PR9_Pos (25UL) |
| |
| #define | PORT5_OMR_PR9_Msk (0x2000000UL) |
| |
| #define | PORT5_OMR_PR10_Pos (26UL) |
| |
| #define | PORT5_OMR_PR10_Msk (0x4000000UL) |
| |
| #define | PORT5_OMR_PR11_Pos (27UL) |
| |
| #define | PORT5_OMR_PR11_Msk (0x8000000UL) |
| |
| #define | PORT5_OMR_PR12_Pos (28UL) |
| |
| #define | PORT5_OMR_PR12_Msk (0x10000000UL) |
| |
| #define | PORT5_OMR_PR13_Pos (29UL) |
| |
| #define | PORT5_OMR_PR13_Msk (0x20000000UL) |
| |
| #define | PORT5_OMR_PR14_Pos (30UL) |
| |
| #define | PORT5_OMR_PR14_Msk (0x40000000UL) |
| |
| #define | PORT5_OMR_PR15_Pos (31UL) |
| |
| #define | PORT5_OMR_PR15_Msk (0x80000000UL) |
| |
| #define | PORT5_IOCR0_PC0_Pos (3UL) |
| |
| #define | PORT5_IOCR0_PC0_Msk (0xf8UL) |
| |
| #define | PORT5_IOCR0_PC1_Pos (11UL) |
| |
| #define | PORT5_IOCR0_PC1_Msk (0xf800UL) |
| |
| #define | PORT5_IOCR0_PC2_Pos (19UL) |
| |
| #define | PORT5_IOCR0_PC2_Msk (0xf80000UL) |
| |
| #define | PORT5_IOCR0_PC3_Pos (27UL) |
| |
| #define | PORT5_IOCR0_PC3_Msk (0xf8000000UL) |
| |
| #define | PORT5_IOCR4_PC4_Pos (3UL) |
| |
| #define | PORT5_IOCR4_PC4_Msk (0xf8UL) |
| |
| #define | PORT5_IOCR4_PC5_Pos (11UL) |
| |
| #define | PORT5_IOCR4_PC5_Msk (0xf800UL) |
| |
| #define | PORT5_IOCR4_PC6_Pos (19UL) |
| |
| #define | PORT5_IOCR4_PC6_Msk (0xf80000UL) |
| |
| #define | PORT5_IOCR4_PC7_Pos (27UL) |
| |
| #define | PORT5_IOCR4_PC7_Msk (0xf8000000UL) |
| |
| #define | PORT5_IOCR8_PC8_Pos (3UL) |
| |
| #define | PORT5_IOCR8_PC8_Msk (0xf8UL) |
| |
| #define | PORT5_IOCR8_PC9_Pos (11UL) |
| |
| #define | PORT5_IOCR8_PC9_Msk (0xf800UL) |
| |
| #define | PORT5_IOCR8_PC10_Pos (19UL) |
| |
| #define | PORT5_IOCR8_PC10_Msk (0xf80000UL) |
| |
| #define | PORT5_IOCR8_PC11_Pos (27UL) |
| |
| #define | PORT5_IOCR8_PC11_Msk (0xf8000000UL) |
| |
| #define | PORT5_IN_P0_Pos (0UL) |
| |
| #define | PORT5_IN_P0_Msk (0x1UL) |
| |
| #define | PORT5_IN_P1_Pos (1UL) |
| |
| #define | PORT5_IN_P1_Msk (0x2UL) |
| |
| #define | PORT5_IN_P2_Pos (2UL) |
| |
| #define | PORT5_IN_P2_Msk (0x4UL) |
| |
| #define | PORT5_IN_P3_Pos (3UL) |
| |
| #define | PORT5_IN_P3_Msk (0x8UL) |
| |
| #define | PORT5_IN_P4_Pos (4UL) |
| |
| #define | PORT5_IN_P4_Msk (0x10UL) |
| |
| #define | PORT5_IN_P5_Pos (5UL) |
| |
| #define | PORT5_IN_P5_Msk (0x20UL) |
| |
| #define | PORT5_IN_P6_Pos (6UL) |
| |
| #define | PORT5_IN_P6_Msk (0x40UL) |
| |
| #define | PORT5_IN_P7_Pos (7UL) |
| |
| #define | PORT5_IN_P7_Msk (0x80UL) |
| |
| #define | PORT5_IN_P8_Pos (8UL) |
| |
| #define | PORT5_IN_P8_Msk (0x100UL) |
| |
| #define | PORT5_IN_P9_Pos (9UL) |
| |
| #define | PORT5_IN_P9_Msk (0x200UL) |
| |
| #define | PORT5_IN_P10_Pos (10UL) |
| |
| #define | PORT5_IN_P10_Msk (0x400UL) |
| |
| #define | PORT5_IN_P11_Pos (11UL) |
| |
| #define | PORT5_IN_P11_Msk (0x800UL) |
| |
| #define | PORT5_IN_P12_Pos (12UL) |
| |
| #define | PORT5_IN_P12_Msk (0x1000UL) |
| |
| #define | PORT5_IN_P13_Pos (13UL) |
| |
| #define | PORT5_IN_P13_Msk (0x2000UL) |
| |
| #define | PORT5_IN_P14_Pos (14UL) |
| |
| #define | PORT5_IN_P14_Msk (0x4000UL) |
| |
| #define | PORT5_IN_P15_Pos (15UL) |
| |
| #define | PORT5_IN_P15_Msk (0x8000UL) |
| |
| #define | PORT5_PDR0_PD0_Pos (0UL) |
| |
| #define | PORT5_PDR0_PD0_Msk (0x7UL) |
| |
| #define | PORT5_PDR0_PD1_Pos (4UL) |
| |
| #define | PORT5_PDR0_PD1_Msk (0x70UL) |
| |
| #define | PORT5_PDR0_PD2_Pos (8UL) |
| |
| #define | PORT5_PDR0_PD2_Msk (0x700UL) |
| |
| #define | PORT5_PDR0_PD3_Pos (12UL) |
| |
| #define | PORT5_PDR0_PD3_Msk (0x7000UL) |
| |
| #define | PORT5_PDR0_PD4_Pos (16UL) |
| |
| #define | PORT5_PDR0_PD4_Msk (0x70000UL) |
| |
| #define | PORT5_PDR0_PD5_Pos (20UL) |
| |
| #define | PORT5_PDR0_PD5_Msk (0x700000UL) |
| |
| #define | PORT5_PDR0_PD6_Pos (24UL) |
| |
| #define | PORT5_PDR0_PD6_Msk (0x7000000UL) |
| |
| #define | PORT5_PDR0_PD7_Pos (28UL) |
| |
| #define | PORT5_PDR0_PD7_Msk (0x70000000UL) |
| |
| #define | PORT5_PDR1_PD8_Pos (0UL) |
| |
| #define | PORT5_PDR1_PD8_Msk (0x7UL) |
| |
| #define | PORT5_PDR1_PD9_Pos (4UL) |
| |
| #define | PORT5_PDR1_PD9_Msk (0x70UL) |
| |
| #define | PORT5_PDR1_PD10_Pos (8UL) |
| |
| #define | PORT5_PDR1_PD10_Msk (0x700UL) |
| |
| #define | PORT5_PDR1_PD11_Pos (12UL) |
| |
| #define | PORT5_PDR1_PD11_Msk (0x7000UL) |
| |
| #define | PORT5_PDR1_PD12_Pos (16UL) |
| |
| #define | PORT5_PDR1_PD12_Msk (0x70000UL) |
| |
| #define | PORT5_PDR1_PD13_Pos (20UL) |
| |
| #define | PORT5_PDR1_PD13_Msk (0x700000UL) |
| |
| #define | PORT5_PDR1_PD14_Pos (24UL) |
| |
| #define | PORT5_PDR1_PD14_Msk (0x7000000UL) |
| |
| #define | PORT5_PDR1_PD15_Pos (28UL) |
| |
| #define | PORT5_PDR1_PD15_Msk (0x70000000UL) |
| |
| #define | PORT5_PDISC_PDIS0_Pos (0UL) |
| |
| #define | PORT5_PDISC_PDIS0_Msk (0x1UL) |
| |
| #define | PORT5_PDISC_PDIS1_Pos (1UL) |
| |
| #define | PORT5_PDISC_PDIS1_Msk (0x2UL) |
| |
| #define | PORT5_PDISC_PDIS2_Pos (2UL) |
| |
| #define | PORT5_PDISC_PDIS2_Msk (0x4UL) |
| |
| #define | PORT5_PDISC_PDIS3_Pos (3UL) |
| |
| #define | PORT5_PDISC_PDIS3_Msk (0x8UL) |
| |
| #define | PORT5_PDISC_PDIS4_Pos (4UL) |
| |
| #define | PORT5_PDISC_PDIS4_Msk (0x10UL) |
| |
| #define | PORT5_PDISC_PDIS5_Pos (5UL) |
| |
| #define | PORT5_PDISC_PDIS5_Msk (0x20UL) |
| |
| #define | PORT5_PDISC_PDIS6_Pos (6UL) |
| |
| #define | PORT5_PDISC_PDIS6_Msk (0x40UL) |
| |
| #define | PORT5_PDISC_PDIS7_Pos (7UL) |
| |
| #define | PORT5_PDISC_PDIS7_Msk (0x80UL) |
| |
| #define | PORT5_PDISC_PDIS8_Pos (8UL) |
| |
| #define | PORT5_PDISC_PDIS8_Msk (0x100UL) |
| |
| #define | PORT5_PDISC_PDIS9_Pos (9UL) |
| |
| #define | PORT5_PDISC_PDIS9_Msk (0x200UL) |
| |
| #define | PORT5_PDISC_PDIS10_Pos (10UL) |
| |
| #define | PORT5_PDISC_PDIS10_Msk (0x400UL) |
| |
| #define | PORT5_PDISC_PDIS11_Pos (11UL) |
| |
| #define | PORT5_PDISC_PDIS11_Msk (0x800UL) |
| |
| #define | PORT5_PDISC_PDIS12_Pos (12UL) |
| |
| #define | PORT5_PDISC_PDIS12_Msk (0x1000UL) |
| |
| #define | PORT5_PDISC_PDIS13_Pos (13UL) |
| |
| #define | PORT5_PDISC_PDIS13_Msk (0x2000UL) |
| |
| #define | PORT5_PDISC_PDIS14_Pos (14UL) |
| |
| #define | PORT5_PDISC_PDIS14_Msk (0x4000UL) |
| |
| #define | PORT5_PDISC_PDIS15_Pos (15UL) |
| |
| #define | PORT5_PDISC_PDIS15_Msk (0x8000UL) |
| |
| #define | PORT5_PPS_PPS0_Pos (0UL) |
| |
| #define | PORT5_PPS_PPS0_Msk (0x1UL) |
| |
| #define | PORT5_PPS_PPS1_Pos (1UL) |
| |
| #define | PORT5_PPS_PPS1_Msk (0x2UL) |
| |
| #define | PORT5_PPS_PPS2_Pos (2UL) |
| |
| #define | PORT5_PPS_PPS2_Msk (0x4UL) |
| |
| #define | PORT5_PPS_PPS3_Pos (3UL) |
| |
| #define | PORT5_PPS_PPS3_Msk (0x8UL) |
| |
| #define | PORT5_PPS_PPS4_Pos (4UL) |
| |
| #define | PORT5_PPS_PPS4_Msk (0x10UL) |
| |
| #define | PORT5_PPS_PPS5_Pos (5UL) |
| |
| #define | PORT5_PPS_PPS5_Msk (0x20UL) |
| |
| #define | PORT5_PPS_PPS6_Pos (6UL) |
| |
| #define | PORT5_PPS_PPS6_Msk (0x40UL) |
| |
| #define | PORT5_PPS_PPS7_Pos (7UL) |
| |
| #define | PORT5_PPS_PPS7_Msk (0x80UL) |
| |
| #define | PORT5_PPS_PPS8_Pos (8UL) |
| |
| #define | PORT5_PPS_PPS8_Msk (0x100UL) |
| |
| #define | PORT5_PPS_PPS9_Pos (9UL) |
| |
| #define | PORT5_PPS_PPS9_Msk (0x200UL) |
| |
| #define | PORT5_PPS_PPS10_Pos (10UL) |
| |
| #define | PORT5_PPS_PPS10_Msk (0x400UL) |
| |
| #define | PORT5_PPS_PPS11_Pos (11UL) |
| |
| #define | PORT5_PPS_PPS11_Msk (0x800UL) |
| |
| #define | PORT5_PPS_PPS12_Pos (12UL) |
| |
| #define | PORT5_PPS_PPS12_Msk (0x1000UL) |
| |
| #define | PORT5_PPS_PPS13_Pos (13UL) |
| |
| #define | PORT5_PPS_PPS13_Msk (0x2000UL) |
| |
| #define | PORT5_PPS_PPS14_Pos (14UL) |
| |
| #define | PORT5_PPS_PPS14_Msk (0x4000UL) |
| |
| #define | PORT5_PPS_PPS15_Pos (15UL) |
| |
| #define | PORT5_PPS_PPS15_Msk (0x8000UL) |
| |
| #define | PORT5_HWSEL_HW0_Pos (0UL) |
| |
| #define | PORT5_HWSEL_HW0_Msk (0x3UL) |
| |
| #define | PORT5_HWSEL_HW1_Pos (2UL) |
| |
| #define | PORT5_HWSEL_HW1_Msk (0xcUL) |
| |
| #define | PORT5_HWSEL_HW2_Pos (4UL) |
| |
| #define | PORT5_HWSEL_HW2_Msk (0x30UL) |
| |
| #define | PORT5_HWSEL_HW3_Pos (6UL) |
| |
| #define | PORT5_HWSEL_HW3_Msk (0xc0UL) |
| |
| #define | PORT5_HWSEL_HW4_Pos (8UL) |
| |
| #define | PORT5_HWSEL_HW4_Msk (0x300UL) |
| |
| #define | PORT5_HWSEL_HW5_Pos (10UL) |
| |
| #define | PORT5_HWSEL_HW5_Msk (0xc00UL) |
| |
| #define | PORT5_HWSEL_HW6_Pos (12UL) |
| |
| #define | PORT5_HWSEL_HW6_Msk (0x3000UL) |
| |
| #define | PORT5_HWSEL_HW7_Pos (14UL) |
| |
| #define | PORT5_HWSEL_HW7_Msk (0xc000UL) |
| |
| #define | PORT5_HWSEL_HW8_Pos (16UL) |
| |
| #define | PORT5_HWSEL_HW8_Msk (0x30000UL) |
| |
| #define | PORT5_HWSEL_HW9_Pos (18UL) |
| |
| #define | PORT5_HWSEL_HW9_Msk (0xc0000UL) |
| |
| #define | PORT5_HWSEL_HW10_Pos (20UL) |
| |
| #define | PORT5_HWSEL_HW10_Msk (0x300000UL) |
| |
| #define | PORT5_HWSEL_HW11_Pos (22UL) |
| |
| #define | PORT5_HWSEL_HW11_Msk (0xc00000UL) |
| |
| #define | PORT5_HWSEL_HW12_Pos (24UL) |
| |
| #define | PORT5_HWSEL_HW12_Msk (0x3000000UL) |
| |
| #define | PORT5_HWSEL_HW13_Pos (26UL) |
| |
| #define | PORT5_HWSEL_HW13_Msk (0xc000000UL) |
| |
| #define | PORT5_HWSEL_HW14_Pos (28UL) |
| |
| #define | PORT5_HWSEL_HW14_Msk (0x30000000UL) |
| |
| #define | PORT5_HWSEL_HW15_Pos (30UL) |
| |
| #define | PORT5_HWSEL_HW15_Msk (0xc0000000UL) |
| |
| #define | PORT6_OUT_P0_Pos (0UL) |
| |
| #define | PORT6_OUT_P0_Msk (0x1UL) |
| |
| #define | PORT6_OUT_P1_Pos (1UL) |
| |
| #define | PORT6_OUT_P1_Msk (0x2UL) |
| |
| #define | PORT6_OUT_P2_Pos (2UL) |
| |
| #define | PORT6_OUT_P2_Msk (0x4UL) |
| |
| #define | PORT6_OUT_P3_Pos (3UL) |
| |
| #define | PORT6_OUT_P3_Msk (0x8UL) |
| |
| #define | PORT6_OUT_P4_Pos (4UL) |
| |
| #define | PORT6_OUT_P4_Msk (0x10UL) |
| |
| #define | PORT6_OUT_P5_Pos (5UL) |
| |
| #define | PORT6_OUT_P5_Msk (0x20UL) |
| |
| #define | PORT6_OUT_P6_Pos (6UL) |
| |
| #define | PORT6_OUT_P6_Msk (0x40UL) |
| |
| #define | PORT6_OUT_P7_Pos (7UL) |
| |
| #define | PORT6_OUT_P7_Msk (0x80UL) |
| |
| #define | PORT6_OUT_P8_Pos (8UL) |
| |
| #define | PORT6_OUT_P8_Msk (0x100UL) |
| |
| #define | PORT6_OUT_P9_Pos (9UL) |
| |
| #define | PORT6_OUT_P9_Msk (0x200UL) |
| |
| #define | PORT6_OUT_P10_Pos (10UL) |
| |
| #define | PORT6_OUT_P10_Msk (0x400UL) |
| |
| #define | PORT6_OUT_P11_Pos (11UL) |
| |
| #define | PORT6_OUT_P11_Msk (0x800UL) |
| |
| #define | PORT6_OUT_P12_Pos (12UL) |
| |
| #define | PORT6_OUT_P12_Msk (0x1000UL) |
| |
| #define | PORT6_OUT_P13_Pos (13UL) |
| |
| #define | PORT6_OUT_P13_Msk (0x2000UL) |
| |
| #define | PORT6_OUT_P14_Pos (14UL) |
| |
| #define | PORT6_OUT_P14_Msk (0x4000UL) |
| |
| #define | PORT6_OUT_P15_Pos (15UL) |
| |
| #define | PORT6_OUT_P15_Msk (0x8000UL) |
| |
| #define | PORT6_OMR_PS0_Pos (0UL) |
| |
| #define | PORT6_OMR_PS0_Msk (0x1UL) |
| |
| #define | PORT6_OMR_PS1_Pos (1UL) |
| |
| #define | PORT6_OMR_PS1_Msk (0x2UL) |
| |
| #define | PORT6_OMR_PS2_Pos (2UL) |
| |
| #define | PORT6_OMR_PS2_Msk (0x4UL) |
| |
| #define | PORT6_OMR_PS3_Pos (3UL) |
| |
| #define | PORT6_OMR_PS3_Msk (0x8UL) |
| |
| #define | PORT6_OMR_PS4_Pos (4UL) |
| |
| #define | PORT6_OMR_PS4_Msk (0x10UL) |
| |
| #define | PORT6_OMR_PS5_Pos (5UL) |
| |
| #define | PORT6_OMR_PS5_Msk (0x20UL) |
| |
| #define | PORT6_OMR_PS6_Pos (6UL) |
| |
| #define | PORT6_OMR_PS6_Msk (0x40UL) |
| |
| #define | PORT6_OMR_PS7_Pos (7UL) |
| |
| #define | PORT6_OMR_PS7_Msk (0x80UL) |
| |
| #define | PORT6_OMR_PS8_Pos (8UL) |
| |
| #define | PORT6_OMR_PS8_Msk (0x100UL) |
| |
| #define | PORT6_OMR_PS9_Pos (9UL) |
| |
| #define | PORT6_OMR_PS9_Msk (0x200UL) |
| |
| #define | PORT6_OMR_PS10_Pos (10UL) |
| |
| #define | PORT6_OMR_PS10_Msk (0x400UL) |
| |
| #define | PORT6_OMR_PS11_Pos (11UL) |
| |
| #define | PORT6_OMR_PS11_Msk (0x800UL) |
| |
| #define | PORT6_OMR_PS12_Pos (12UL) |
| |
| #define | PORT6_OMR_PS12_Msk (0x1000UL) |
| |
| #define | PORT6_OMR_PS13_Pos (13UL) |
| |
| #define | PORT6_OMR_PS13_Msk (0x2000UL) |
| |
| #define | PORT6_OMR_PS14_Pos (14UL) |
| |
| #define | PORT6_OMR_PS14_Msk (0x4000UL) |
| |
| #define | PORT6_OMR_PS15_Pos (15UL) |
| |
| #define | PORT6_OMR_PS15_Msk (0x8000UL) |
| |
| #define | PORT6_OMR_PR0_Pos (16UL) |
| |
| #define | PORT6_OMR_PR0_Msk (0x10000UL) |
| |
| #define | PORT6_OMR_PR1_Pos (17UL) |
| |
| #define | PORT6_OMR_PR1_Msk (0x20000UL) |
| |
| #define | PORT6_OMR_PR2_Pos (18UL) |
| |
| #define | PORT6_OMR_PR2_Msk (0x40000UL) |
| |
| #define | PORT6_OMR_PR3_Pos (19UL) |
| |
| #define | PORT6_OMR_PR3_Msk (0x80000UL) |
| |
| #define | PORT6_OMR_PR4_Pos (20UL) |
| |
| #define | PORT6_OMR_PR4_Msk (0x100000UL) |
| |
| #define | PORT6_OMR_PR5_Pos (21UL) |
| |
| #define | PORT6_OMR_PR5_Msk (0x200000UL) |
| |
| #define | PORT6_OMR_PR6_Pos (22UL) |
| |
| #define | PORT6_OMR_PR6_Msk (0x400000UL) |
| |
| #define | PORT6_OMR_PR7_Pos (23UL) |
| |
| #define | PORT6_OMR_PR7_Msk (0x800000UL) |
| |
| #define | PORT6_OMR_PR8_Pos (24UL) |
| |
| #define | PORT6_OMR_PR8_Msk (0x1000000UL) |
| |
| #define | PORT6_OMR_PR9_Pos (25UL) |
| |
| #define | PORT6_OMR_PR9_Msk (0x2000000UL) |
| |
| #define | PORT6_OMR_PR10_Pos (26UL) |
| |
| #define | PORT6_OMR_PR10_Msk (0x4000000UL) |
| |
| #define | PORT6_OMR_PR11_Pos (27UL) |
| |
| #define | PORT6_OMR_PR11_Msk (0x8000000UL) |
| |
| #define | PORT6_OMR_PR12_Pos (28UL) |
| |
| #define | PORT6_OMR_PR12_Msk (0x10000000UL) |
| |
| #define | PORT6_OMR_PR13_Pos (29UL) |
| |
| #define | PORT6_OMR_PR13_Msk (0x20000000UL) |
| |
| #define | PORT6_OMR_PR14_Pos (30UL) |
| |
| #define | PORT6_OMR_PR14_Msk (0x40000000UL) |
| |
| #define | PORT6_OMR_PR15_Pos (31UL) |
| |
| #define | PORT6_OMR_PR15_Msk (0x80000000UL) |
| |
| #define | PORT6_IOCR0_PC0_Pos (3UL) |
| |
| #define | PORT6_IOCR0_PC0_Msk (0xf8UL) |
| |
| #define | PORT6_IOCR0_PC1_Pos (11UL) |
| |
| #define | PORT6_IOCR0_PC1_Msk (0xf800UL) |
| |
| #define | PORT6_IOCR0_PC2_Pos (19UL) |
| |
| #define | PORT6_IOCR0_PC2_Msk (0xf80000UL) |
| |
| #define | PORT6_IOCR0_PC3_Pos (27UL) |
| |
| #define | PORT6_IOCR0_PC3_Msk (0xf8000000UL) |
| |
| #define | PORT6_IOCR4_PC4_Pos (3UL) |
| |
| #define | PORT6_IOCR4_PC4_Msk (0xf8UL) |
| |
| #define | PORT6_IOCR4_PC5_Pos (11UL) |
| |
| #define | PORT6_IOCR4_PC5_Msk (0xf800UL) |
| |
| #define | PORT6_IOCR4_PC6_Pos (19UL) |
| |
| #define | PORT6_IOCR4_PC6_Msk (0xf80000UL) |
| |
| #define | PORT6_IOCR4_PC7_Pos (27UL) |
| |
| #define | PORT6_IOCR4_PC7_Msk (0xf8000000UL) |
| |
| #define | PORT6_IN_P0_Pos (0UL) |
| |
| #define | PORT6_IN_P0_Msk (0x1UL) |
| |
| #define | PORT6_IN_P1_Pos (1UL) |
| |
| #define | PORT6_IN_P1_Msk (0x2UL) |
| |
| #define | PORT6_IN_P2_Pos (2UL) |
| |
| #define | PORT6_IN_P2_Msk (0x4UL) |
| |
| #define | PORT6_IN_P3_Pos (3UL) |
| |
| #define | PORT6_IN_P3_Msk (0x8UL) |
| |
| #define | PORT6_IN_P4_Pos (4UL) |
| |
| #define | PORT6_IN_P4_Msk (0x10UL) |
| |
| #define | PORT6_IN_P5_Pos (5UL) |
| |
| #define | PORT6_IN_P5_Msk (0x20UL) |
| |
| #define | PORT6_IN_P6_Pos (6UL) |
| |
| #define | PORT6_IN_P6_Msk (0x40UL) |
| |
| #define | PORT6_IN_P7_Pos (7UL) |
| |
| #define | PORT6_IN_P7_Msk (0x80UL) |
| |
| #define | PORT6_IN_P8_Pos (8UL) |
| |
| #define | PORT6_IN_P8_Msk (0x100UL) |
| |
| #define | PORT6_IN_P9_Pos (9UL) |
| |
| #define | PORT6_IN_P9_Msk (0x200UL) |
| |
| #define | PORT6_IN_P10_Pos (10UL) |
| |
| #define | PORT6_IN_P10_Msk (0x400UL) |
| |
| #define | PORT6_IN_P11_Pos (11UL) |
| |
| #define | PORT6_IN_P11_Msk (0x800UL) |
| |
| #define | PORT6_IN_P12_Pos (12UL) |
| |
| #define | PORT6_IN_P12_Msk (0x1000UL) |
| |
| #define | PORT6_IN_P13_Pos (13UL) |
| |
| #define | PORT6_IN_P13_Msk (0x2000UL) |
| |
| #define | PORT6_IN_P14_Pos (14UL) |
| |
| #define | PORT6_IN_P14_Msk (0x4000UL) |
| |
| #define | PORT6_IN_P15_Pos (15UL) |
| |
| #define | PORT6_IN_P15_Msk (0x8000UL) |
| |
| #define | PORT6_PDR0_PD0_Pos (0UL) |
| |
| #define | PORT6_PDR0_PD0_Msk (0x7UL) |
| |
| #define | PORT6_PDR0_PD1_Pos (4UL) |
| |
| #define | PORT6_PDR0_PD1_Msk (0x70UL) |
| |
| #define | PORT6_PDR0_PD2_Pos (8UL) |
| |
| #define | PORT6_PDR0_PD2_Msk (0x700UL) |
| |
| #define | PORT6_PDR0_PD3_Pos (12UL) |
| |
| #define | PORT6_PDR0_PD3_Msk (0x7000UL) |
| |
| #define | PORT6_PDR0_PD4_Pos (16UL) |
| |
| #define | PORT6_PDR0_PD4_Msk (0x70000UL) |
| |
| #define | PORT6_PDR0_PD5_Pos (20UL) |
| |
| #define | PORT6_PDR0_PD5_Msk (0x700000UL) |
| |
| #define | PORT6_PDR0_PD6_Pos (24UL) |
| |
| #define | PORT6_PDR0_PD6_Msk (0x7000000UL) |
| |
| #define | PORT6_PDR0_PD7_Pos (28UL) |
| |
| #define | PORT6_PDR0_PD7_Msk (0x70000000UL) |
| |
| #define | PORT6_PDISC_PDIS0_Pos (0UL) |
| |
| #define | PORT6_PDISC_PDIS0_Msk (0x1UL) |
| |
| #define | PORT6_PDISC_PDIS1_Pos (1UL) |
| |
| #define | PORT6_PDISC_PDIS1_Msk (0x2UL) |
| |
| #define | PORT6_PDISC_PDIS2_Pos (2UL) |
| |
| #define | PORT6_PDISC_PDIS2_Msk (0x4UL) |
| |
| #define | PORT6_PDISC_PDIS3_Pos (3UL) |
| |
| #define | PORT6_PDISC_PDIS3_Msk (0x8UL) |
| |
| #define | PORT6_PDISC_PDIS4_Pos (4UL) |
| |
| #define | PORT6_PDISC_PDIS4_Msk (0x10UL) |
| |
| #define | PORT6_PDISC_PDIS5_Pos (5UL) |
| |
| #define | PORT6_PDISC_PDIS5_Msk (0x20UL) |
| |
| #define | PORT6_PDISC_PDIS6_Pos (6UL) |
| |
| #define | PORT6_PDISC_PDIS6_Msk (0x40UL) |
| |
| #define | PORT6_PDISC_PDIS7_Pos (7UL) |
| |
| #define | PORT6_PDISC_PDIS7_Msk (0x80UL) |
| |
| #define | PORT6_PDISC_PDIS8_Pos (8UL) |
| |
| #define | PORT6_PDISC_PDIS8_Msk (0x100UL) |
| |
| #define | PORT6_PDISC_PDIS9_Pos (9UL) |
| |
| #define | PORT6_PDISC_PDIS9_Msk (0x200UL) |
| |
| #define | PORT6_PDISC_PDIS10_Pos (10UL) |
| |
| #define | PORT6_PDISC_PDIS10_Msk (0x400UL) |
| |
| #define | PORT6_PDISC_PDIS11_Pos (11UL) |
| |
| #define | PORT6_PDISC_PDIS11_Msk (0x800UL) |
| |
| #define | PORT6_PDISC_PDIS12_Pos (12UL) |
| |
| #define | PORT6_PDISC_PDIS12_Msk (0x1000UL) |
| |
| #define | PORT6_PDISC_PDIS13_Pos (13UL) |
| |
| #define | PORT6_PDISC_PDIS13_Msk (0x2000UL) |
| |
| #define | PORT6_PDISC_PDIS14_Pos (14UL) |
| |
| #define | PORT6_PDISC_PDIS14_Msk (0x4000UL) |
| |
| #define | PORT6_PDISC_PDIS15_Pos (15UL) |
| |
| #define | PORT6_PDISC_PDIS15_Msk (0x8000UL) |
| |
| #define | PORT6_PPS_PPS0_Pos (0UL) |
| |
| #define | PORT6_PPS_PPS0_Msk (0x1UL) |
| |
| #define | PORT6_PPS_PPS1_Pos (1UL) |
| |
| #define | PORT6_PPS_PPS1_Msk (0x2UL) |
| |
| #define | PORT6_PPS_PPS2_Pos (2UL) |
| |
| #define | PORT6_PPS_PPS2_Msk (0x4UL) |
| |
| #define | PORT6_PPS_PPS3_Pos (3UL) |
| |
| #define | PORT6_PPS_PPS3_Msk (0x8UL) |
| |
| #define | PORT6_PPS_PPS4_Pos (4UL) |
| |
| #define | PORT6_PPS_PPS4_Msk (0x10UL) |
| |
| #define | PORT6_PPS_PPS5_Pos (5UL) |
| |
| #define | PORT6_PPS_PPS5_Msk (0x20UL) |
| |
| #define | PORT6_PPS_PPS6_Pos (6UL) |
| |
| #define | PORT6_PPS_PPS6_Msk (0x40UL) |
| |
| #define | PORT6_PPS_PPS7_Pos (7UL) |
| |
| #define | PORT6_PPS_PPS7_Msk (0x80UL) |
| |
| #define | PORT6_PPS_PPS8_Pos (8UL) |
| |
| #define | PORT6_PPS_PPS8_Msk (0x100UL) |
| |
| #define | PORT6_PPS_PPS9_Pos (9UL) |
| |
| #define | PORT6_PPS_PPS9_Msk (0x200UL) |
| |
| #define | PORT6_PPS_PPS10_Pos (10UL) |
| |
| #define | PORT6_PPS_PPS10_Msk (0x400UL) |
| |
| #define | PORT6_PPS_PPS11_Pos (11UL) |
| |
| #define | PORT6_PPS_PPS11_Msk (0x800UL) |
| |
| #define | PORT6_PPS_PPS12_Pos (12UL) |
| |
| #define | PORT6_PPS_PPS12_Msk (0x1000UL) |
| |
| #define | PORT6_PPS_PPS13_Pos (13UL) |
| |
| #define | PORT6_PPS_PPS13_Msk (0x2000UL) |
| |
| #define | PORT6_PPS_PPS14_Pos (14UL) |
| |
| #define | PORT6_PPS_PPS14_Msk (0x4000UL) |
| |
| #define | PORT6_PPS_PPS15_Pos (15UL) |
| |
| #define | PORT6_PPS_PPS15_Msk (0x8000UL) |
| |
| #define | PORT6_HWSEL_HW0_Pos (0UL) |
| |
| #define | PORT6_HWSEL_HW0_Msk (0x3UL) |
| |
| #define | PORT6_HWSEL_HW1_Pos (2UL) |
| |
| #define | PORT6_HWSEL_HW1_Msk (0xcUL) |
| |
| #define | PORT6_HWSEL_HW2_Pos (4UL) |
| |
| #define | PORT6_HWSEL_HW2_Msk (0x30UL) |
| |
| #define | PORT6_HWSEL_HW3_Pos (6UL) |
| |
| #define | PORT6_HWSEL_HW3_Msk (0xc0UL) |
| |
| #define | PORT6_HWSEL_HW4_Pos (8UL) |
| |
| #define | PORT6_HWSEL_HW4_Msk (0x300UL) |
| |
| #define | PORT6_HWSEL_HW5_Pos (10UL) |
| |
| #define | PORT6_HWSEL_HW5_Msk (0xc00UL) |
| |
| #define | PORT6_HWSEL_HW6_Pos (12UL) |
| |
| #define | PORT6_HWSEL_HW6_Msk (0x3000UL) |
| |
| #define | PORT6_HWSEL_HW7_Pos (14UL) |
| |
| #define | PORT6_HWSEL_HW7_Msk (0xc000UL) |
| |
| #define | PORT6_HWSEL_HW8_Pos (16UL) |
| |
| #define | PORT6_HWSEL_HW8_Msk (0x30000UL) |
| |
| #define | PORT6_HWSEL_HW9_Pos (18UL) |
| |
| #define | PORT6_HWSEL_HW9_Msk (0xc0000UL) |
| |
| #define | PORT6_HWSEL_HW10_Pos (20UL) |
| |
| #define | PORT6_HWSEL_HW10_Msk (0x300000UL) |
| |
| #define | PORT6_HWSEL_HW11_Pos (22UL) |
| |
| #define | PORT6_HWSEL_HW11_Msk (0xc00000UL) |
| |
| #define | PORT6_HWSEL_HW12_Pos (24UL) |
| |
| #define | PORT6_HWSEL_HW12_Msk (0x3000000UL) |
| |
| #define | PORT6_HWSEL_HW13_Pos (26UL) |
| |
| #define | PORT6_HWSEL_HW13_Msk (0xc000000UL) |
| |
| #define | PORT6_HWSEL_HW14_Pos (28UL) |
| |
| #define | PORT6_HWSEL_HW14_Msk (0x30000000UL) |
| |
| #define | PORT6_HWSEL_HW15_Pos (30UL) |
| |
| #define | PORT6_HWSEL_HW15_Msk (0xc0000000UL) |
| |
| #define | PORT7_OUT_P0_Pos (0UL) |
| |
| #define | PORT7_OUT_P0_Msk (0x1UL) |
| |
| #define | PORT7_OUT_P1_Pos (1UL) |
| |
| #define | PORT7_OUT_P1_Msk (0x2UL) |
| |
| #define | PORT7_OUT_P2_Pos (2UL) |
| |
| #define | PORT7_OUT_P2_Msk (0x4UL) |
| |
| #define | PORT7_OUT_P3_Pos (3UL) |
| |
| #define | PORT7_OUT_P3_Msk (0x8UL) |
| |
| #define | PORT7_OUT_P4_Pos (4UL) |
| |
| #define | PORT7_OUT_P4_Msk (0x10UL) |
| |
| #define | PORT7_OUT_P5_Pos (5UL) |
| |
| #define | PORT7_OUT_P5_Msk (0x20UL) |
| |
| #define | PORT7_OUT_P6_Pos (6UL) |
| |
| #define | PORT7_OUT_P6_Msk (0x40UL) |
| |
| #define | PORT7_OUT_P7_Pos (7UL) |
| |
| #define | PORT7_OUT_P7_Msk (0x80UL) |
| |
| #define | PORT7_OUT_P8_Pos (8UL) |
| |
| #define | PORT7_OUT_P8_Msk (0x100UL) |
| |
| #define | PORT7_OUT_P9_Pos (9UL) |
| |
| #define | PORT7_OUT_P9_Msk (0x200UL) |
| |
| #define | PORT7_OUT_P10_Pos (10UL) |
| |
| #define | PORT7_OUT_P10_Msk (0x400UL) |
| |
| #define | PORT7_OUT_P11_Pos (11UL) |
| |
| #define | PORT7_OUT_P11_Msk (0x800UL) |
| |
| #define | PORT7_OUT_P12_Pos (12UL) |
| |
| #define | PORT7_OUT_P12_Msk (0x1000UL) |
| |
| #define | PORT7_OUT_P13_Pos (13UL) |
| |
| #define | PORT7_OUT_P13_Msk (0x2000UL) |
| |
| #define | PORT7_OUT_P14_Pos (14UL) |
| |
| #define | PORT7_OUT_P14_Msk (0x4000UL) |
| |
| #define | PORT7_OUT_P15_Pos (15UL) |
| |
| #define | PORT7_OUT_P15_Msk (0x8000UL) |
| |
| #define | PORT7_OMR_PS0_Pos (0UL) |
| |
| #define | PORT7_OMR_PS0_Msk (0x1UL) |
| |
| #define | PORT7_OMR_PS1_Pos (1UL) |
| |
| #define | PORT7_OMR_PS1_Msk (0x2UL) |
| |
| #define | PORT7_OMR_PS2_Pos (2UL) |
| |
| #define | PORT7_OMR_PS2_Msk (0x4UL) |
| |
| #define | PORT7_OMR_PS3_Pos (3UL) |
| |
| #define | PORT7_OMR_PS3_Msk (0x8UL) |
| |
| #define | PORT7_OMR_PS4_Pos (4UL) |
| |
| #define | PORT7_OMR_PS4_Msk (0x10UL) |
| |
| #define | PORT7_OMR_PS5_Pos (5UL) |
| |
| #define | PORT7_OMR_PS5_Msk (0x20UL) |
| |
| #define | PORT7_OMR_PS6_Pos (6UL) |
| |
| #define | PORT7_OMR_PS6_Msk (0x40UL) |
| |
| #define | PORT7_OMR_PS7_Pos (7UL) |
| |
| #define | PORT7_OMR_PS7_Msk (0x80UL) |
| |
| #define | PORT7_OMR_PS8_Pos (8UL) |
| |
| #define | PORT7_OMR_PS8_Msk (0x100UL) |
| |
| #define | PORT7_OMR_PS9_Pos (9UL) |
| |
| #define | PORT7_OMR_PS9_Msk (0x200UL) |
| |
| #define | PORT7_OMR_PS10_Pos (10UL) |
| |
| #define | PORT7_OMR_PS10_Msk (0x400UL) |
| |
| #define | PORT7_OMR_PS11_Pos (11UL) |
| |
| #define | PORT7_OMR_PS11_Msk (0x800UL) |
| |
| #define | PORT7_OMR_PS12_Pos (12UL) |
| |
| #define | PORT7_OMR_PS12_Msk (0x1000UL) |
| |
| #define | PORT7_OMR_PS13_Pos (13UL) |
| |
| #define | PORT7_OMR_PS13_Msk (0x2000UL) |
| |
| #define | PORT7_OMR_PS14_Pos (14UL) |
| |
| #define | PORT7_OMR_PS14_Msk (0x4000UL) |
| |
| #define | PORT7_OMR_PS15_Pos (15UL) |
| |
| #define | PORT7_OMR_PS15_Msk (0x8000UL) |
| |
| #define | PORT7_OMR_PR0_Pos (16UL) |
| |
| #define | PORT7_OMR_PR0_Msk (0x10000UL) |
| |
| #define | PORT7_OMR_PR1_Pos (17UL) |
| |
| #define | PORT7_OMR_PR1_Msk (0x20000UL) |
| |
| #define | PORT7_OMR_PR2_Pos (18UL) |
| |
| #define | PORT7_OMR_PR2_Msk (0x40000UL) |
| |
| #define | PORT7_OMR_PR3_Pos (19UL) |
| |
| #define | PORT7_OMR_PR3_Msk (0x80000UL) |
| |
| #define | PORT7_OMR_PR4_Pos (20UL) |
| |
| #define | PORT7_OMR_PR4_Msk (0x100000UL) |
| |
| #define | PORT7_OMR_PR5_Pos (21UL) |
| |
| #define | PORT7_OMR_PR5_Msk (0x200000UL) |
| |
| #define | PORT7_OMR_PR6_Pos (22UL) |
| |
| #define | PORT7_OMR_PR6_Msk (0x400000UL) |
| |
| #define | PORT7_OMR_PR7_Pos (23UL) |
| |
| #define | PORT7_OMR_PR7_Msk (0x800000UL) |
| |
| #define | PORT7_OMR_PR8_Pos (24UL) |
| |
| #define | PORT7_OMR_PR8_Msk (0x1000000UL) |
| |
| #define | PORT7_OMR_PR9_Pos (25UL) |
| |
| #define | PORT7_OMR_PR9_Msk (0x2000000UL) |
| |
| #define | PORT7_OMR_PR10_Pos (26UL) |
| |
| #define | PORT7_OMR_PR10_Msk (0x4000000UL) |
| |
| #define | PORT7_OMR_PR11_Pos (27UL) |
| |
| #define | PORT7_OMR_PR11_Msk (0x8000000UL) |
| |
| #define | PORT7_OMR_PR12_Pos (28UL) |
| |
| #define | PORT7_OMR_PR12_Msk (0x10000000UL) |
| |
| #define | PORT7_OMR_PR13_Pos (29UL) |
| |
| #define | PORT7_OMR_PR13_Msk (0x20000000UL) |
| |
| #define | PORT7_OMR_PR14_Pos (30UL) |
| |
| #define | PORT7_OMR_PR14_Msk (0x40000000UL) |
| |
| #define | PORT7_OMR_PR15_Pos (31UL) |
| |
| #define | PORT7_OMR_PR15_Msk (0x80000000UL) |
| |
| #define | PORT7_IOCR0_PC0_Pos (3UL) |
| |
| #define | PORT7_IOCR0_PC0_Msk (0xf8UL) |
| |
| #define | PORT7_IOCR0_PC1_Pos (11UL) |
| |
| #define | PORT7_IOCR0_PC1_Msk (0xf800UL) |
| |
| #define | PORT7_IOCR0_PC2_Pos (19UL) |
| |
| #define | PORT7_IOCR0_PC2_Msk (0xf80000UL) |
| |
| #define | PORT7_IOCR0_PC3_Pos (27UL) |
| |
| #define | PORT7_IOCR0_PC3_Msk (0xf8000000UL) |
| |
| #define | PORT7_IOCR4_PC4_Pos (3UL) |
| |
| #define | PORT7_IOCR4_PC4_Msk (0xf8UL) |
| |
| #define | PORT7_IOCR4_PC5_Pos (11UL) |
| |
| #define | PORT7_IOCR4_PC5_Msk (0xf800UL) |
| |
| #define | PORT7_IOCR4_PC6_Pos (19UL) |
| |
| #define | PORT7_IOCR4_PC6_Msk (0xf80000UL) |
| |
| #define | PORT7_IOCR4_PC7_Pos (27UL) |
| |
| #define | PORT7_IOCR4_PC7_Msk (0xf8000000UL) |
| |
| #define | PORT7_IOCR8_PC8_Pos (3UL) |
| |
| #define | PORT7_IOCR8_PC8_Msk (0xf8UL) |
| |
| #define | PORT7_IOCR8_PC9_Pos (11UL) |
| |
| #define | PORT7_IOCR8_PC9_Msk (0xf800UL) |
| |
| #define | PORT7_IOCR8_PC10_Pos (19UL) |
| |
| #define | PORT7_IOCR8_PC10_Msk (0xf80000UL) |
| |
| #define | PORT7_IOCR8_PC11_Pos (27UL) |
| |
| #define | PORT7_IOCR8_PC11_Msk (0xf8000000UL) |
| |
| #define | PORT7_IN_P0_Pos (0UL) |
| |
| #define | PORT7_IN_P0_Msk (0x1UL) |
| |
| #define | PORT7_IN_P1_Pos (1UL) |
| |
| #define | PORT7_IN_P1_Msk (0x2UL) |
| |
| #define | PORT7_IN_P2_Pos (2UL) |
| |
| #define | PORT7_IN_P2_Msk (0x4UL) |
| |
| #define | PORT7_IN_P3_Pos (3UL) |
| |
| #define | PORT7_IN_P3_Msk (0x8UL) |
| |
| #define | PORT7_IN_P4_Pos (4UL) |
| |
| #define | PORT7_IN_P4_Msk (0x10UL) |
| |
| #define | PORT7_IN_P5_Pos (5UL) |
| |
| #define | PORT7_IN_P5_Msk (0x20UL) |
| |
| #define | PORT7_IN_P6_Pos (6UL) |
| |
| #define | PORT7_IN_P6_Msk (0x40UL) |
| |
| #define | PORT7_IN_P7_Pos (7UL) |
| |
| #define | PORT7_IN_P7_Msk (0x80UL) |
| |
| #define | PORT7_IN_P8_Pos (8UL) |
| |
| #define | PORT7_IN_P8_Msk (0x100UL) |
| |
| #define | PORT7_IN_P9_Pos (9UL) |
| |
| #define | PORT7_IN_P9_Msk (0x200UL) |
| |
| #define | PORT7_IN_P10_Pos (10UL) |
| |
| #define | PORT7_IN_P10_Msk (0x400UL) |
| |
| #define | PORT7_IN_P11_Pos (11UL) |
| |
| #define | PORT7_IN_P11_Msk (0x800UL) |
| |
| #define | PORT7_IN_P12_Pos (12UL) |
| |
| #define | PORT7_IN_P12_Msk (0x1000UL) |
| |
| #define | PORT7_IN_P13_Pos (13UL) |
| |
| #define | PORT7_IN_P13_Msk (0x2000UL) |
| |
| #define | PORT7_IN_P14_Pos (14UL) |
| |
| #define | PORT7_IN_P14_Msk (0x4000UL) |
| |
| #define | PORT7_IN_P15_Pos (15UL) |
| |
| #define | PORT7_IN_P15_Msk (0x8000UL) |
| |
| #define | PORT7_PDR0_PD0_Pos (0UL) |
| |
| #define | PORT7_PDR0_PD0_Msk (0x7UL) |
| |
| #define | PORT7_PDR0_PD1_Pos (4UL) |
| |
| #define | PORT7_PDR0_PD1_Msk (0x70UL) |
| |
| #define | PORT7_PDR0_PD2_Pos (8UL) |
| |
| #define | PORT7_PDR0_PD2_Msk (0x700UL) |
| |
| #define | PORT7_PDR0_PD3_Pos (12UL) |
| |
| #define | PORT7_PDR0_PD3_Msk (0x7000UL) |
| |
| #define | PORT7_PDR0_PD4_Pos (16UL) |
| |
| #define | PORT7_PDR0_PD4_Msk (0x70000UL) |
| |
| #define | PORT7_PDR0_PD5_Pos (20UL) |
| |
| #define | PORT7_PDR0_PD5_Msk (0x700000UL) |
| |
| #define | PORT7_PDR0_PD6_Pos (24UL) |
| |
| #define | PORT7_PDR0_PD6_Msk (0x7000000UL) |
| |
| #define | PORT7_PDR0_PD7_Pos (28UL) |
| |
| #define | PORT7_PDR0_PD7_Msk (0x70000000UL) |
| |
| #define | PORT7_PDR1_PD8_Pos (0UL) |
| |
| #define | PORT7_PDR1_PD8_Msk (0x7UL) |
| |
| #define | PORT7_PDR1_PD9_Pos (4UL) |
| |
| #define | PORT7_PDR1_PD9_Msk (0x70UL) |
| |
| #define | PORT7_PDR1_PD10_Pos (8UL) |
| |
| #define | PORT7_PDR1_PD10_Msk (0x700UL) |
| |
| #define | PORT7_PDR1_PD11_Pos (12UL) |
| |
| #define | PORT7_PDR1_PD11_Msk (0x7000UL) |
| |
| #define | PORT7_PDR1_PD12_Pos (16UL) |
| |
| #define | PORT7_PDR1_PD12_Msk (0x70000UL) |
| |
| #define | PORT7_PDR1_PD13_Pos (20UL) |
| |
| #define | PORT7_PDR1_PD13_Msk (0x700000UL) |
| |
| #define | PORT7_PDR1_PD14_Pos (24UL) |
| |
| #define | PORT7_PDR1_PD14_Msk (0x7000000UL) |
| |
| #define | PORT7_PDR1_PD15_Pos (28UL) |
| |
| #define | PORT7_PDR1_PD15_Msk (0x70000000UL) |
| |
| #define | PORT7_PDISC_PDIS0_Pos (0UL) |
| |
| #define | PORT7_PDISC_PDIS0_Msk (0x1UL) |
| |
| #define | PORT7_PDISC_PDIS1_Pos (1UL) |
| |
| #define | PORT7_PDISC_PDIS1_Msk (0x2UL) |
| |
| #define | PORT7_PDISC_PDIS2_Pos (2UL) |
| |
| #define | PORT7_PDISC_PDIS2_Msk (0x4UL) |
| |
| #define | PORT7_PDISC_PDIS3_Pos (3UL) |
| |
| #define | PORT7_PDISC_PDIS3_Msk (0x8UL) |
| |
| #define | PORT7_PDISC_PDIS4_Pos (4UL) |
| |
| #define | PORT7_PDISC_PDIS4_Msk (0x10UL) |
| |
| #define | PORT7_PDISC_PDIS5_Pos (5UL) |
| |
| #define | PORT7_PDISC_PDIS5_Msk (0x20UL) |
| |
| #define | PORT7_PDISC_PDIS6_Pos (6UL) |
| |
| #define | PORT7_PDISC_PDIS6_Msk (0x40UL) |
| |
| #define | PORT7_PDISC_PDIS7_Pos (7UL) |
| |
| #define | PORT7_PDISC_PDIS7_Msk (0x80UL) |
| |
| #define | PORT7_PDISC_PDIS8_Pos (8UL) |
| |
| #define | PORT7_PDISC_PDIS8_Msk (0x100UL) |
| |
| #define | PORT7_PDISC_PDIS9_Pos (9UL) |
| |
| #define | PORT7_PDISC_PDIS9_Msk (0x200UL) |
| |
| #define | PORT7_PDISC_PDIS10_Pos (10UL) |
| |
| #define | PORT7_PDISC_PDIS10_Msk (0x400UL) |
| |
| #define | PORT7_PDISC_PDIS11_Pos (11UL) |
| |
| #define | PORT7_PDISC_PDIS11_Msk (0x800UL) |
| |
| #define | PORT7_PDISC_PDIS12_Pos (12UL) |
| |
| #define | PORT7_PDISC_PDIS12_Msk (0x1000UL) |
| |
| #define | PORT7_PDISC_PDIS13_Pos (13UL) |
| |
| #define | PORT7_PDISC_PDIS13_Msk (0x2000UL) |
| |
| #define | PORT7_PDISC_PDIS14_Pos (14UL) |
| |
| #define | PORT7_PDISC_PDIS14_Msk (0x4000UL) |
| |
| #define | PORT7_PDISC_PDIS15_Pos (15UL) |
| |
| #define | PORT7_PDISC_PDIS15_Msk (0x8000UL) |
| |
| #define | PORT7_PPS_PPS0_Pos (0UL) |
| |
| #define | PORT7_PPS_PPS0_Msk (0x1UL) |
| |
| #define | PORT7_PPS_PPS1_Pos (1UL) |
| |
| #define | PORT7_PPS_PPS1_Msk (0x2UL) |
| |
| #define | PORT7_PPS_PPS2_Pos (2UL) |
| |
| #define | PORT7_PPS_PPS2_Msk (0x4UL) |
| |
| #define | PORT7_PPS_PPS3_Pos (3UL) |
| |
| #define | PORT7_PPS_PPS3_Msk (0x8UL) |
| |
| #define | PORT7_PPS_PPS4_Pos (4UL) |
| |
| #define | PORT7_PPS_PPS4_Msk (0x10UL) |
| |
| #define | PORT7_PPS_PPS5_Pos (5UL) |
| |
| #define | PORT7_PPS_PPS5_Msk (0x20UL) |
| |
| #define | PORT7_PPS_PPS6_Pos (6UL) |
| |
| #define | PORT7_PPS_PPS6_Msk (0x40UL) |
| |
| #define | PORT7_PPS_PPS7_Pos (7UL) |
| |
| #define | PORT7_PPS_PPS7_Msk (0x80UL) |
| |
| #define | PORT7_PPS_PPS8_Pos (8UL) |
| |
| #define | PORT7_PPS_PPS8_Msk (0x100UL) |
| |
| #define | PORT7_PPS_PPS9_Pos (9UL) |
| |
| #define | PORT7_PPS_PPS9_Msk (0x200UL) |
| |
| #define | PORT7_PPS_PPS10_Pos (10UL) |
| |
| #define | PORT7_PPS_PPS10_Msk (0x400UL) |
| |
| #define | PORT7_PPS_PPS11_Pos (11UL) |
| |
| #define | PORT7_PPS_PPS11_Msk (0x800UL) |
| |
| #define | PORT7_PPS_PPS12_Pos (12UL) |
| |
| #define | PORT7_PPS_PPS12_Msk (0x1000UL) |
| |
| #define | PORT7_PPS_PPS13_Pos (13UL) |
| |
| #define | PORT7_PPS_PPS13_Msk (0x2000UL) |
| |
| #define | PORT7_PPS_PPS14_Pos (14UL) |
| |
| #define | PORT7_PPS_PPS14_Msk (0x4000UL) |
| |
| #define | PORT7_PPS_PPS15_Pos (15UL) |
| |
| #define | PORT7_PPS_PPS15_Msk (0x8000UL) |
| |
| #define | PORT7_HWSEL_HW0_Pos (0UL) |
| |
| #define | PORT7_HWSEL_HW0_Msk (0x3UL) |
| |
| #define | PORT7_HWSEL_HW1_Pos (2UL) |
| |
| #define | PORT7_HWSEL_HW1_Msk (0xcUL) |
| |
| #define | PORT7_HWSEL_HW2_Pos (4UL) |
| |
| #define | PORT7_HWSEL_HW2_Msk (0x30UL) |
| |
| #define | PORT7_HWSEL_HW3_Pos (6UL) |
| |
| #define | PORT7_HWSEL_HW3_Msk (0xc0UL) |
| |
| #define | PORT7_HWSEL_HW4_Pos (8UL) |
| |
| #define | PORT7_HWSEL_HW4_Msk (0x300UL) |
| |
| #define | PORT7_HWSEL_HW5_Pos (10UL) |
| |
| #define | PORT7_HWSEL_HW5_Msk (0xc00UL) |
| |
| #define | PORT7_HWSEL_HW6_Pos (12UL) |
| |
| #define | PORT7_HWSEL_HW6_Msk (0x3000UL) |
| |
| #define | PORT7_HWSEL_HW7_Pos (14UL) |
| |
| #define | PORT7_HWSEL_HW7_Msk (0xc000UL) |
| |
| #define | PORT7_HWSEL_HW8_Pos (16UL) |
| |
| #define | PORT7_HWSEL_HW8_Msk (0x30000UL) |
| |
| #define | PORT7_HWSEL_HW9_Pos (18UL) |
| |
| #define | PORT7_HWSEL_HW9_Msk (0xc0000UL) |
| |
| #define | PORT7_HWSEL_HW10_Pos (20UL) |
| |
| #define | PORT7_HWSEL_HW10_Msk (0x300000UL) |
| |
| #define | PORT7_HWSEL_HW11_Pos (22UL) |
| |
| #define | PORT7_HWSEL_HW11_Msk (0xc00000UL) |
| |
| #define | PORT7_HWSEL_HW12_Pos (24UL) |
| |
| #define | PORT7_HWSEL_HW12_Msk (0x3000000UL) |
| |
| #define | PORT7_HWSEL_HW13_Pos (26UL) |
| |
| #define | PORT7_HWSEL_HW13_Msk (0xc000000UL) |
| |
| #define | PORT7_HWSEL_HW14_Pos (28UL) |
| |
| #define | PORT7_HWSEL_HW14_Msk (0x30000000UL) |
| |
| #define | PORT7_HWSEL_HW15_Pos (30UL) |
| |
| #define | PORT7_HWSEL_HW15_Msk (0xc0000000UL) |
| |
| #define | PORT8_OUT_P0_Pos (0UL) |
| |
| #define | PORT8_OUT_P0_Msk (0x1UL) |
| |
| #define | PORT8_OUT_P1_Pos (1UL) |
| |
| #define | PORT8_OUT_P1_Msk (0x2UL) |
| |
| #define | PORT8_OUT_P2_Pos (2UL) |
| |
| #define | PORT8_OUT_P2_Msk (0x4UL) |
| |
| #define | PORT8_OUT_P3_Pos (3UL) |
| |
| #define | PORT8_OUT_P3_Msk (0x8UL) |
| |
| #define | PORT8_OUT_P4_Pos (4UL) |
| |
| #define | PORT8_OUT_P4_Msk (0x10UL) |
| |
| #define | PORT8_OUT_P5_Pos (5UL) |
| |
| #define | PORT8_OUT_P5_Msk (0x20UL) |
| |
| #define | PORT8_OUT_P6_Pos (6UL) |
| |
| #define | PORT8_OUT_P6_Msk (0x40UL) |
| |
| #define | PORT8_OUT_P7_Pos (7UL) |
| |
| #define | PORT8_OUT_P7_Msk (0x80UL) |
| |
| #define | PORT8_OUT_P8_Pos (8UL) |
| |
| #define | PORT8_OUT_P8_Msk (0x100UL) |
| |
| #define | PORT8_OUT_P9_Pos (9UL) |
| |
| #define | PORT8_OUT_P9_Msk (0x200UL) |
| |
| #define | PORT8_OUT_P10_Pos (10UL) |
| |
| #define | PORT8_OUT_P10_Msk (0x400UL) |
| |
| #define | PORT8_OUT_P11_Pos (11UL) |
| |
| #define | PORT8_OUT_P11_Msk (0x800UL) |
| |
| #define | PORT8_OUT_P12_Pos (12UL) |
| |
| #define | PORT8_OUT_P12_Msk (0x1000UL) |
| |
| #define | PORT8_OUT_P13_Pos (13UL) |
| |
| #define | PORT8_OUT_P13_Msk (0x2000UL) |
| |
| #define | PORT8_OUT_P14_Pos (14UL) |
| |
| #define | PORT8_OUT_P14_Msk (0x4000UL) |
| |
| #define | PORT8_OUT_P15_Pos (15UL) |
| |
| #define | PORT8_OUT_P15_Msk (0x8000UL) |
| |
| #define | PORT8_OMR_PS0_Pos (0UL) |
| |
| #define | PORT8_OMR_PS0_Msk (0x1UL) |
| |
| #define | PORT8_OMR_PS1_Pos (1UL) |
| |
| #define | PORT8_OMR_PS1_Msk (0x2UL) |
| |
| #define | PORT8_OMR_PS2_Pos (2UL) |
| |
| #define | PORT8_OMR_PS2_Msk (0x4UL) |
| |
| #define | PORT8_OMR_PS3_Pos (3UL) |
| |
| #define | PORT8_OMR_PS3_Msk (0x8UL) |
| |
| #define | PORT8_OMR_PS4_Pos (4UL) |
| |
| #define | PORT8_OMR_PS4_Msk (0x10UL) |
| |
| #define | PORT8_OMR_PS5_Pos (5UL) |
| |
| #define | PORT8_OMR_PS5_Msk (0x20UL) |
| |
| #define | PORT8_OMR_PS6_Pos (6UL) |
| |
| #define | PORT8_OMR_PS6_Msk (0x40UL) |
| |
| #define | PORT8_OMR_PS7_Pos (7UL) |
| |
| #define | PORT8_OMR_PS7_Msk (0x80UL) |
| |
| #define | PORT8_OMR_PS8_Pos (8UL) |
| |
| #define | PORT8_OMR_PS8_Msk (0x100UL) |
| |
| #define | PORT8_OMR_PS9_Pos (9UL) |
| |
| #define | PORT8_OMR_PS9_Msk (0x200UL) |
| |
| #define | PORT8_OMR_PS10_Pos (10UL) |
| |
| #define | PORT8_OMR_PS10_Msk (0x400UL) |
| |
| #define | PORT8_OMR_PS11_Pos (11UL) |
| |
| #define | PORT8_OMR_PS11_Msk (0x800UL) |
| |
| #define | PORT8_OMR_PS12_Pos (12UL) |
| |
| #define | PORT8_OMR_PS12_Msk (0x1000UL) |
| |
| #define | PORT8_OMR_PS13_Pos (13UL) |
| |
| #define | PORT8_OMR_PS13_Msk (0x2000UL) |
| |
| #define | PORT8_OMR_PS14_Pos (14UL) |
| |
| #define | PORT8_OMR_PS14_Msk (0x4000UL) |
| |
| #define | PORT8_OMR_PS15_Pos (15UL) |
| |
| #define | PORT8_OMR_PS15_Msk (0x8000UL) |
| |
| #define | PORT8_OMR_PR0_Pos (16UL) |
| |
| #define | PORT8_OMR_PR0_Msk (0x10000UL) |
| |
| #define | PORT8_OMR_PR1_Pos (17UL) |
| |
| #define | PORT8_OMR_PR1_Msk (0x20000UL) |
| |
| #define | PORT8_OMR_PR2_Pos (18UL) |
| |
| #define | PORT8_OMR_PR2_Msk (0x40000UL) |
| |
| #define | PORT8_OMR_PR3_Pos (19UL) |
| |
| #define | PORT8_OMR_PR3_Msk (0x80000UL) |
| |
| #define | PORT8_OMR_PR4_Pos (20UL) |
| |
| #define | PORT8_OMR_PR4_Msk (0x100000UL) |
| |
| #define | PORT8_OMR_PR5_Pos (21UL) |
| |
| #define | PORT8_OMR_PR5_Msk (0x200000UL) |
| |
| #define | PORT8_OMR_PR6_Pos (22UL) |
| |
| #define | PORT8_OMR_PR6_Msk (0x400000UL) |
| |
| #define | PORT8_OMR_PR7_Pos (23UL) |
| |
| #define | PORT8_OMR_PR7_Msk (0x800000UL) |
| |
| #define | PORT8_OMR_PR8_Pos (24UL) |
| |
| #define | PORT8_OMR_PR8_Msk (0x1000000UL) |
| |
| #define | PORT8_OMR_PR9_Pos (25UL) |
| |
| #define | PORT8_OMR_PR9_Msk (0x2000000UL) |
| |
| #define | PORT8_OMR_PR10_Pos (26UL) |
| |
| #define | PORT8_OMR_PR10_Msk (0x4000000UL) |
| |
| #define | PORT8_OMR_PR11_Pos (27UL) |
| |
| #define | PORT8_OMR_PR11_Msk (0x8000000UL) |
| |
| #define | PORT8_OMR_PR12_Pos (28UL) |
| |
| #define | PORT8_OMR_PR12_Msk (0x10000000UL) |
| |
| #define | PORT8_OMR_PR13_Pos (29UL) |
| |
| #define | PORT8_OMR_PR13_Msk (0x20000000UL) |
| |
| #define | PORT8_OMR_PR14_Pos (30UL) |
| |
| #define | PORT8_OMR_PR14_Msk (0x40000000UL) |
| |
| #define | PORT8_OMR_PR15_Pos (31UL) |
| |
| #define | PORT8_OMR_PR15_Msk (0x80000000UL) |
| |
| #define | PORT8_IOCR0_PC0_Pos (3UL) |
| |
| #define | PORT8_IOCR0_PC0_Msk (0xf8UL) |
| |
| #define | PORT8_IOCR0_PC1_Pos (11UL) |
| |
| #define | PORT8_IOCR0_PC1_Msk (0xf800UL) |
| |
| #define | PORT8_IOCR0_PC2_Pos (19UL) |
| |
| #define | PORT8_IOCR0_PC2_Msk (0xf80000UL) |
| |
| #define | PORT8_IOCR0_PC3_Pos (27UL) |
| |
| #define | PORT8_IOCR0_PC3_Msk (0xf8000000UL) |
| |
| #define | PORT8_IOCR4_PC4_Pos (3UL) |
| |
| #define | PORT8_IOCR4_PC4_Msk (0xf8UL) |
| |
| #define | PORT8_IOCR4_PC5_Pos (11UL) |
| |
| #define | PORT8_IOCR4_PC5_Msk (0xf800UL) |
| |
| #define | PORT8_IOCR4_PC6_Pos (19UL) |
| |
| #define | PORT8_IOCR4_PC6_Msk (0xf80000UL) |
| |
| #define | PORT8_IOCR4_PC7_Pos (27UL) |
| |
| #define | PORT8_IOCR4_PC7_Msk (0xf8000000UL) |
| |
| #define | PORT8_IOCR8_PC8_Pos (3UL) |
| |
| #define | PORT8_IOCR8_PC8_Msk (0xf8UL) |
| |
| #define | PORT8_IOCR8_PC9_Pos (11UL) |
| |
| #define | PORT8_IOCR8_PC9_Msk (0xf800UL) |
| |
| #define | PORT8_IOCR8_PC10_Pos (19UL) |
| |
| #define | PORT8_IOCR8_PC10_Msk (0xf80000UL) |
| |
| #define | PORT8_IOCR8_PC11_Pos (27UL) |
| |
| #define | PORT8_IOCR8_PC11_Msk (0xf8000000UL) |
| |
| #define | PORT8_IN_P0_Pos (0UL) |
| |
| #define | PORT8_IN_P0_Msk (0x1UL) |
| |
| #define | PORT8_IN_P1_Pos (1UL) |
| |
| #define | PORT8_IN_P1_Msk (0x2UL) |
| |
| #define | PORT8_IN_P2_Pos (2UL) |
| |
| #define | PORT8_IN_P2_Msk (0x4UL) |
| |
| #define | PORT8_IN_P3_Pos (3UL) |
| |
| #define | PORT8_IN_P3_Msk (0x8UL) |
| |
| #define | PORT8_IN_P4_Pos (4UL) |
| |
| #define | PORT8_IN_P4_Msk (0x10UL) |
| |
| #define | PORT8_IN_P5_Pos (5UL) |
| |
| #define | PORT8_IN_P5_Msk (0x20UL) |
| |
| #define | PORT8_IN_P6_Pos (6UL) |
| |
| #define | PORT8_IN_P6_Msk (0x40UL) |
| |
| #define | PORT8_IN_P7_Pos (7UL) |
| |
| #define | PORT8_IN_P7_Msk (0x80UL) |
| |
| #define | PORT8_IN_P8_Pos (8UL) |
| |
| #define | PORT8_IN_P8_Msk (0x100UL) |
| |
| #define | PORT8_IN_P9_Pos (9UL) |
| |
| #define | PORT8_IN_P9_Msk (0x200UL) |
| |
| #define | PORT8_IN_P10_Pos (10UL) |
| |
| #define | PORT8_IN_P10_Msk (0x400UL) |
| |
| #define | PORT8_IN_P11_Pos (11UL) |
| |
| #define | PORT8_IN_P11_Msk (0x800UL) |
| |
| #define | PORT8_IN_P12_Pos (12UL) |
| |
| #define | PORT8_IN_P12_Msk (0x1000UL) |
| |
| #define | PORT8_IN_P13_Pos (13UL) |
| |
| #define | PORT8_IN_P13_Msk (0x2000UL) |
| |
| #define | PORT8_IN_P14_Pos (14UL) |
| |
| #define | PORT8_IN_P14_Msk (0x4000UL) |
| |
| #define | PORT8_IN_P15_Pos (15UL) |
| |
| #define | PORT8_IN_P15_Msk (0x8000UL) |
| |
| #define | PORT8_PDR0_PD0_Pos (0UL) |
| |
| #define | PORT8_PDR0_PD0_Msk (0x7UL) |
| |
| #define | PORT8_PDR0_PD1_Pos (4UL) |
| |
| #define | PORT8_PDR0_PD1_Msk (0x70UL) |
| |
| #define | PORT8_PDR0_PD2_Pos (8UL) |
| |
| #define | PORT8_PDR0_PD2_Msk (0x700UL) |
| |
| #define | PORT8_PDR0_PD3_Pos (12UL) |
| |
| #define | PORT8_PDR0_PD3_Msk (0x7000UL) |
| |
| #define | PORT8_PDR0_PD4_Pos (16UL) |
| |
| #define | PORT8_PDR0_PD4_Msk (0x70000UL) |
| |
| #define | PORT8_PDR0_PD5_Pos (20UL) |
| |
| #define | PORT8_PDR0_PD5_Msk (0x700000UL) |
| |
| #define | PORT8_PDR0_PD6_Pos (24UL) |
| |
| #define | PORT8_PDR0_PD6_Msk (0x7000000UL) |
| |
| #define | PORT8_PDR0_PD7_Pos (28UL) |
| |
| #define | PORT8_PDR0_PD7_Msk (0x70000000UL) |
| |
| #define | PORT8_PDR1_PD8_Pos (0UL) |
| |
| #define | PORT8_PDR1_PD8_Msk (0x7UL) |
| |
| #define | PORT8_PDR1_PD9_Pos (4UL) |
| |
| #define | PORT8_PDR1_PD9_Msk (0x70UL) |
| |
| #define | PORT8_PDR1_PD10_Pos (8UL) |
| |
| #define | PORT8_PDR1_PD10_Msk (0x700UL) |
| |
| #define | PORT8_PDR1_PD11_Pos (12UL) |
| |
| #define | PORT8_PDR1_PD11_Msk (0x7000UL) |
| |
| #define | PORT8_PDR1_PD12_Pos (16UL) |
| |
| #define | PORT8_PDR1_PD12_Msk (0x70000UL) |
| |
| #define | PORT8_PDR1_PD13_Pos (20UL) |
| |
| #define | PORT8_PDR1_PD13_Msk (0x700000UL) |
| |
| #define | PORT8_PDR1_PD14_Pos (24UL) |
| |
| #define | PORT8_PDR1_PD14_Msk (0x7000000UL) |
| |
| #define | PORT8_PDR1_PD15_Pos (28UL) |
| |
| #define | PORT8_PDR1_PD15_Msk (0x70000000UL) |
| |
| #define | PORT8_PDISC_PDIS0_Pos (0UL) |
| |
| #define | PORT8_PDISC_PDIS0_Msk (0x1UL) |
| |
| #define | PORT8_PDISC_PDIS1_Pos (1UL) |
| |
| #define | PORT8_PDISC_PDIS1_Msk (0x2UL) |
| |
| #define | PORT8_PDISC_PDIS2_Pos (2UL) |
| |
| #define | PORT8_PDISC_PDIS2_Msk (0x4UL) |
| |
| #define | PORT8_PDISC_PDIS3_Pos (3UL) |
| |
| #define | PORT8_PDISC_PDIS3_Msk (0x8UL) |
| |
| #define | PORT8_PDISC_PDIS4_Pos (4UL) |
| |
| #define | PORT8_PDISC_PDIS4_Msk (0x10UL) |
| |
| #define | PORT8_PDISC_PDIS5_Pos (5UL) |
| |
| #define | PORT8_PDISC_PDIS5_Msk (0x20UL) |
| |
| #define | PORT8_PDISC_PDIS6_Pos (6UL) |
| |
| #define | PORT8_PDISC_PDIS6_Msk (0x40UL) |
| |
| #define | PORT8_PDISC_PDIS7_Pos (7UL) |
| |
| #define | PORT8_PDISC_PDIS7_Msk (0x80UL) |
| |
| #define | PORT8_PDISC_PDIS8_Pos (8UL) |
| |
| #define | PORT8_PDISC_PDIS8_Msk (0x100UL) |
| |
| #define | PORT8_PDISC_PDIS9_Pos (9UL) |
| |
| #define | PORT8_PDISC_PDIS9_Msk (0x200UL) |
| |
| #define | PORT8_PDISC_PDIS10_Pos (10UL) |
| |
| #define | PORT8_PDISC_PDIS10_Msk (0x400UL) |
| |
| #define | PORT8_PDISC_PDIS11_Pos (11UL) |
| |
| #define | PORT8_PDISC_PDIS11_Msk (0x800UL) |
| |
| #define | PORT8_PDISC_PDIS12_Pos (12UL) |
| |
| #define | PORT8_PDISC_PDIS12_Msk (0x1000UL) |
| |
| #define | PORT8_PDISC_PDIS13_Pos (13UL) |
| |
| #define | PORT8_PDISC_PDIS13_Msk (0x2000UL) |
| |
| #define | PORT8_PDISC_PDIS14_Pos (14UL) |
| |
| #define | PORT8_PDISC_PDIS14_Msk (0x4000UL) |
| |
| #define | PORT8_PDISC_PDIS15_Pos (15UL) |
| |
| #define | PORT8_PDISC_PDIS15_Msk (0x8000UL) |
| |
| #define | PORT8_PPS_PPS0_Pos (0UL) |
| |
| #define | PORT8_PPS_PPS0_Msk (0x1UL) |
| |
| #define | PORT8_PPS_PPS1_Pos (1UL) |
| |
| #define | PORT8_PPS_PPS1_Msk (0x2UL) |
| |
| #define | PORT8_PPS_PPS2_Pos (2UL) |
| |
| #define | PORT8_PPS_PPS2_Msk (0x4UL) |
| |
| #define | PORT8_PPS_PPS3_Pos (3UL) |
| |
| #define | PORT8_PPS_PPS3_Msk (0x8UL) |
| |
| #define | PORT8_PPS_PPS4_Pos (4UL) |
| |
| #define | PORT8_PPS_PPS4_Msk (0x10UL) |
| |
| #define | PORT8_PPS_PPS5_Pos (5UL) |
| |
| #define | PORT8_PPS_PPS5_Msk (0x20UL) |
| |
| #define | PORT8_PPS_PPS6_Pos (6UL) |
| |
| #define | PORT8_PPS_PPS6_Msk (0x40UL) |
| |
| #define | PORT8_PPS_PPS7_Pos (7UL) |
| |
| #define | PORT8_PPS_PPS7_Msk (0x80UL) |
| |
| #define | PORT8_PPS_PPS8_Pos (8UL) |
| |
| #define | PORT8_PPS_PPS8_Msk (0x100UL) |
| |
| #define | PORT8_PPS_PPS9_Pos (9UL) |
| |
| #define | PORT8_PPS_PPS9_Msk (0x200UL) |
| |
| #define | PORT8_PPS_PPS10_Pos (10UL) |
| |
| #define | PORT8_PPS_PPS10_Msk (0x400UL) |
| |
| #define | PORT8_PPS_PPS11_Pos (11UL) |
| |
| #define | PORT8_PPS_PPS11_Msk (0x800UL) |
| |
| #define | PORT8_PPS_PPS12_Pos (12UL) |
| |
| #define | PORT8_PPS_PPS12_Msk (0x1000UL) |
| |
| #define | PORT8_PPS_PPS13_Pos (13UL) |
| |
| #define | PORT8_PPS_PPS13_Msk (0x2000UL) |
| |
| #define | PORT8_PPS_PPS14_Pos (14UL) |
| |
| #define | PORT8_PPS_PPS14_Msk (0x4000UL) |
| |
| #define | PORT8_PPS_PPS15_Pos (15UL) |
| |
| #define | PORT8_PPS_PPS15_Msk (0x8000UL) |
| |
| #define | PORT8_HWSEL_HW0_Pos (0UL) |
| |
| #define | PORT8_HWSEL_HW0_Msk (0x3UL) |
| |
| #define | PORT8_HWSEL_HW1_Pos (2UL) |
| |
| #define | PORT8_HWSEL_HW1_Msk (0xcUL) |
| |
| #define | PORT8_HWSEL_HW2_Pos (4UL) |
| |
| #define | PORT8_HWSEL_HW2_Msk (0x30UL) |
| |
| #define | PORT8_HWSEL_HW3_Pos (6UL) |
| |
| #define | PORT8_HWSEL_HW3_Msk (0xc0UL) |
| |
| #define | PORT8_HWSEL_HW4_Pos (8UL) |
| |
| #define | PORT8_HWSEL_HW4_Msk (0x300UL) |
| |
| #define | PORT8_HWSEL_HW5_Pos (10UL) |
| |
| #define | PORT8_HWSEL_HW5_Msk (0xc00UL) |
| |
| #define | PORT8_HWSEL_HW6_Pos (12UL) |
| |
| #define | PORT8_HWSEL_HW6_Msk (0x3000UL) |
| |
| #define | PORT8_HWSEL_HW7_Pos (14UL) |
| |
| #define | PORT8_HWSEL_HW7_Msk (0xc000UL) |
| |
| #define | PORT8_HWSEL_HW8_Pos (16UL) |
| |
| #define | PORT8_HWSEL_HW8_Msk (0x30000UL) |
| |
| #define | PORT8_HWSEL_HW9_Pos (18UL) |
| |
| #define | PORT8_HWSEL_HW9_Msk (0xc0000UL) |
| |
| #define | PORT8_HWSEL_HW10_Pos (20UL) |
| |
| #define | PORT8_HWSEL_HW10_Msk (0x300000UL) |
| |
| #define | PORT8_HWSEL_HW11_Pos (22UL) |
| |
| #define | PORT8_HWSEL_HW11_Msk (0xc00000UL) |
| |
| #define | PORT8_HWSEL_HW12_Pos (24UL) |
| |
| #define | PORT8_HWSEL_HW12_Msk (0x3000000UL) |
| |
| #define | PORT8_HWSEL_HW13_Pos (26UL) |
| |
| #define | PORT8_HWSEL_HW13_Msk (0xc000000UL) |
| |
| #define | PORT8_HWSEL_HW14_Pos (28UL) |
| |
| #define | PORT8_HWSEL_HW14_Msk (0x30000000UL) |
| |
| #define | PORT8_HWSEL_HW15_Pos (30UL) |
| |
| #define | PORT8_HWSEL_HW15_Msk (0xc0000000UL) |
| |
| #define | PORT9_OUT_P0_Pos (0UL) |
| |
| #define | PORT9_OUT_P0_Msk (0x1UL) |
| |
| #define | PORT9_OUT_P1_Pos (1UL) |
| |
| #define | PORT9_OUT_P1_Msk (0x2UL) |
| |
| #define | PORT9_OUT_P2_Pos (2UL) |
| |
| #define | PORT9_OUT_P2_Msk (0x4UL) |
| |
| #define | PORT9_OUT_P3_Pos (3UL) |
| |
| #define | PORT9_OUT_P3_Msk (0x8UL) |
| |
| #define | PORT9_OUT_P4_Pos (4UL) |
| |
| #define | PORT9_OUT_P4_Msk (0x10UL) |
| |
| #define | PORT9_OUT_P5_Pos (5UL) |
| |
| #define | PORT9_OUT_P5_Msk (0x20UL) |
| |
| #define | PORT9_OUT_P6_Pos (6UL) |
| |
| #define | PORT9_OUT_P6_Msk (0x40UL) |
| |
| #define | PORT9_OUT_P7_Pos (7UL) |
| |
| #define | PORT9_OUT_P7_Msk (0x80UL) |
| |
| #define | PORT9_OUT_P8_Pos (8UL) |
| |
| #define | PORT9_OUT_P8_Msk (0x100UL) |
| |
| #define | PORT9_OUT_P9_Pos (9UL) |
| |
| #define | PORT9_OUT_P9_Msk (0x200UL) |
| |
| #define | PORT9_OUT_P10_Pos (10UL) |
| |
| #define | PORT9_OUT_P10_Msk (0x400UL) |
| |
| #define | PORT9_OUT_P11_Pos (11UL) |
| |
| #define | PORT9_OUT_P11_Msk (0x800UL) |
| |
| #define | PORT9_OUT_P12_Pos (12UL) |
| |
| #define | PORT9_OUT_P12_Msk (0x1000UL) |
| |
| #define | PORT9_OUT_P13_Pos (13UL) |
| |
| #define | PORT9_OUT_P13_Msk (0x2000UL) |
| |
| #define | PORT9_OUT_P14_Pos (14UL) |
| |
| #define | PORT9_OUT_P14_Msk (0x4000UL) |
| |
| #define | PORT9_OUT_P15_Pos (15UL) |
| |
| #define | PORT9_OUT_P15_Msk (0x8000UL) |
| |
| #define | PORT9_OMR_PS0_Pos (0UL) |
| |
| #define | PORT9_OMR_PS0_Msk (0x1UL) |
| |
| #define | PORT9_OMR_PS1_Pos (1UL) |
| |
| #define | PORT9_OMR_PS1_Msk (0x2UL) |
| |
| #define | PORT9_OMR_PS2_Pos (2UL) |
| |
| #define | PORT9_OMR_PS2_Msk (0x4UL) |
| |
| #define | PORT9_OMR_PS3_Pos (3UL) |
| |
| #define | PORT9_OMR_PS3_Msk (0x8UL) |
| |
| #define | PORT9_OMR_PS4_Pos (4UL) |
| |
| #define | PORT9_OMR_PS4_Msk (0x10UL) |
| |
| #define | PORT9_OMR_PS5_Pos (5UL) |
| |
| #define | PORT9_OMR_PS5_Msk (0x20UL) |
| |
| #define | PORT9_OMR_PS6_Pos (6UL) |
| |
| #define | PORT9_OMR_PS6_Msk (0x40UL) |
| |
| #define | PORT9_OMR_PS7_Pos (7UL) |
| |
| #define | PORT9_OMR_PS7_Msk (0x80UL) |
| |
| #define | PORT9_OMR_PS8_Pos (8UL) |
| |
| #define | PORT9_OMR_PS8_Msk (0x100UL) |
| |
| #define | PORT9_OMR_PS9_Pos (9UL) |
| |
| #define | PORT9_OMR_PS9_Msk (0x200UL) |
| |
| #define | PORT9_OMR_PS10_Pos (10UL) |
| |
| #define | PORT9_OMR_PS10_Msk (0x400UL) |
| |
| #define | PORT9_OMR_PS11_Pos (11UL) |
| |
| #define | PORT9_OMR_PS11_Msk (0x800UL) |
| |
| #define | PORT9_OMR_PS12_Pos (12UL) |
| |
| #define | PORT9_OMR_PS12_Msk (0x1000UL) |
| |
| #define | PORT9_OMR_PS13_Pos (13UL) |
| |
| #define | PORT9_OMR_PS13_Msk (0x2000UL) |
| |
| #define | PORT9_OMR_PS14_Pos (14UL) |
| |
| #define | PORT9_OMR_PS14_Msk (0x4000UL) |
| |
| #define | PORT9_OMR_PS15_Pos (15UL) |
| |
| #define | PORT9_OMR_PS15_Msk (0x8000UL) |
| |
| #define | PORT9_OMR_PR0_Pos (16UL) |
| |
| #define | PORT9_OMR_PR0_Msk (0x10000UL) |
| |
| #define | PORT9_OMR_PR1_Pos (17UL) |
| |
| #define | PORT9_OMR_PR1_Msk (0x20000UL) |
| |
| #define | PORT9_OMR_PR2_Pos (18UL) |
| |
| #define | PORT9_OMR_PR2_Msk (0x40000UL) |
| |
| #define | PORT9_OMR_PR3_Pos (19UL) |
| |
| #define | PORT9_OMR_PR3_Msk (0x80000UL) |
| |
| #define | PORT9_OMR_PR4_Pos (20UL) |
| |
| #define | PORT9_OMR_PR4_Msk (0x100000UL) |
| |
| #define | PORT9_OMR_PR5_Pos (21UL) |
| |
| #define | PORT9_OMR_PR5_Msk (0x200000UL) |
| |
| #define | PORT9_OMR_PR6_Pos (22UL) |
| |
| #define | PORT9_OMR_PR6_Msk (0x400000UL) |
| |
| #define | PORT9_OMR_PR7_Pos (23UL) |
| |
| #define | PORT9_OMR_PR7_Msk (0x800000UL) |
| |
| #define | PORT9_OMR_PR8_Pos (24UL) |
| |
| #define | PORT9_OMR_PR8_Msk (0x1000000UL) |
| |
| #define | PORT9_OMR_PR9_Pos (25UL) |
| |
| #define | PORT9_OMR_PR9_Msk (0x2000000UL) |
| |
| #define | PORT9_OMR_PR10_Pos (26UL) |
| |
| #define | PORT9_OMR_PR10_Msk (0x4000000UL) |
| |
| #define | PORT9_OMR_PR11_Pos (27UL) |
| |
| #define | PORT9_OMR_PR11_Msk (0x8000000UL) |
| |
| #define | PORT9_OMR_PR12_Pos (28UL) |
| |
| #define | PORT9_OMR_PR12_Msk (0x10000000UL) |
| |
| #define | PORT9_OMR_PR13_Pos (29UL) |
| |
| #define | PORT9_OMR_PR13_Msk (0x20000000UL) |
| |
| #define | PORT9_OMR_PR14_Pos (30UL) |
| |
| #define | PORT9_OMR_PR14_Msk (0x40000000UL) |
| |
| #define | PORT9_OMR_PR15_Pos (31UL) |
| |
| #define | PORT9_OMR_PR15_Msk (0x80000000UL) |
| |
| #define | PORT9_IOCR0_PC0_Pos (3UL) |
| |
| #define | PORT9_IOCR0_PC0_Msk (0xf8UL) |
| |
| #define | PORT9_IOCR0_PC1_Pos (11UL) |
| |
| #define | PORT9_IOCR0_PC1_Msk (0xf800UL) |
| |
| #define | PORT9_IOCR0_PC2_Pos (19UL) |
| |
| #define | PORT9_IOCR0_PC2_Msk (0xf80000UL) |
| |
| #define | PORT9_IOCR0_PC3_Pos (27UL) |
| |
| #define | PORT9_IOCR0_PC3_Msk (0xf8000000UL) |
| |
| #define | PORT9_IOCR4_PC4_Pos (3UL) |
| |
| #define | PORT9_IOCR4_PC4_Msk (0xf8UL) |
| |
| #define | PORT9_IOCR4_PC5_Pos (11UL) |
| |
| #define | PORT9_IOCR4_PC5_Msk (0xf800UL) |
| |
| #define | PORT9_IOCR4_PC6_Pos (19UL) |
| |
| #define | PORT9_IOCR4_PC6_Msk (0xf80000UL) |
| |
| #define | PORT9_IOCR4_PC7_Pos (27UL) |
| |
| #define | PORT9_IOCR4_PC7_Msk (0xf8000000UL) |
| |
| #define | PORT9_IOCR8_PC8_Pos (3UL) |
| |
| #define | PORT9_IOCR8_PC8_Msk (0xf8UL) |
| |
| #define | PORT9_IOCR8_PC9_Pos (11UL) |
| |
| #define | PORT9_IOCR8_PC9_Msk (0xf800UL) |
| |
| #define | PORT9_IOCR8_PC10_Pos (19UL) |
| |
| #define | PORT9_IOCR8_PC10_Msk (0xf80000UL) |
| |
| #define | PORT9_IOCR8_PC11_Pos (27UL) |
| |
| #define | PORT9_IOCR8_PC11_Msk (0xf8000000UL) |
| |
| #define | PORT9_IN_P0_Pos (0UL) |
| |
| #define | PORT9_IN_P0_Msk (0x1UL) |
| |
| #define | PORT9_IN_P1_Pos (1UL) |
| |
| #define | PORT9_IN_P1_Msk (0x2UL) |
| |
| #define | PORT9_IN_P2_Pos (2UL) |
| |
| #define | PORT9_IN_P2_Msk (0x4UL) |
| |
| #define | PORT9_IN_P3_Pos (3UL) |
| |
| #define | PORT9_IN_P3_Msk (0x8UL) |
| |
| #define | PORT9_IN_P4_Pos (4UL) |
| |
| #define | PORT9_IN_P4_Msk (0x10UL) |
| |
| #define | PORT9_IN_P5_Pos (5UL) |
| |
| #define | PORT9_IN_P5_Msk (0x20UL) |
| |
| #define | PORT9_IN_P6_Pos (6UL) |
| |
| #define | PORT9_IN_P6_Msk (0x40UL) |
| |
| #define | PORT9_IN_P7_Pos (7UL) |
| |
| #define | PORT9_IN_P7_Msk (0x80UL) |
| |
| #define | PORT9_IN_P8_Pos (8UL) |
| |
| #define | PORT9_IN_P8_Msk (0x100UL) |
| |
| #define | PORT9_IN_P9_Pos (9UL) |
| |
| #define | PORT9_IN_P9_Msk (0x200UL) |
| |
| #define | PORT9_IN_P10_Pos (10UL) |
| |
| #define | PORT9_IN_P10_Msk (0x400UL) |
| |
| #define | PORT9_IN_P11_Pos (11UL) |
| |
| #define | PORT9_IN_P11_Msk (0x800UL) |
| |
| #define | PORT9_IN_P12_Pos (12UL) |
| |
| #define | PORT9_IN_P12_Msk (0x1000UL) |
| |
| #define | PORT9_IN_P13_Pos (13UL) |
| |
| #define | PORT9_IN_P13_Msk (0x2000UL) |
| |
| #define | PORT9_IN_P14_Pos (14UL) |
| |
| #define | PORT9_IN_P14_Msk (0x4000UL) |
| |
| #define | PORT9_IN_P15_Pos (15UL) |
| |
| #define | PORT9_IN_P15_Msk (0x8000UL) |
| |
| #define | PORT9_PDR0_PD0_Pos (0UL) |
| |
| #define | PORT9_PDR0_PD0_Msk (0x7UL) |
| |
| #define | PORT9_PDR0_PD1_Pos (4UL) |
| |
| #define | PORT9_PDR0_PD1_Msk (0x70UL) |
| |
| #define | PORT9_PDR0_PD2_Pos (8UL) |
| |
| #define | PORT9_PDR0_PD2_Msk (0x700UL) |
| |
| #define | PORT9_PDR0_PD3_Pos (12UL) |
| |
| #define | PORT9_PDR0_PD3_Msk (0x7000UL) |
| |
| #define | PORT9_PDR0_PD4_Pos (16UL) |
| |
| #define | PORT9_PDR0_PD4_Msk (0x70000UL) |
| |
| #define | PORT9_PDR0_PD5_Pos (20UL) |
| |
| #define | PORT9_PDR0_PD5_Msk (0x700000UL) |
| |
| #define | PORT9_PDR0_PD6_Pos (24UL) |
| |
| #define | PORT9_PDR0_PD6_Msk (0x7000000UL) |
| |
| #define | PORT9_PDR0_PD7_Pos (28UL) |
| |
| #define | PORT9_PDR0_PD7_Msk (0x70000000UL) |
| |
| #define | PORT9_PDR1_PD8_Pos (0UL) |
| |
| #define | PORT9_PDR1_PD8_Msk (0x7UL) |
| |
| #define | PORT9_PDR1_PD9_Pos (4UL) |
| |
| #define | PORT9_PDR1_PD9_Msk (0x70UL) |
| |
| #define | PORT9_PDR1_PD10_Pos (8UL) |
| |
| #define | PORT9_PDR1_PD10_Msk (0x700UL) |
| |
| #define | PORT9_PDR1_PD11_Pos (12UL) |
| |
| #define | PORT9_PDR1_PD11_Msk (0x7000UL) |
| |
| #define | PORT9_PDR1_PD12_Pos (16UL) |
| |
| #define | PORT9_PDR1_PD12_Msk (0x70000UL) |
| |
| #define | PORT9_PDR1_PD13_Pos (20UL) |
| |
| #define | PORT9_PDR1_PD13_Msk (0x700000UL) |
| |
| #define | PORT9_PDR1_PD14_Pos (24UL) |
| |
| #define | PORT9_PDR1_PD14_Msk (0x7000000UL) |
| |
| #define | PORT9_PDR1_PD15_Pos (28UL) |
| |
| #define | PORT9_PDR1_PD15_Msk (0x70000000UL) |
| |
| #define | PORT9_PDISC_PDIS0_Pos (0UL) |
| |
| #define | PORT9_PDISC_PDIS0_Msk (0x1UL) |
| |
| #define | PORT9_PDISC_PDIS1_Pos (1UL) |
| |
| #define | PORT9_PDISC_PDIS1_Msk (0x2UL) |
| |
| #define | PORT9_PDISC_PDIS2_Pos (2UL) |
| |
| #define | PORT9_PDISC_PDIS2_Msk (0x4UL) |
| |
| #define | PORT9_PDISC_PDIS3_Pos (3UL) |
| |
| #define | PORT9_PDISC_PDIS3_Msk (0x8UL) |
| |
| #define | PORT9_PDISC_PDIS4_Pos (4UL) |
| |
| #define | PORT9_PDISC_PDIS4_Msk (0x10UL) |
| |
| #define | PORT9_PDISC_PDIS5_Pos (5UL) |
| |
| #define | PORT9_PDISC_PDIS5_Msk (0x20UL) |
| |
| #define | PORT9_PDISC_PDIS6_Pos (6UL) |
| |
| #define | PORT9_PDISC_PDIS6_Msk (0x40UL) |
| |
| #define | PORT9_PDISC_PDIS7_Pos (7UL) |
| |
| #define | PORT9_PDISC_PDIS7_Msk (0x80UL) |
| |
| #define | PORT9_PDISC_PDIS8_Pos (8UL) |
| |
| #define | PORT9_PDISC_PDIS8_Msk (0x100UL) |
| |
| #define | PORT9_PDISC_PDIS9_Pos (9UL) |
| |
| #define | PORT9_PDISC_PDIS9_Msk (0x200UL) |
| |
| #define | PORT9_PDISC_PDIS10_Pos (10UL) |
| |
| #define | PORT9_PDISC_PDIS10_Msk (0x400UL) |
| |
| #define | PORT9_PDISC_PDIS11_Pos (11UL) |
| |
| #define | PORT9_PDISC_PDIS11_Msk (0x800UL) |
| |
| #define | PORT9_PDISC_PDIS12_Pos (12UL) |
| |
| #define | PORT9_PDISC_PDIS12_Msk (0x1000UL) |
| |
| #define | PORT9_PDISC_PDIS13_Pos (13UL) |
| |
| #define | PORT9_PDISC_PDIS13_Msk (0x2000UL) |
| |
| #define | PORT9_PDISC_PDIS14_Pos (14UL) |
| |
| #define | PORT9_PDISC_PDIS14_Msk (0x4000UL) |
| |
| #define | PORT9_PDISC_PDIS15_Pos (15UL) |
| |
| #define | PORT9_PDISC_PDIS15_Msk (0x8000UL) |
| |
| #define | PORT9_PPS_PPS0_Pos (0UL) |
| |
| #define | PORT9_PPS_PPS0_Msk (0x1UL) |
| |
| #define | PORT9_PPS_PPS1_Pos (1UL) |
| |
| #define | PORT9_PPS_PPS1_Msk (0x2UL) |
| |
| #define | PORT9_PPS_PPS2_Pos (2UL) |
| |
| #define | PORT9_PPS_PPS2_Msk (0x4UL) |
| |
| #define | PORT9_PPS_PPS3_Pos (3UL) |
| |
| #define | PORT9_PPS_PPS3_Msk (0x8UL) |
| |
| #define | PORT9_PPS_PPS4_Pos (4UL) |
| |
| #define | PORT9_PPS_PPS4_Msk (0x10UL) |
| |
| #define | PORT9_PPS_PPS5_Pos (5UL) |
| |
| #define | PORT9_PPS_PPS5_Msk (0x20UL) |
| |
| #define | PORT9_PPS_PPS6_Pos (6UL) |
| |
| #define | PORT9_PPS_PPS6_Msk (0x40UL) |
| |
| #define | PORT9_PPS_PPS7_Pos (7UL) |
| |
| #define | PORT9_PPS_PPS7_Msk (0x80UL) |
| |
| #define | PORT9_PPS_PPS8_Pos (8UL) |
| |
| #define | PORT9_PPS_PPS8_Msk (0x100UL) |
| |
| #define | PORT9_PPS_PPS9_Pos (9UL) |
| |
| #define | PORT9_PPS_PPS9_Msk (0x200UL) |
| |
| #define | PORT9_PPS_PPS10_Pos (10UL) |
| |
| #define | PORT9_PPS_PPS10_Msk (0x400UL) |
| |
| #define | PORT9_PPS_PPS11_Pos (11UL) |
| |
| #define | PORT9_PPS_PPS11_Msk (0x800UL) |
| |
| #define | PORT9_PPS_PPS12_Pos (12UL) |
| |
| #define | PORT9_PPS_PPS12_Msk (0x1000UL) |
| |
| #define | PORT9_PPS_PPS13_Pos (13UL) |
| |
| #define | PORT9_PPS_PPS13_Msk (0x2000UL) |
| |
| #define | PORT9_PPS_PPS14_Pos (14UL) |
| |
| #define | PORT9_PPS_PPS14_Msk (0x4000UL) |
| |
| #define | PORT9_PPS_PPS15_Pos (15UL) |
| |
| #define | PORT9_PPS_PPS15_Msk (0x8000UL) |
| |
| #define | PORT9_HWSEL_HW0_Pos (0UL) |
| |
| #define | PORT9_HWSEL_HW0_Msk (0x3UL) |
| |
| #define | PORT9_HWSEL_HW1_Pos (2UL) |
| |
| #define | PORT9_HWSEL_HW1_Msk (0xcUL) |
| |
| #define | PORT9_HWSEL_HW2_Pos (4UL) |
| |
| #define | PORT9_HWSEL_HW2_Msk (0x30UL) |
| |
| #define | PORT9_HWSEL_HW3_Pos (6UL) |
| |
| #define | PORT9_HWSEL_HW3_Msk (0xc0UL) |
| |
| #define | PORT9_HWSEL_HW4_Pos (8UL) |
| |
| #define | PORT9_HWSEL_HW4_Msk (0x300UL) |
| |
| #define | PORT9_HWSEL_HW5_Pos (10UL) |
| |
| #define | PORT9_HWSEL_HW5_Msk (0xc00UL) |
| |
| #define | PORT9_HWSEL_HW6_Pos (12UL) |
| |
| #define | PORT9_HWSEL_HW6_Msk (0x3000UL) |
| |
| #define | PORT9_HWSEL_HW7_Pos (14UL) |
| |
| #define | PORT9_HWSEL_HW7_Msk (0xc000UL) |
| |
| #define | PORT9_HWSEL_HW8_Pos (16UL) |
| |
| #define | PORT9_HWSEL_HW8_Msk (0x30000UL) |
| |
| #define | PORT9_HWSEL_HW9_Pos (18UL) |
| |
| #define | PORT9_HWSEL_HW9_Msk (0xc0000UL) |
| |
| #define | PORT9_HWSEL_HW10_Pos (20UL) |
| |
| #define | PORT9_HWSEL_HW10_Msk (0x300000UL) |
| |
| #define | PORT9_HWSEL_HW11_Pos (22UL) |
| |
| #define | PORT9_HWSEL_HW11_Msk (0xc00000UL) |
| |
| #define | PORT9_HWSEL_HW12_Pos (24UL) |
| |
| #define | PORT9_HWSEL_HW12_Msk (0x3000000UL) |
| |
| #define | PORT9_HWSEL_HW13_Pos (26UL) |
| |
| #define | PORT9_HWSEL_HW13_Msk (0xc000000UL) |
| |
| #define | PORT9_HWSEL_HW14_Pos (28UL) |
| |
| #define | PORT9_HWSEL_HW14_Msk (0x30000000UL) |
| |
| #define | PORT9_HWSEL_HW15_Pos (30UL) |
| |
| #define | PORT9_HWSEL_HW15_Msk (0xc0000000UL) |
| |
| #define | PORT14_OUT_P0_Pos (0UL) |
| |
| #define | PORT14_OUT_P0_Msk (0x1UL) |
| |
| #define | PORT14_OUT_P1_Pos (1UL) |
| |
| #define | PORT14_OUT_P1_Msk (0x2UL) |
| |
| #define | PORT14_OUT_P2_Pos (2UL) |
| |
| #define | PORT14_OUT_P2_Msk (0x4UL) |
| |
| #define | PORT14_OUT_P3_Pos (3UL) |
| |
| #define | PORT14_OUT_P3_Msk (0x8UL) |
| |
| #define | PORT14_OUT_P4_Pos (4UL) |
| |
| #define | PORT14_OUT_P4_Msk (0x10UL) |
| |
| #define | PORT14_OUT_P5_Pos (5UL) |
| |
| #define | PORT14_OUT_P5_Msk (0x20UL) |
| |
| #define | PORT14_OUT_P6_Pos (6UL) |
| |
| #define | PORT14_OUT_P6_Msk (0x40UL) |
| |
| #define | PORT14_OUT_P7_Pos (7UL) |
| |
| #define | PORT14_OUT_P7_Msk (0x80UL) |
| |
| #define | PORT14_OUT_P8_Pos (8UL) |
| |
| #define | PORT14_OUT_P8_Msk (0x100UL) |
| |
| #define | PORT14_OUT_P9_Pos (9UL) |
| |
| #define | PORT14_OUT_P9_Msk (0x200UL) |
| |
| #define | PORT14_OUT_P10_Pos (10UL) |
| |
| #define | PORT14_OUT_P10_Msk (0x400UL) |
| |
| #define | PORT14_OUT_P11_Pos (11UL) |
| |
| #define | PORT14_OUT_P11_Msk (0x800UL) |
| |
| #define | PORT14_OUT_P12_Pos (12UL) |
| |
| #define | PORT14_OUT_P12_Msk (0x1000UL) |
| |
| #define | PORT14_OUT_P13_Pos (13UL) |
| |
| #define | PORT14_OUT_P13_Msk (0x2000UL) |
| |
| #define | PORT14_OUT_P14_Pos (14UL) |
| |
| #define | PORT14_OUT_P14_Msk (0x4000UL) |
| |
| #define | PORT14_OUT_P15_Pos (15UL) |
| |
| #define | PORT14_OUT_P15_Msk (0x8000UL) |
| |
| #define | PORT14_OMR_PS0_Pos (0UL) |
| |
| #define | PORT14_OMR_PS0_Msk (0x1UL) |
| |
| #define | PORT14_OMR_PS1_Pos (1UL) |
| |
| #define | PORT14_OMR_PS1_Msk (0x2UL) |
| |
| #define | PORT14_OMR_PS2_Pos (2UL) |
| |
| #define | PORT14_OMR_PS2_Msk (0x4UL) |
| |
| #define | PORT14_OMR_PS3_Pos (3UL) |
| |
| #define | PORT14_OMR_PS3_Msk (0x8UL) |
| |
| #define | PORT14_OMR_PS4_Pos (4UL) |
| |
| #define | PORT14_OMR_PS4_Msk (0x10UL) |
| |
| #define | PORT14_OMR_PS5_Pos (5UL) |
| |
| #define | PORT14_OMR_PS5_Msk (0x20UL) |
| |
| #define | PORT14_OMR_PS6_Pos (6UL) |
| |
| #define | PORT14_OMR_PS6_Msk (0x40UL) |
| |
| #define | PORT14_OMR_PS7_Pos (7UL) |
| |
| #define | PORT14_OMR_PS7_Msk (0x80UL) |
| |
| #define | PORT14_OMR_PS8_Pos (8UL) |
| |
| #define | PORT14_OMR_PS8_Msk (0x100UL) |
| |
| #define | PORT14_OMR_PS9_Pos (9UL) |
| |
| #define | PORT14_OMR_PS9_Msk (0x200UL) |
| |
| #define | PORT14_OMR_PS10_Pos (10UL) |
| |
| #define | PORT14_OMR_PS10_Msk (0x400UL) |
| |
| #define | PORT14_OMR_PS11_Pos (11UL) |
| |
| #define | PORT14_OMR_PS11_Msk (0x800UL) |
| |
| #define | PORT14_OMR_PS12_Pos (12UL) |
| |
| #define | PORT14_OMR_PS12_Msk (0x1000UL) |
| |
| #define | PORT14_OMR_PS13_Pos (13UL) |
| |
| #define | PORT14_OMR_PS13_Msk (0x2000UL) |
| |
| #define | PORT14_OMR_PS14_Pos (14UL) |
| |
| #define | PORT14_OMR_PS14_Msk (0x4000UL) |
| |
| #define | PORT14_OMR_PS15_Pos (15UL) |
| |
| #define | PORT14_OMR_PS15_Msk (0x8000UL) |
| |
| #define | PORT14_OMR_PR0_Pos (16UL) |
| |
| #define | PORT14_OMR_PR0_Msk (0x10000UL) |
| |
| #define | PORT14_OMR_PR1_Pos (17UL) |
| |
| #define | PORT14_OMR_PR1_Msk (0x20000UL) |
| |
| #define | PORT14_OMR_PR2_Pos (18UL) |
| |
| #define | PORT14_OMR_PR2_Msk (0x40000UL) |
| |
| #define | PORT14_OMR_PR3_Pos (19UL) |
| |
| #define | PORT14_OMR_PR3_Msk (0x80000UL) |
| |
| #define | PORT14_OMR_PR4_Pos (20UL) |
| |
| #define | PORT14_OMR_PR4_Msk (0x100000UL) |
| |
| #define | PORT14_OMR_PR5_Pos (21UL) |
| |
| #define | PORT14_OMR_PR5_Msk (0x200000UL) |
| |
| #define | PORT14_OMR_PR6_Pos (22UL) |
| |
| #define | PORT14_OMR_PR6_Msk (0x400000UL) |
| |
| #define | PORT14_OMR_PR7_Pos (23UL) |
| |
| #define | PORT14_OMR_PR7_Msk (0x800000UL) |
| |
| #define | PORT14_OMR_PR8_Pos (24UL) |
| |
| #define | PORT14_OMR_PR8_Msk (0x1000000UL) |
| |
| #define | PORT14_OMR_PR9_Pos (25UL) |
| |
| #define | PORT14_OMR_PR9_Msk (0x2000000UL) |
| |
| #define | PORT14_OMR_PR10_Pos (26UL) |
| |
| #define | PORT14_OMR_PR10_Msk (0x4000000UL) |
| |
| #define | PORT14_OMR_PR11_Pos (27UL) |
| |
| #define | PORT14_OMR_PR11_Msk (0x8000000UL) |
| |
| #define | PORT14_OMR_PR12_Pos (28UL) |
| |
| #define | PORT14_OMR_PR12_Msk (0x10000000UL) |
| |
| #define | PORT14_OMR_PR13_Pos (29UL) |
| |
| #define | PORT14_OMR_PR13_Msk (0x20000000UL) |
| |
| #define | PORT14_OMR_PR14_Pos (30UL) |
| |
| #define | PORT14_OMR_PR14_Msk (0x40000000UL) |
| |
| #define | PORT14_OMR_PR15_Pos (31UL) |
| |
| #define | PORT14_OMR_PR15_Msk (0x80000000UL) |
| |
| #define | PORT14_IOCR0_PC0_Pos (3UL) |
| |
| #define | PORT14_IOCR0_PC0_Msk (0xf8UL) |
| |
| #define | PORT14_IOCR0_PC1_Pos (11UL) |
| |
| #define | PORT14_IOCR0_PC1_Msk (0xf800UL) |
| |
| #define | PORT14_IOCR0_PC2_Pos (19UL) |
| |
| #define | PORT14_IOCR0_PC2_Msk (0xf80000UL) |
| |
| #define | PORT14_IOCR0_PC3_Pos (27UL) |
| |
| #define | PORT14_IOCR0_PC3_Msk (0xf8000000UL) |
| |
| #define | PORT14_IOCR4_PC4_Pos (3UL) |
| |
| #define | PORT14_IOCR4_PC4_Msk (0xf8UL) |
| |
| #define | PORT14_IOCR4_PC5_Pos (11UL) |
| |
| #define | PORT14_IOCR4_PC5_Msk (0xf800UL) |
| |
| #define | PORT14_IOCR4_PC6_Pos (19UL) |
| |
| #define | PORT14_IOCR4_PC6_Msk (0xf80000UL) |
| |
| #define | PORT14_IOCR4_PC7_Pos (27UL) |
| |
| #define | PORT14_IOCR4_PC7_Msk (0xf8000000UL) |
| |
| #define | PORT14_IOCR8_PC8_Pos (3UL) |
| |
| #define | PORT14_IOCR8_PC8_Msk (0xf8UL) |
| |
| #define | PORT14_IOCR8_PC9_Pos (11UL) |
| |
| #define | PORT14_IOCR8_PC9_Msk (0xf800UL) |
| |
| #define | PORT14_IOCR8_PC10_Pos (19UL) |
| |
| #define | PORT14_IOCR8_PC10_Msk (0xf80000UL) |
| |
| #define | PORT14_IOCR8_PC11_Pos (27UL) |
| |
| #define | PORT14_IOCR8_PC11_Msk (0xf8000000UL) |
| |
| #define | PORT14_IOCR12_PC12_Pos (3UL) |
| |
| #define | PORT14_IOCR12_PC12_Msk (0xf8UL) |
| |
| #define | PORT14_IOCR12_PC13_Pos (11UL) |
| |
| #define | PORT14_IOCR12_PC13_Msk (0xf800UL) |
| |
| #define | PORT14_IOCR12_PC14_Pos (19UL) |
| |
| #define | PORT14_IOCR12_PC14_Msk (0xf80000UL) |
| |
| #define | PORT14_IOCR12_PC15_Pos (27UL) |
| |
| #define | PORT14_IOCR12_PC15_Msk (0xf8000000UL) |
| |
| #define | PORT14_IN_P0_Pos (0UL) |
| |
| #define | PORT14_IN_P0_Msk (0x1UL) |
| |
| #define | PORT14_IN_P1_Pos (1UL) |
| |
| #define | PORT14_IN_P1_Msk (0x2UL) |
| |
| #define | PORT14_IN_P2_Pos (2UL) |
| |
| #define | PORT14_IN_P2_Msk (0x4UL) |
| |
| #define | PORT14_IN_P3_Pos (3UL) |
| |
| #define | PORT14_IN_P3_Msk (0x8UL) |
| |
| #define | PORT14_IN_P4_Pos (4UL) |
| |
| #define | PORT14_IN_P4_Msk (0x10UL) |
| |
| #define | PORT14_IN_P5_Pos (5UL) |
| |
| #define | PORT14_IN_P5_Msk (0x20UL) |
| |
| #define | PORT14_IN_P6_Pos (6UL) |
| |
| #define | PORT14_IN_P6_Msk (0x40UL) |
| |
| #define | PORT14_IN_P7_Pos (7UL) |
| |
| #define | PORT14_IN_P7_Msk (0x80UL) |
| |
| #define | PORT14_IN_P8_Pos (8UL) |
| |
| #define | PORT14_IN_P8_Msk (0x100UL) |
| |
| #define | PORT14_IN_P9_Pos (9UL) |
| |
| #define | PORT14_IN_P9_Msk (0x200UL) |
| |
| #define | PORT14_IN_P10_Pos (10UL) |
| |
| #define | PORT14_IN_P10_Msk (0x400UL) |
| |
| #define | PORT14_IN_P11_Pos (11UL) |
| |
| #define | PORT14_IN_P11_Msk (0x800UL) |
| |
| #define | PORT14_IN_P12_Pos (12UL) |
| |
| #define | PORT14_IN_P12_Msk (0x1000UL) |
| |
| #define | PORT14_IN_P13_Pos (13UL) |
| |
| #define | PORT14_IN_P13_Msk (0x2000UL) |
| |
| #define | PORT14_IN_P14_Pos (14UL) |
| |
| #define | PORT14_IN_P14_Msk (0x4000UL) |
| |
| #define | PORT14_IN_P15_Pos (15UL) |
| |
| #define | PORT14_IN_P15_Msk (0x8000UL) |
| |
| #define | PORT14_PDISC_PDIS0_Pos (0UL) |
| |
| #define | PORT14_PDISC_PDIS0_Msk (0x1UL) |
| |
| #define | PORT14_PDISC_PDIS1_Pos (1UL) |
| |
| #define | PORT14_PDISC_PDIS1_Msk (0x2UL) |
| |
| #define | PORT14_PDISC_PDIS2_Pos (2UL) |
| |
| #define | PORT14_PDISC_PDIS2_Msk (0x4UL) |
| |
| #define | PORT14_PDISC_PDIS3_Pos (3UL) |
| |
| #define | PORT14_PDISC_PDIS3_Msk (0x8UL) |
| |
| #define | PORT14_PDISC_PDIS4_Pos (4UL) |
| |
| #define | PORT14_PDISC_PDIS4_Msk (0x10UL) |
| |
| #define | PORT14_PDISC_PDIS5_Pos (5UL) |
| |
| #define | PORT14_PDISC_PDIS5_Msk (0x20UL) |
| |
| #define | PORT14_PDISC_PDIS6_Pos (6UL) |
| |
| #define | PORT14_PDISC_PDIS6_Msk (0x40UL) |
| |
| #define | PORT14_PDISC_PDIS7_Pos (7UL) |
| |
| #define | PORT14_PDISC_PDIS7_Msk (0x80UL) |
| |
| #define | PORT14_PDISC_PDIS8_Pos (8UL) |
| |
| #define | PORT14_PDISC_PDIS8_Msk (0x100UL) |
| |
| #define | PORT14_PDISC_PDIS9_Pos (9UL) |
| |
| #define | PORT14_PDISC_PDIS9_Msk (0x200UL) |
| |
| #define | PORT14_PDISC_PDIS12_Pos (12UL) |
| |
| #define | PORT14_PDISC_PDIS12_Msk (0x1000UL) |
| |
| #define | PORT14_PDISC_PDIS13_Pos (13UL) |
| |
| #define | PORT14_PDISC_PDIS13_Msk (0x2000UL) |
| |
| #define | PORT14_PDISC_PDIS14_Pos (14UL) |
| |
| #define | PORT14_PDISC_PDIS14_Msk (0x4000UL) |
| |
| #define | PORT14_PDISC_PDIS15_Pos (15UL) |
| |
| #define | PORT14_PDISC_PDIS15_Msk (0x8000UL) |
| |
| #define | PORT14_PPS_PPS0_Pos (0UL) |
| |
| #define | PORT14_PPS_PPS0_Msk (0x1UL) |
| |
| #define | PORT14_PPS_PPS1_Pos (1UL) |
| |
| #define | PORT14_PPS_PPS1_Msk (0x2UL) |
| |
| #define | PORT14_PPS_PPS2_Pos (2UL) |
| |
| #define | PORT14_PPS_PPS2_Msk (0x4UL) |
| |
| #define | PORT14_PPS_PPS3_Pos (3UL) |
| |
| #define | PORT14_PPS_PPS3_Msk (0x8UL) |
| |
| #define | PORT14_PPS_PPS4_Pos (4UL) |
| |
| #define | PORT14_PPS_PPS4_Msk (0x10UL) |
| |
| #define | PORT14_PPS_PPS5_Pos (5UL) |
| |
| #define | PORT14_PPS_PPS5_Msk (0x20UL) |
| |
| #define | PORT14_PPS_PPS6_Pos (6UL) |
| |
| #define | PORT14_PPS_PPS6_Msk (0x40UL) |
| |
| #define | PORT14_PPS_PPS7_Pos (7UL) |
| |
| #define | PORT14_PPS_PPS7_Msk (0x80UL) |
| |
| #define | PORT14_PPS_PPS8_Pos (8UL) |
| |
| #define | PORT14_PPS_PPS8_Msk (0x100UL) |
| |
| #define | PORT14_PPS_PPS9_Pos (9UL) |
| |
| #define | PORT14_PPS_PPS9_Msk (0x200UL) |
| |
| #define | PORT14_PPS_PPS10_Pos (10UL) |
| |
| #define | PORT14_PPS_PPS10_Msk (0x400UL) |
| |
| #define | PORT14_PPS_PPS11_Pos (11UL) |
| |
| #define | PORT14_PPS_PPS11_Msk (0x800UL) |
| |
| #define | PORT14_PPS_PPS12_Pos (12UL) |
| |
| #define | PORT14_PPS_PPS12_Msk (0x1000UL) |
| |
| #define | PORT14_PPS_PPS13_Pos (13UL) |
| |
| #define | PORT14_PPS_PPS13_Msk (0x2000UL) |
| |
| #define | PORT14_PPS_PPS14_Pos (14UL) |
| |
| #define | PORT14_PPS_PPS14_Msk (0x4000UL) |
| |
| #define | PORT14_PPS_PPS15_Pos (15UL) |
| |
| #define | PORT14_PPS_PPS15_Msk (0x8000UL) |
| |
| #define | PORT14_HWSEL_HW0_Pos (0UL) |
| |
| #define | PORT14_HWSEL_HW0_Msk (0x3UL) |
| |
| #define | PORT14_HWSEL_HW1_Pos (2UL) |
| |
| #define | PORT14_HWSEL_HW1_Msk (0xcUL) |
| |
| #define | PORT14_HWSEL_HW2_Pos (4UL) |
| |
| #define | PORT14_HWSEL_HW2_Msk (0x30UL) |
| |
| #define | PORT14_HWSEL_HW3_Pos (6UL) |
| |
| #define | PORT14_HWSEL_HW3_Msk (0xc0UL) |
| |
| #define | PORT14_HWSEL_HW4_Pos (8UL) |
| |
| #define | PORT14_HWSEL_HW4_Msk (0x300UL) |
| |
| #define | PORT14_HWSEL_HW5_Pos (10UL) |
| |
| #define | PORT14_HWSEL_HW5_Msk (0xc00UL) |
| |
| #define | PORT14_HWSEL_HW6_Pos (12UL) |
| |
| #define | PORT14_HWSEL_HW6_Msk (0x3000UL) |
| |
| #define | PORT14_HWSEL_HW7_Pos (14UL) |
| |
| #define | PORT14_HWSEL_HW7_Msk (0xc000UL) |
| |
| #define | PORT14_HWSEL_HW8_Pos (16UL) |
| |
| #define | PORT14_HWSEL_HW8_Msk (0x30000UL) |
| |
| #define | PORT14_HWSEL_HW9_Pos (18UL) |
| |
| #define | PORT14_HWSEL_HW9_Msk (0xc0000UL) |
| |
| #define | PORT14_HWSEL_HW10_Pos (20UL) |
| |
| #define | PORT14_HWSEL_HW10_Msk (0x300000UL) |
| |
| #define | PORT14_HWSEL_HW11_Pos (22UL) |
| |
| #define | PORT14_HWSEL_HW11_Msk (0xc00000UL) |
| |
| #define | PORT14_HWSEL_HW12_Pos (24UL) |
| |
| #define | PORT14_HWSEL_HW12_Msk (0x3000000UL) |
| |
| #define | PORT14_HWSEL_HW13_Pos (26UL) |
| |
| #define | PORT14_HWSEL_HW13_Msk (0xc000000UL) |
| |
| #define | PORT14_HWSEL_HW14_Pos (28UL) |
| |
| #define | PORT14_HWSEL_HW14_Msk (0x30000000UL) |
| |
| #define | PORT14_HWSEL_HW15_Pos (30UL) |
| |
| #define | PORT14_HWSEL_HW15_Msk (0xc0000000UL) |
| |
| #define | PORT15_OUT_P0_Pos (0UL) |
| |
| #define | PORT15_OUT_P0_Msk (0x1UL) |
| |
| #define | PORT15_OUT_P1_Pos (1UL) |
| |
| #define | PORT15_OUT_P1_Msk (0x2UL) |
| |
| #define | PORT15_OUT_P2_Pos (2UL) |
| |
| #define | PORT15_OUT_P2_Msk (0x4UL) |
| |
| #define | PORT15_OUT_P3_Pos (3UL) |
| |
| #define | PORT15_OUT_P3_Msk (0x8UL) |
| |
| #define | PORT15_OUT_P4_Pos (4UL) |
| |
| #define | PORT15_OUT_P4_Msk (0x10UL) |
| |
| #define | PORT15_OUT_P5_Pos (5UL) |
| |
| #define | PORT15_OUT_P5_Msk (0x20UL) |
| |
| #define | PORT15_OUT_P6_Pos (6UL) |
| |
| #define | PORT15_OUT_P6_Msk (0x40UL) |
| |
| #define | PORT15_OUT_P7_Pos (7UL) |
| |
| #define | PORT15_OUT_P7_Msk (0x80UL) |
| |
| #define | PORT15_OUT_P8_Pos (8UL) |
| |
| #define | PORT15_OUT_P8_Msk (0x100UL) |
| |
| #define | PORT15_OUT_P9_Pos (9UL) |
| |
| #define | PORT15_OUT_P9_Msk (0x200UL) |
| |
| #define | PORT15_OUT_P10_Pos (10UL) |
| |
| #define | PORT15_OUT_P10_Msk (0x400UL) |
| |
| #define | PORT15_OUT_P11_Pos (11UL) |
| |
| #define | PORT15_OUT_P11_Msk (0x800UL) |
| |
| #define | PORT15_OUT_P12_Pos (12UL) |
| |
| #define | PORT15_OUT_P12_Msk (0x1000UL) |
| |
| #define | PORT15_OUT_P13_Pos (13UL) |
| |
| #define | PORT15_OUT_P13_Msk (0x2000UL) |
| |
| #define | PORT15_OUT_P14_Pos (14UL) |
| |
| #define | PORT15_OUT_P14_Msk (0x4000UL) |
| |
| #define | PORT15_OUT_P15_Pos (15UL) |
| |
| #define | PORT15_OUT_P15_Msk (0x8000UL) |
| |
| #define | PORT15_OMR_PS0_Pos (0UL) |
| |
| #define | PORT15_OMR_PS0_Msk (0x1UL) |
| |
| #define | PORT15_OMR_PS1_Pos (1UL) |
| |
| #define | PORT15_OMR_PS1_Msk (0x2UL) |
| |
| #define | PORT15_OMR_PS2_Pos (2UL) |
| |
| #define | PORT15_OMR_PS2_Msk (0x4UL) |
| |
| #define | PORT15_OMR_PS3_Pos (3UL) |
| |
| #define | PORT15_OMR_PS3_Msk (0x8UL) |
| |
| #define | PORT15_OMR_PS4_Pos (4UL) |
| |
| #define | PORT15_OMR_PS4_Msk (0x10UL) |
| |
| #define | PORT15_OMR_PS5_Pos (5UL) |
| |
| #define | PORT15_OMR_PS5_Msk (0x20UL) |
| |
| #define | PORT15_OMR_PS6_Pos (6UL) |
| |
| #define | PORT15_OMR_PS6_Msk (0x40UL) |
| |
| #define | PORT15_OMR_PS7_Pos (7UL) |
| |
| #define | PORT15_OMR_PS7_Msk (0x80UL) |
| |
| #define | PORT15_OMR_PS8_Pos (8UL) |
| |
| #define | PORT15_OMR_PS8_Msk (0x100UL) |
| |
| #define | PORT15_OMR_PS9_Pos (9UL) |
| |
| #define | PORT15_OMR_PS9_Msk (0x200UL) |
| |
| #define | PORT15_OMR_PS10_Pos (10UL) |
| |
| #define | PORT15_OMR_PS10_Msk (0x400UL) |
| |
| #define | PORT15_OMR_PS11_Pos (11UL) |
| |
| #define | PORT15_OMR_PS11_Msk (0x800UL) |
| |
| #define | PORT15_OMR_PS12_Pos (12UL) |
| |
| #define | PORT15_OMR_PS12_Msk (0x1000UL) |
| |
| #define | PORT15_OMR_PS13_Pos (13UL) |
| |
| #define | PORT15_OMR_PS13_Msk (0x2000UL) |
| |
| #define | PORT15_OMR_PS14_Pos (14UL) |
| |
| #define | PORT15_OMR_PS14_Msk (0x4000UL) |
| |
| #define | PORT15_OMR_PS15_Pos (15UL) |
| |
| #define | PORT15_OMR_PS15_Msk (0x8000UL) |
| |
| #define | PORT15_OMR_PR0_Pos (16UL) |
| |
| #define | PORT15_OMR_PR0_Msk (0x10000UL) |
| |
| #define | PORT15_OMR_PR1_Pos (17UL) |
| |
| #define | PORT15_OMR_PR1_Msk (0x20000UL) |
| |
| #define | PORT15_OMR_PR2_Pos (18UL) |
| |
| #define | PORT15_OMR_PR2_Msk (0x40000UL) |
| |
| #define | PORT15_OMR_PR3_Pos (19UL) |
| |
| #define | PORT15_OMR_PR3_Msk (0x80000UL) |
| |
| #define | PORT15_OMR_PR4_Pos (20UL) |
| |
| #define | PORT15_OMR_PR4_Msk (0x100000UL) |
| |
| #define | PORT15_OMR_PR5_Pos (21UL) |
| |
| #define | PORT15_OMR_PR5_Msk (0x200000UL) |
| |
| #define | PORT15_OMR_PR6_Pos (22UL) |
| |
| #define | PORT15_OMR_PR6_Msk (0x400000UL) |
| |
| #define | PORT15_OMR_PR7_Pos (23UL) |
| |
| #define | PORT15_OMR_PR7_Msk (0x800000UL) |
| |
| #define | PORT15_OMR_PR8_Pos (24UL) |
| |
| #define | PORT15_OMR_PR8_Msk (0x1000000UL) |
| |
| #define | PORT15_OMR_PR9_Pos (25UL) |
| |
| #define | PORT15_OMR_PR9_Msk (0x2000000UL) |
| |
| #define | PORT15_OMR_PR10_Pos (26UL) |
| |
| #define | PORT15_OMR_PR10_Msk (0x4000000UL) |
| |
| #define | PORT15_OMR_PR11_Pos (27UL) |
| |
| #define | PORT15_OMR_PR11_Msk (0x8000000UL) |
| |
| #define | PORT15_OMR_PR12_Pos (28UL) |
| |
| #define | PORT15_OMR_PR12_Msk (0x10000000UL) |
| |
| #define | PORT15_OMR_PR13_Pos (29UL) |
| |
| #define | PORT15_OMR_PR13_Msk (0x20000000UL) |
| |
| #define | PORT15_OMR_PR14_Pos (30UL) |
| |
| #define | PORT15_OMR_PR14_Msk (0x40000000UL) |
| |
| #define | PORT15_OMR_PR15_Pos (31UL) |
| |
| #define | PORT15_OMR_PR15_Msk (0x80000000UL) |
| |
| #define | PORT15_IOCR0_PC0_Pos (3UL) |
| |
| #define | PORT15_IOCR0_PC0_Msk (0xf8UL) |
| |
| #define | PORT15_IOCR0_PC1_Pos (11UL) |
| |
| #define | PORT15_IOCR0_PC1_Msk (0xf800UL) |
| |
| #define | PORT15_IOCR0_PC2_Pos (19UL) |
| |
| #define | PORT15_IOCR0_PC2_Msk (0xf80000UL) |
| |
| #define | PORT15_IOCR0_PC3_Pos (27UL) |
| |
| #define | PORT15_IOCR0_PC3_Msk (0xf8000000UL) |
| |
| #define | PORT15_IOCR4_PC4_Pos (3UL) |
| |
| #define | PORT15_IOCR4_PC4_Msk (0xf8UL) |
| |
| #define | PORT15_IOCR4_PC5_Pos (11UL) |
| |
| #define | PORT15_IOCR4_PC5_Msk (0xf800UL) |
| |
| #define | PORT15_IOCR4_PC6_Pos (19UL) |
| |
| #define | PORT15_IOCR4_PC6_Msk (0xf80000UL) |
| |
| #define | PORT15_IOCR4_PC7_Pos (27UL) |
| |
| #define | PORT15_IOCR4_PC7_Msk (0xf8000000UL) |
| |
| #define | PORT15_IOCR8_PC8_Pos (3UL) |
| |
| #define | PORT15_IOCR8_PC8_Msk (0xf8UL) |
| |
| #define | PORT15_IOCR8_PC9_Pos (11UL) |
| |
| #define | PORT15_IOCR8_PC9_Msk (0xf800UL) |
| |
| #define | PORT15_IOCR8_PC10_Pos (19UL) |
| |
| #define | PORT15_IOCR8_PC10_Msk (0xf80000UL) |
| |
| #define | PORT15_IOCR8_PC11_Pos (27UL) |
| |
| #define | PORT15_IOCR8_PC11_Msk (0xf8000000UL) |
| |
| #define | PORT15_IOCR12_PC12_Pos (3UL) |
| |
| #define | PORT15_IOCR12_PC12_Msk (0xf8UL) |
| |
| #define | PORT15_IOCR12_PC13_Pos (11UL) |
| |
| #define | PORT15_IOCR12_PC13_Msk (0xf800UL) |
| |
| #define | PORT15_IOCR12_PC14_Pos (19UL) |
| |
| #define | PORT15_IOCR12_PC14_Msk (0xf80000UL) |
| |
| #define | PORT15_IOCR12_PC15_Pos (27UL) |
| |
| #define | PORT15_IOCR12_PC15_Msk (0xf8000000UL) |
| |
| #define | PORT15_IN_P0_Pos (0UL) |
| |
| #define | PORT15_IN_P0_Msk (0x1UL) |
| |
| #define | PORT15_IN_P1_Pos (1UL) |
| |
| #define | PORT15_IN_P1_Msk (0x2UL) |
| |
| #define | PORT15_IN_P2_Pos (2UL) |
| |
| #define | PORT15_IN_P2_Msk (0x4UL) |
| |
| #define | PORT15_IN_P3_Pos (3UL) |
| |
| #define | PORT15_IN_P3_Msk (0x8UL) |
| |
| #define | PORT15_IN_P4_Pos (4UL) |
| |
| #define | PORT15_IN_P4_Msk (0x10UL) |
| |
| #define | PORT15_IN_P5_Pos (5UL) |
| |
| #define | PORT15_IN_P5_Msk (0x20UL) |
| |
| #define | PORT15_IN_P6_Pos (6UL) |
| |
| #define | PORT15_IN_P6_Msk (0x40UL) |
| |
| #define | PORT15_IN_P7_Pos (7UL) |
| |
| #define | PORT15_IN_P7_Msk (0x80UL) |
| |
| #define | PORT15_IN_P8_Pos (8UL) |
| |
| #define | PORT15_IN_P8_Msk (0x100UL) |
| |
| #define | PORT15_IN_P9_Pos (9UL) |
| |
| #define | PORT15_IN_P9_Msk (0x200UL) |
| |
| #define | PORT15_IN_P10_Pos (10UL) |
| |
| #define | PORT15_IN_P10_Msk (0x400UL) |
| |
| #define | PORT15_IN_P11_Pos (11UL) |
| |
| #define | PORT15_IN_P11_Msk (0x800UL) |
| |
| #define | PORT15_IN_P12_Pos (12UL) |
| |
| #define | PORT15_IN_P12_Msk (0x1000UL) |
| |
| #define | PORT15_IN_P13_Pos (13UL) |
| |
| #define | PORT15_IN_P13_Msk (0x2000UL) |
| |
| #define | PORT15_IN_P14_Pos (14UL) |
| |
| #define | PORT15_IN_P14_Msk (0x4000UL) |
| |
| #define | PORT15_IN_P15_Pos (15UL) |
| |
| #define | PORT15_IN_P15_Msk (0x8000UL) |
| |
| #define | PORT15_PDISC_PDIS2_Pos (2UL) |
| |
| #define | PORT15_PDISC_PDIS2_Msk (0x4UL) |
| |
| #define | PORT15_PDISC_PDIS3_Pos (3UL) |
| |
| #define | PORT15_PDISC_PDIS3_Msk (0x8UL) |
| |
| #define | PORT15_PDISC_PDIS4_Pos (4UL) |
| |
| #define | PORT15_PDISC_PDIS4_Msk (0x10UL) |
| |
| #define | PORT15_PDISC_PDIS5_Pos (5UL) |
| |
| #define | PORT15_PDISC_PDIS5_Msk (0x20UL) |
| |
| #define | PORT15_PDISC_PDIS6_Pos (6UL) |
| |
| #define | PORT15_PDISC_PDIS6_Msk (0x40UL) |
| |
| #define | PORT15_PDISC_PDIS7_Pos (7UL) |
| |
| #define | PORT15_PDISC_PDIS7_Msk (0x80UL) |
| |
| #define | PORT15_PDISC_PDIS8_Pos (8UL) |
| |
| #define | PORT15_PDISC_PDIS8_Msk (0x100UL) |
| |
| #define | PORT15_PDISC_PDIS9_Pos (9UL) |
| |
| #define | PORT15_PDISC_PDIS9_Msk (0x200UL) |
| |
| #define | PORT15_PDISC_PDIS12_Pos (12UL) |
| |
| #define | PORT15_PDISC_PDIS12_Msk (0x1000UL) |
| |
| #define | PORT15_PDISC_PDIS13_Pos (13UL) |
| |
| #define | PORT15_PDISC_PDIS13_Msk (0x2000UL) |
| |
| #define | PORT15_PDISC_PDIS14_Pos (14UL) |
| |
| #define | PORT15_PDISC_PDIS14_Msk (0x4000UL) |
| |
| #define | PORT15_PDISC_PDIS15_Pos (15UL) |
| |
| #define | PORT15_PDISC_PDIS15_Msk (0x8000UL) |
| |
| #define | PORT15_PPS_PPS0_Pos (0UL) |
| |
| #define | PORT15_PPS_PPS0_Msk (0x1UL) |
| |
| #define | PORT15_PPS_PPS1_Pos (1UL) |
| |
| #define | PORT15_PPS_PPS1_Msk (0x2UL) |
| |
| #define | PORT15_PPS_PPS2_Pos (2UL) |
| |
| #define | PORT15_PPS_PPS2_Msk (0x4UL) |
| |
| #define | PORT15_PPS_PPS3_Pos (3UL) |
| |
| #define | PORT15_PPS_PPS3_Msk (0x8UL) |
| |
| #define | PORT15_PPS_PPS4_Pos (4UL) |
| |
| #define | PORT15_PPS_PPS4_Msk (0x10UL) |
| |
| #define | PORT15_PPS_PPS5_Pos (5UL) |
| |
| #define | PORT15_PPS_PPS5_Msk (0x20UL) |
| |
| #define | PORT15_PPS_PPS6_Pos (6UL) |
| |
| #define | PORT15_PPS_PPS6_Msk (0x40UL) |
| |
| #define | PORT15_PPS_PPS7_Pos (7UL) |
| |
| #define | PORT15_PPS_PPS7_Msk (0x80UL) |
| |
| #define | PORT15_PPS_PPS8_Pos (8UL) |
| |
| #define | PORT15_PPS_PPS8_Msk (0x100UL) |
| |
| #define | PORT15_PPS_PPS9_Pos (9UL) |
| |
| #define | PORT15_PPS_PPS9_Msk (0x200UL) |
| |
| #define | PORT15_PPS_PPS10_Pos (10UL) |
| |
| #define | PORT15_PPS_PPS10_Msk (0x400UL) |
| |
| #define | PORT15_PPS_PPS11_Pos (11UL) |
| |
| #define | PORT15_PPS_PPS11_Msk (0x800UL) |
| |
| #define | PORT15_PPS_PPS12_Pos (12UL) |
| |
| #define | PORT15_PPS_PPS12_Msk (0x1000UL) |
| |
| #define | PORT15_PPS_PPS13_Pos (13UL) |
| |
| #define | PORT15_PPS_PPS13_Msk (0x2000UL) |
| |
| #define | PORT15_PPS_PPS14_Pos (14UL) |
| |
| #define | PORT15_PPS_PPS14_Msk (0x4000UL) |
| |
| #define | PORT15_PPS_PPS15_Pos (15UL) |
| |
| #define | PORT15_PPS_PPS15_Msk (0x8000UL) |
| |
| #define | PORT15_HWSEL_HW0_Pos (0UL) |
| |
| #define | PORT15_HWSEL_HW0_Msk (0x3UL) |
| |
| #define | PORT15_HWSEL_HW1_Pos (2UL) |
| |
| #define | PORT15_HWSEL_HW1_Msk (0xcUL) |
| |
| #define | PORT15_HWSEL_HW2_Pos (4UL) |
| |
| #define | PORT15_HWSEL_HW2_Msk (0x30UL) |
| |
| #define | PORT15_HWSEL_HW3_Pos (6UL) |
| |
| #define | PORT15_HWSEL_HW3_Msk (0xc0UL) |
| |
| #define | PORT15_HWSEL_HW4_Pos (8UL) |
| |
| #define | PORT15_HWSEL_HW4_Msk (0x300UL) |
| |
| #define | PORT15_HWSEL_HW5_Pos (10UL) |
| |
| #define | PORT15_HWSEL_HW5_Msk (0xc00UL) |
| |
| #define | PORT15_HWSEL_HW6_Pos (12UL) |
| |
| #define | PORT15_HWSEL_HW6_Msk (0x3000UL) |
| |
| #define | PORT15_HWSEL_HW7_Pos (14UL) |
| |
| #define | PORT15_HWSEL_HW7_Msk (0xc000UL) |
| |
| #define | PORT15_HWSEL_HW8_Pos (16UL) |
| |
| #define | PORT15_HWSEL_HW8_Msk (0x30000UL) |
| |
| #define | PORT15_HWSEL_HW9_Pos (18UL) |
| |
| #define | PORT15_HWSEL_HW9_Msk (0xc0000UL) |
| |
| #define | PORT15_HWSEL_HW10_Pos (20UL) |
| |
| #define | PORT15_HWSEL_HW10_Msk (0x300000UL) |
| |
| #define | PORT15_HWSEL_HW11_Pos (22UL) |
| |
| #define | PORT15_HWSEL_HW11_Msk (0xc00000UL) |
| |
| #define | PORT15_HWSEL_HW12_Pos (24UL) |
| |
| #define | PORT15_HWSEL_HW12_Msk (0x3000000UL) |
| |
| #define | PORT15_HWSEL_HW13_Pos (26UL) |
| |
| #define | PORT15_HWSEL_HW13_Msk (0xc000000UL) |
| |
| #define | PORT15_HWSEL_HW14_Pos (28UL) |
| |
| #define | PORT15_HWSEL_HW14_Msk (0x30000000UL) |
| |
| #define | PORT15_HWSEL_HW15_Pos (30UL) |
| |
| #define | PORT15_HWSEL_HW15_Msk (0xc0000000UL) |
| |
| #define | PPB_BASE 0xE000E000UL |
| |
| #define | DLR_BASE 0x50004900UL |
| |
| #define | ERU0_BASE 0x50004800UL |
| |
| #define | ERU1_BASE 0x40044000UL |
| |
| #define | GPDMA0_BASE 0x500142C0UL |
| |
| #define | GPDMA0_CH0_BASE 0x50014000UL |
| |
| #define | GPDMA0_CH1_BASE 0x50014058UL |
| |
| #define | GPDMA0_CH2_BASE 0x500140B0UL |
| |
| #define | GPDMA0_CH3_BASE 0x50014108UL |
| |
| #define | GPDMA0_CH4_BASE 0x50014160UL |
| |
| #define | GPDMA0_CH5_BASE 0x500141B8UL |
| |
| #define | GPDMA0_CH6_BASE 0x50014210UL |
| |
| #define | GPDMA0_CH7_BASE 0x50014268UL |
| |
| #define | GPDMA1_BASE 0x500182C0UL |
| |
| #define | GPDMA1_CH0_BASE 0x50018000UL |
| |
| #define | GPDMA1_CH1_BASE 0x50018058UL |
| |
| #define | GPDMA1_CH2_BASE 0x500180B0UL |
| |
| #define | GPDMA1_CH3_BASE 0x50018108UL |
| |
| #define | FCE_BASE 0x50020000UL |
| |
| #define | FCE_KE0_BASE 0x50020020UL |
| |
| #define | FCE_KE1_BASE 0x50020040UL |
| |
| #define | FCE_KE2_BASE 0x50020060UL |
| |
| #define | FCE_KE3_BASE 0x50020080UL |
| |
| #define | PBA0_BASE 0x40000000UL |
| |
| #define | PBA1_BASE 0x48000000UL |
| |
| #define | FLASH0_BASE 0x58001000UL |
| |
| #define | PREF_BASE 0x58004000UL |
| |
| #define | PMU0_BASE 0x58000508UL |
| |
| #define | WDT_BASE 0x50008000UL |
| |
| #define | RTC_BASE 0x50004A00UL |
| |
| #define | SCU_CLK_BASE 0x50004600UL |
| |
| #define | SCU_OSC_BASE 0x50004700UL |
| |
| #define | SCU_PLL_BASE 0x50004710UL |
| |
| #define | SCU_GENERAL_BASE 0x50004000UL |
| |
| #define | SCU_INTERRUPT_BASE 0x50004074UL |
| |
| #define | SCU_PARITY_BASE 0x5000413CUL |
| |
| #define | SCU_TRAP_BASE 0x50004160UL |
| |
| #define | SCU_HIBERNATE_BASE 0x50004300UL |
| |
| #define | SCU_POWER_BASE 0x50004200UL |
| |
| #define | SCU_RESET_BASE 0x50004400UL |
| |
| #define | LEDTS0_BASE 0x48010000UL |
| |
| #define | SDMMC_CON_BASE 0x500040B4UL |
| |
| #define | SDMMC_BASE 0x4801C000UL |
| |
| #define | EBU_BASE 0x58008000UL |
| |
| #define | ETH0_CON_BASE 0x50004040UL |
| |
| #define | ETH0_BASE 0x5000C000UL |
| |
| #define | ECAT0_CON_BASE 0x500041B0UL |
| |
| #define | ECAT0_BASE 0x54010000UL |
| |
| #define | ECAT0_FMMU0_BASE 0x54010600UL |
| |
| #define | ECAT0_FMMU1_BASE 0x54010610UL |
| |
| #define | ECAT0_FMMU2_BASE 0x54010620UL |
| |
| #define | ECAT0_FMMU3_BASE 0x54010630UL |
| |
| #define | ECAT0_FMMU4_BASE 0x54010640UL |
| |
| #define | ECAT0_FMMU5_BASE 0x54010650UL |
| |
| #define | ECAT0_FMMU6_BASE 0x54010660UL |
| |
| #define | ECAT0_FMMU7_BASE 0x54010670UL |
| |
| #define | ECAT0_SM0_BASE 0x54010800UL |
| |
| #define | ECAT0_SM1_BASE 0x54010808UL |
| |
| #define | ECAT0_SM2_BASE 0x54010810UL |
| |
| #define | ECAT0_SM3_BASE 0x54010818UL |
| |
| #define | ECAT0_SM4_BASE 0x54010820UL |
| |
| #define | ECAT0_SM5_BASE 0x54010828UL |
| |
| #define | ECAT0_SM6_BASE 0x54010830UL |
| |
| #define | ECAT0_SM7_BASE 0x54010838UL |
| |
| #define | USB0_BASE 0x50040000UL |
| |
| #define | USB_EP_BASE 0x50040900UL |
| |
| #define | USB0_EP1_BASE 0x50040920UL |
| |
| #define | USB0_EP2_BASE 0x50040940UL |
| |
| #define | USB0_EP3_BASE 0x50040960UL |
| |
| #define | USB0_EP4_BASE 0x50040980UL |
| |
| #define | USB0_EP5_BASE 0x500409A0UL |
| |
| #define | USB0_EP6_BASE 0x500409C0UL |
| |
| #define | USB0_CH0_BASE 0x50040500UL |
| |
| #define | USB0_CH1_BASE 0x50040520UL |
| |
| #define | USB0_CH2_BASE 0x50040540UL |
| |
| #define | USB0_CH3_BASE 0x50040560UL |
| |
| #define | USB0_CH4_BASE 0x50040580UL |
| |
| #define | USB0_CH5_BASE 0x500405A0UL |
| |
| #define | USB0_CH6_BASE 0x500405C0UL |
| |
| #define | USB0_CH7_BASE 0x500405E0UL |
| |
| #define | USB0_CH8_BASE 0x50040600UL |
| |
| #define | USB0_CH9_BASE 0x50040620UL |
| |
| #define | USB0_CH10_BASE 0x50040640UL |
| |
| #define | USB0_CH11_BASE 0x50040660UL |
| |
| #define | USB0_CH12_BASE 0x50040680UL |
| |
| #define | USB0_CH13_BASE 0x500406A0UL |
| |
| #define | USIC0_BASE 0x40030008UL |
| |
| #define | USIC1_BASE 0x48020008UL |
| |
| #define | USIC2_BASE 0x48024008UL |
| |
| #define | USIC0_CH0_BASE 0x40030000UL |
| |
| #define | USIC0_CH1_BASE 0x40030200UL |
| |
| #define | USIC1_CH0_BASE 0x48020000UL |
| |
| #define | USIC1_CH1_BASE 0x48020200UL |
| |
| #define | USIC2_CH0_BASE 0x48024000UL |
| |
| #define | USIC2_CH1_BASE 0x48024200UL |
| |
| #define | CAN_BASE 0x48014000UL |
| |
| #define | CAN_NODE0_BASE 0x48014200UL |
| |
| #define | CAN_NODE1_BASE 0x48014300UL |
| |
| #define | CAN_NODE2_BASE 0x48014400UL |
| |
| #define | CAN_NODE3_BASE 0x48014500UL |
| |
| #define | CAN_NODE4_BASE 0x48014600UL |
| |
| #define | CAN_NODE5_BASE 0x48014700UL |
| |
| #define | CAN_MO_BASE 0x48015000UL |
| |
| #define | VADC_BASE 0x40004000UL |
| |
| #define | VADC_G0_BASE 0x40004400UL |
| |
| #define | VADC_G1_BASE 0x40004800UL |
| |
| #define | VADC_G2_BASE 0x40004C00UL |
| |
| #define | VADC_G3_BASE 0x40005000UL |
| |
| #define | DSD_BASE 0x40008000UL |
| |
| #define | DSD_CH0_BASE 0x40008100UL |
| |
| #define | DSD_CH1_BASE 0x40008200UL |
| |
| #define | DSD_CH2_BASE 0x40008300UL |
| |
| #define | DSD_CH3_BASE 0x40008400UL |
| |
| #define | DAC_BASE 0x48018000UL |
| |
| #define | CCU40_BASE 0x4000C000UL |
| |
| #define | CCU41_BASE 0x40010000UL |
| |
| #define | CCU42_BASE 0x40014000UL |
| |
| #define | CCU43_BASE 0x48004000UL |
| |
| #define | CCU40_CC40_BASE 0x4000C100UL |
| |
| #define | CCU40_CC41_BASE 0x4000C200UL |
| |
| #define | CCU40_CC42_BASE 0x4000C300UL |
| |
| #define | CCU40_CC43_BASE 0x4000C400UL |
| |
| #define | CCU41_CC40_BASE 0x40010100UL |
| |
| #define | CCU41_CC41_BASE 0x40010200UL |
| |
| #define | CCU41_CC42_BASE 0x40010300UL |
| |
| #define | CCU41_CC43_BASE 0x40010400UL |
| |
| #define | CCU42_CC40_BASE 0x40014100UL |
| |
| #define | CCU42_CC41_BASE 0x40014200UL |
| |
| #define | CCU42_CC42_BASE 0x40014300UL |
| |
| #define | CCU42_CC43_BASE 0x40014400UL |
| |
| #define | CCU43_CC40_BASE 0x48004100UL |
| |
| #define | CCU43_CC41_BASE 0x48004200UL |
| |
| #define | CCU43_CC42_BASE 0x48004300UL |
| |
| #define | CCU43_CC43_BASE 0x48004400UL |
| |
| #define | CCU80_BASE 0x40020000UL |
| |
| #define | CCU81_BASE 0x40024000UL |
| |
| #define | CCU80_CC80_BASE 0x40020100UL |
| |
| #define | CCU80_CC81_BASE 0x40020200UL |
| |
| #define | CCU80_CC82_BASE 0x40020300UL |
| |
| #define | CCU80_CC83_BASE 0x40020400UL |
| |
| #define | CCU81_CC80_BASE 0x40024100UL |
| |
| #define | CCU81_CC81_BASE 0x40024200UL |
| |
| #define | CCU81_CC82_BASE 0x40024300UL |
| |
| #define | CCU81_CC83_BASE 0x40024400UL |
| |
| #define | POSIF0_BASE 0x40028000UL |
| |
| #define | POSIF1_BASE 0x4002C000UL |
| |
| #define | PORT0_BASE 0x48028000UL |
| |
| #define | PORT1_BASE 0x48028100UL |
| |
| #define | PORT2_BASE 0x48028200UL |
| |
| #define | PORT3_BASE 0x48028300UL |
| |
| #define | PORT4_BASE 0x48028400UL |
| |
| #define | PORT5_BASE 0x48028500UL |
| |
| #define | PORT6_BASE 0x48028600UL |
| |
| #define | PORT7_BASE 0x48028700UL |
| |
| #define | PORT8_BASE 0x48028800UL |
| |
| #define | PORT9_BASE 0x48028900UL |
| |
| #define | PORT14_BASE 0x48028E00UL |
| |
| #define | PORT15_BASE 0x48028F00UL |
| |
| #define | PPB ((PPB_Type *) PPB_BASE) |
| |
| #define | DLR ((DLR_GLOBAL_TypeDef *) DLR_BASE) |
| |
| #define | ERU0 ((ERU_GLOBAL_TypeDef *) ERU0_BASE) |
| |
| #define | ERU1 ((ERU_GLOBAL_TypeDef *) ERU1_BASE) |
| |
| #define | GPDMA0 ((GPDMA0_GLOBAL_TypeDef *) GPDMA0_BASE) |
| |
| #define | GPDMA0_CH0 ((GPDMA0_CH_TypeDef *) GPDMA0_CH0_BASE) |
| |
| #define | GPDMA0_CH1 ((GPDMA0_CH_TypeDef *) GPDMA0_CH1_BASE) |
| |
| #define | GPDMA0_CH2 ((GPDMA0_CH_TypeDef *) GPDMA0_CH2_BASE) |
| |
| #define | GPDMA0_CH3 ((GPDMA0_CH_TypeDef *) GPDMA0_CH3_BASE) |
| |
| #define | GPDMA0_CH4 ((GPDMA0_CH_TypeDef *) GPDMA0_CH4_BASE) |
| |
| #define | GPDMA0_CH5 ((GPDMA0_CH_TypeDef *) GPDMA0_CH5_BASE) |
| |
| #define | GPDMA0_CH6 ((GPDMA0_CH_TypeDef *) GPDMA0_CH6_BASE) |
| |
| #define | GPDMA0_CH7 ((GPDMA0_CH_TypeDef *) GPDMA0_CH7_BASE) |
| |
| #define | GPDMA1 ((GPDMA1_GLOBAL_TypeDef *) GPDMA1_BASE) |
| |
| #define | GPDMA1_CH0 ((GPDMA1_CH_TypeDef *) GPDMA1_CH0_BASE) |
| |
| #define | GPDMA1_CH1 ((GPDMA1_CH_TypeDef *) GPDMA1_CH1_BASE) |
| |
| #define | GPDMA1_CH2 ((GPDMA1_CH_TypeDef *) GPDMA1_CH2_BASE) |
| |
| #define | GPDMA1_CH3 ((GPDMA1_CH_TypeDef *) GPDMA1_CH3_BASE) |
| |
| #define | FCE ((FCE_GLOBAL_TypeDef *) FCE_BASE) |
| |
| #define | FCE_KE0 ((FCE_KE_TypeDef *) FCE_KE0_BASE) |
| |
| #define | FCE_KE1 ((FCE_KE_TypeDef *) FCE_KE1_BASE) |
| |
| #define | FCE_KE2 ((FCE_KE_TypeDef *) FCE_KE2_BASE) |
| |
| #define | FCE_KE3 ((FCE_KE_TypeDef *) FCE_KE3_BASE) |
| |
| #define | PBA0 ((PBA_GLOBAL_TypeDef *) PBA0_BASE) |
| |
| #define | PBA1 ((PBA_GLOBAL_TypeDef *) PBA1_BASE) |
| |
| #define | FLASH0 ((FLASH0_GLOBAL_TypeDef *) FLASH0_BASE) |
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| #define | PREF ((PREF_GLOBAL_TypeDef *) PREF_BASE) |
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| #define | PMU0 ((PMU0_GLOBAL_TypeDef *) PMU0_BASE) |
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| #define | WDT ((WDT_GLOBAL_TypeDef *) WDT_BASE) |
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| #define | RTC ((RTC_GLOBAL_TypeDef *) RTC_BASE) |
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| #define | SCU_CLK ((SCU_CLK_TypeDef *) SCU_CLK_BASE) |
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| #define | SCU_OSC ((SCU_OSC_TypeDef *) SCU_OSC_BASE) |
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| #define | SCU_PLL ((SCU_PLL_TypeDef *) SCU_PLL_BASE) |
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| #define | SCU_GENERAL ((SCU_GENERAL_TypeDef *) SCU_GENERAL_BASE) |
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| #define | SCU_INTERRUPT ((SCU_INTERRUPT_TypeDef *) SCU_INTERRUPT_BASE) |
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| #define | SCU_PARITY ((SCU_PARITY_TypeDef *) SCU_PARITY_BASE) |
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| #define | SCU_TRAP ((SCU_TRAP_TypeDef *) SCU_TRAP_BASE) |
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| #define | SCU_HIBERNATE ((SCU_HIBERNATE_TypeDef *) SCU_HIBERNATE_BASE) |
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| #define | SCU_POWER ((SCU_POWER_TypeDef *) SCU_POWER_BASE) |
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| #define | SCU_RESET ((SCU_RESET_TypeDef *) SCU_RESET_BASE) |
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| #define | LEDTS0 ((LEDTS0_GLOBAL_TypeDef *) LEDTS0_BASE) |
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| #define | SDMMC_CON ((SDMMC_CON_Type *) SDMMC_CON_BASE) |
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| #define | SDMMC ((SDMMC_GLOBAL_TypeDef *) SDMMC_BASE) |
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| #define | EBU ((EBU_Type *) EBU_BASE) |
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| #define | ETH0_CON ((ETH0_CON_GLOBAL_TypeDef *) ETH0_CON_BASE) |
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| #define | ETH0 ((ETH_GLOBAL_TypeDef *) ETH0_BASE) |
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| #define | ECAT0_CON ((ECAT0_CON_Type *) ECAT0_CON_BASE) |
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| #define | ECAT0 ((ECAT_Type *) ECAT0_BASE) |
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| #define | ECAT0_FMMU0 ((ECAT0_FMMU_Type *) ECAT0_FMMU0_BASE) |
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| #define | ECAT0_FMMU1 ((ECAT0_FMMU_Type *) ECAT0_FMMU1_BASE) |
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| #define | ECAT0_FMMU2 ((ECAT0_FMMU_Type *) ECAT0_FMMU2_BASE) |
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| #define | ECAT0_FMMU3 ((ECAT0_FMMU_Type *) ECAT0_FMMU3_BASE) |
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| #define | ECAT0_FMMU4 ((ECAT0_FMMU_Type *) ECAT0_FMMU4_BASE) |
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| #define | ECAT0_FMMU5 ((ECAT0_FMMU_Type *) ECAT0_FMMU5_BASE) |
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| #define | ECAT0_FMMU6 ((ECAT0_FMMU_Type *) ECAT0_FMMU6_BASE) |
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| #define | ECAT0_FMMU7 ((ECAT0_FMMU_Type *) ECAT0_FMMU7_BASE) |
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| #define | ECAT0_SM0 ((ECAT0_SM_Type *) ECAT0_SM0_BASE) |
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| #define | ECAT0_SM1 ((ECAT0_SM_Type *) ECAT0_SM1_BASE) |
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| #define | ECAT0_SM2 ((ECAT0_SM_Type *) ECAT0_SM2_BASE) |
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| #define | ECAT0_SM3 ((ECAT0_SM_Type *) ECAT0_SM3_BASE) |
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| #define | ECAT0_SM4 ((ECAT0_SM_Type *) ECAT0_SM4_BASE) |
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| #define | ECAT0_SM5 ((ECAT0_SM_Type *) ECAT0_SM5_BASE) |
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| #define | ECAT0_SM6 ((ECAT0_SM_Type *) ECAT0_SM6_BASE) |
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| #define | ECAT0_SM7 ((ECAT0_SM_Type *) ECAT0_SM7_BASE) |
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| #define | USB0 ((USB0_GLOBAL_TypeDef *) USB0_BASE) |
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| #define | USB0_EP0 ((USB0_EP0_TypeDef *) USB_EP_BASE) |
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| #define | USB0_EP1 ((USB0_EP_TypeDef *) USB0_EP1_BASE) |
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| #define | USB0_EP2 ((USB0_EP_TypeDef *) USB0_EP2_BASE) |
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| #define | USB0_EP3 ((USB0_EP_TypeDef *) USB0_EP3_BASE) |
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| #define | USB0_EP4 ((USB0_EP_TypeDef *) USB0_EP4_BASE) |
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| #define | USB0_EP5 ((USB0_EP_TypeDef *) USB0_EP5_BASE) |
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| #define | USB0_EP6 ((USB0_EP_TypeDef *) USB0_EP6_BASE) |
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| #define | USB0_CH0 ((USB0_CH_TypeDef *) USB0_CH0_BASE) |
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| #define | USB0_CH1 ((USB0_CH_TypeDef *) USB0_CH1_BASE) |
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| #define | USB0_CH2 ((USB0_CH_TypeDef *) USB0_CH2_BASE) |
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| #define | USB0_CH3 ((USB0_CH_TypeDef *) USB0_CH3_BASE) |
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| #define | USB0_CH4 ((USB0_CH_TypeDef *) USB0_CH4_BASE) |
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| #define | USB0_CH5 ((USB0_CH_TypeDef *) USB0_CH5_BASE) |
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| #define | USB0_CH6 ((USB0_CH_TypeDef *) USB0_CH6_BASE) |
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| #define | USB0_CH7 ((USB0_CH_TypeDef *) USB0_CH7_BASE) |
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| #define | USB0_CH8 ((USB0_CH_TypeDef *) USB0_CH8_BASE) |
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| #define | USB0_CH9 ((USB0_CH_TypeDef *) USB0_CH9_BASE) |
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| #define | USB0_CH10 ((USB0_CH_TypeDef *) USB0_CH10_BASE) |
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| #define | USB0_CH11 ((USB0_CH_TypeDef *) USB0_CH11_BASE) |
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| #define | USB0_CH12 ((USB0_CH_TypeDef *) USB0_CH12_BASE) |
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| #define | USB0_CH13 ((USB0_CH_TypeDef *) USB0_CH13_BASE) |
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| #define | USIC0 ((USIC_GLOBAL_TypeDef *) USIC0_BASE) |
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| #define | USIC1 ((USIC_GLOBAL_TypeDef *) USIC1_BASE) |
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| #define | USIC2 ((USIC_GLOBAL_TypeDef *) USIC2_BASE) |
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| #define | USIC0_CH0 ((USIC_CH_TypeDef *) USIC0_CH0_BASE) |
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| #define | USIC0_CH1 ((USIC_CH_TypeDef *) USIC0_CH1_BASE) |
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| #define | USIC1_CH0 ((USIC_CH_TypeDef *) USIC1_CH0_BASE) |
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| #define | USIC1_CH1 ((USIC_CH_TypeDef *) USIC1_CH1_BASE) |
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| #define | USIC2_CH0 ((USIC_CH_TypeDef *) USIC2_CH0_BASE) |
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| #define | USIC2_CH1 ((USIC_CH_TypeDef *) USIC2_CH1_BASE) |
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| #define | CAN ((CAN_GLOBAL_TypeDef *) CAN_BASE) |
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| #define | CAN_NODE0 ((CAN_NODE_TypeDef *) CAN_NODE0_BASE) |
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| #define | CAN_NODE1 ((CAN_NODE_TypeDef *) CAN_NODE1_BASE) |
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| #define | CAN_NODE2 ((CAN_NODE_TypeDef *) CAN_NODE2_BASE) |
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| #define | CAN_NODE3 ((CAN_NODE_TypeDef *) CAN_NODE3_BASE) |
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| #define | CAN_NODE4 ((CAN_NODE_TypeDef *) CAN_NODE4_BASE) |
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| #define | CAN_NODE5 ((CAN_NODE_TypeDef *) CAN_NODE5_BASE) |
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| #define | CAN_MO ((CAN_MO_CLUSTER_Type *) CAN_MO_BASE) |
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| #define | VADC ((VADC_GLOBAL_TypeDef *) VADC_BASE) |
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| #define | VADC_G0 ((VADC_G_TypeDef *) VADC_G0_BASE) |
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| #define | VADC_G1 ((VADC_G_TypeDef *) VADC_G1_BASE) |
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| #define | VADC_G2 ((VADC_G_TypeDef *) VADC_G2_BASE) |
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| #define | VADC_G3 ((VADC_G_TypeDef *) VADC_G3_BASE) |
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| #define | DSD ((DSD_GLOBAL_TypeDef *) DSD_BASE) |
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| #define | DSD_CH0 ((DSD_CH_TypeDef *) DSD_CH0_BASE) |
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| #define | DSD_CH1 ((DSD_CH_TypeDef *) DSD_CH1_BASE) |
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| #define | DSD_CH2 ((DSD_CH_TypeDef *) DSD_CH2_BASE) |
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| #define | DSD_CH3 ((DSD_CH_TypeDef *) DSD_CH3_BASE) |
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| #define | DAC ((DAC_GLOBAL_TypeDef *) DAC_BASE) |
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| #define | CCU40 ((CCU4_GLOBAL_TypeDef *) CCU40_BASE) |
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| #define | CCU41 ((CCU4_GLOBAL_TypeDef *) CCU41_BASE) |
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| #define | CCU42 ((CCU4_GLOBAL_TypeDef *) CCU42_BASE) |
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| #define | CCU43 ((CCU4_GLOBAL_TypeDef *) CCU43_BASE) |
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| #define | CCU40_CC40 ((CCU4_CC4_TypeDef *) CCU40_CC40_BASE) |
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| #define | CCU40_CC41 ((CCU4_CC4_TypeDef *) CCU40_CC41_BASE) |
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| #define | CCU40_CC42 ((CCU4_CC4_TypeDef *) CCU40_CC42_BASE) |
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| #define | CCU40_CC43 ((CCU4_CC4_TypeDef *) CCU40_CC43_BASE) |
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| #define | CCU41_CC40 ((CCU4_CC4_TypeDef *) CCU41_CC40_BASE) |
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| #define | CCU41_CC41 ((CCU4_CC4_TypeDef *) CCU41_CC41_BASE) |
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| #define | CCU41_CC42 ((CCU4_CC4_TypeDef *) CCU41_CC42_BASE) |
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| #define | CCU41_CC43 ((CCU4_CC4_TypeDef *) CCU41_CC43_BASE) |
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| #define | CCU42_CC40 ((CCU4_CC4_TypeDef *) CCU42_CC40_BASE) |
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| #define | CCU42_CC41 ((CCU4_CC4_TypeDef *) CCU42_CC41_BASE) |
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| #define | CCU42_CC42 ((CCU4_CC4_TypeDef *) CCU42_CC42_BASE) |
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| #define | CCU42_CC43 ((CCU4_CC4_TypeDef *) CCU42_CC43_BASE) |
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| #define | CCU43_CC40 ((CCU4_CC4_TypeDef *) CCU43_CC40_BASE) |
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| #define | CCU43_CC41 ((CCU4_CC4_TypeDef *) CCU43_CC41_BASE) |
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| #define | CCU43_CC42 ((CCU4_CC4_TypeDef *) CCU43_CC42_BASE) |
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| #define | CCU43_CC43 ((CCU4_CC4_TypeDef *) CCU43_CC43_BASE) |
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| #define | CCU80 ((CCU8_GLOBAL_TypeDef *) CCU80_BASE) |
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| #define | CCU81 ((CCU8_GLOBAL_TypeDef *) CCU81_BASE) |
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| #define | CCU80_CC80 ((CCU8_CC8_TypeDef *) CCU80_CC80_BASE) |
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| #define | CCU80_CC81 ((CCU8_CC8_TypeDef *) CCU80_CC81_BASE) |
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| #define | CCU80_CC82 ((CCU8_CC8_TypeDef *) CCU80_CC82_BASE) |
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| #define | CCU80_CC83 ((CCU8_CC8_TypeDef *) CCU80_CC83_BASE) |
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| #define | CCU81_CC80 ((CCU8_CC8_TypeDef *) CCU81_CC80_BASE) |
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| #define | CCU81_CC81 ((CCU8_CC8_TypeDef *) CCU81_CC81_BASE) |
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| #define | CCU81_CC82 ((CCU8_CC8_TypeDef *) CCU81_CC82_BASE) |
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| #define | CCU81_CC83 ((CCU8_CC8_TypeDef *) CCU81_CC83_BASE) |
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| #define | POSIF0 ((POSIF_GLOBAL_TypeDef *) POSIF0_BASE) |
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| #define | POSIF1 ((POSIF_GLOBAL_TypeDef *) POSIF1_BASE) |
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| #define | PORT0 ((PORT0_Type *) PORT0_BASE) |
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| #define | PORT1 ((PORT1_Type *) PORT1_BASE) |
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| #define | PORT2 ((PORT2_Type *) PORT2_BASE) |
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| #define | PORT3 ((PORT3_Type *) PORT3_BASE) |
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| #define | PORT4 ((PORT4_Type *) PORT4_BASE) |
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| #define | PORT5 ((PORT5_Type *) PORT5_BASE) |
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| #define | PORT6 ((PORT6_Type *) PORT6_BASE) |
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| #define | PORT7 ((PORT7_Type *) PORT7_BASE) |
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| #define | PORT8 ((PORT8_Type *) PORT8_BASE) |
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| #define | PORT9 ((PORT9_Type *) PORT9_BASE) |
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| #define | PORT14 ((PORT14_Type *) PORT14_BASE) |
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| #define | PORT15 ((PORT15_Type *) PORT15_BASE) |
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